[llvm] [AArch64][SVE2p1] Remove redundant PTESTs when predicate is a WHILEcc_x2 (PR #156478)

[Paul Walker via llvm-commits]

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@@ -20001,13 +20001,21 @@ static bool isPredicateCCSettingOp(SDValue N) {
       (N.getOpcode() == ISD::GET_ACTIVE_LANE_MASK) ||
       (N.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
        (N.getConstantOperandVal(0) == Intrinsic::aarch64_sve_whilege ||
+        N.getConstantOperandVal(0) == Intrinsic::aarch64_sve_whilege_x2 ||
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paulwalker-arm wrote:

Now that `isPredicateCCSettingOp` is returning true for multi-vector instructions I suspect its use within `performFirstTrueTestVectorCombine` will need to be rewritten as:
```
// Restricted the DAG combine to only cases where we're extracting the first
// result of a flag-setting operation.
if (!isPredicateCCSettingOp(N0) || N0.getResNo() != 0)
```
to ensure the combine does not trigger when extracting the first lane of the second result.

https://github.com/llvm/llvm-project/pull/156478