[llvm] [SelectionDAG][ARM] Propagate fast math flags in visitBRCOND (PR #156647)
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Thu Sep 4 04:15:14 PDT 2025
https://github.com/paperchalice updated https://github.com/llvm/llvm-project/pull/156647
>From c1b9fbf245cefe5122a4fe6e0548ef571152f459 Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Wed, 3 Sep 2025 19:29:19 +0800
Subject: [PATCH 1/4] [SelectionDAG][ARM] Propagate fast math flags in
visitBRCOND
---
llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 8 ++++----
llvm/lib/Target/ARM/ARMISelLowering.cpp | 11 +++++++----
2 files changed, 11 insertions(+), 8 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 15d7e7626942d..cc0bb950bae00 100644
--- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -19341,13 +19341,13 @@ SDValue DAGCombiner::visitBRCOND(SDNode *N) {
// MachineBasicBlock CFG, which is awkward.
// fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
- // on the target.
+ // on the target, also copy fast math flags.
if (N1.getOpcode() == ISD::SETCC &&
TLI.isOperationLegalOrCustom(ISD::BR_CC,
N1.getOperand(0).getValueType())) {
- return DAG.getNode(ISD::BR_CC, SDLoc(N), MVT::Other,
- Chain, N1.getOperand(2),
- N1.getOperand(0), N1.getOperand(1), N2);
+ return DAG.getNode(ISD::BR_CC, SDLoc(N), MVT::Other, Chain,
+ N1.getOperand(2), N1.getOperand(0), N1.getOperand(1), N2,
+ N1->getFlags());
}
if (N1.hasOneUse()) {
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index 830156359e9e8..c4fcfe21e15f5 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -5570,7 +5570,7 @@ static void expandf64Toi32(SDValue Op, SelectionDAG &DAG,
llvm_unreachable("Unknown VFP cmp argument!");
}
-/// OptimizeVFPBrcond - With -enable-unsafe-fp-math, it's legal to optimize some
+/// OptimizeVFPBrcond - With nnan, it's legal to optimize some
/// f32 and even f64 comparisons to integer ones.
SDValue
ARMTargetLowering::OptimizeVFPBrcond(SDValue Op, SelectionDAG &DAG) const {
@@ -5712,9 +5712,12 @@ SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, Cmp);
}
- if (getTargetMachine().Options.UnsafeFPMath &&
- (CC == ISD::SETEQ || CC == ISD::SETOEQ ||
- CC == ISD::SETNE || CC == ISD::SETUNE)) {
+ if (SDNodeFlags Flags = Op->getFlags();
+ (getTargetMachine().Options.UnsafeFPMath || Flags.hasNoNaNs()) &&
+ (DAG.getDenormalMode(MVT::f32) == DenormalMode::getIEEE() &&
+ DAG.getDenormalMode(MVT::f64) == DenormalMode::getIEEE()) &&
+ (CC == ISD::SETEQ || CC == ISD::SETOEQ || CC == ISD::SETNE ||
+ CC == ISD::SETUNE)) {
if (SDValue Result = OptimizeVFPBrcond(Op, DAG))
return Result;
}
>From 91c8ee3f03d831a00f3731fee94911dc42fe3b4f Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Thu, 4 Sep 2025 19:11:51 +0800
Subject: [PATCH 2/4] format
---
llvm/lib/Target/ARM/ARMISelLowering.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index c4fcfe21e15f5..cfd15284ea6dd 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -5715,7 +5715,7 @@ SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
if (SDNodeFlags Flags = Op->getFlags();
(getTargetMachine().Options.UnsafeFPMath || Flags.hasNoNaNs()) &&
(DAG.getDenormalMode(MVT::f32) == DenormalMode::getIEEE() &&
- DAG.getDenormalMode(MVT::f64) == DenormalMode::getIEEE()) &&
+ DAG.getDenormalMode(MVT::f64) == DenormalMode::getIEEE()) &&
(CC == ISD::SETEQ || CC == ISD::SETOEQ || CC == ISD::SETNE ||
CC == ISD::SETUNE)) {
if (SDValue Result = OptimizeVFPBrcond(Op, DAG))
>From 9c92aedaafa563fbcf5ebb6ff51579f97f94663a Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Thu, 4 Sep 2025 19:14:03 +0800
Subject: [PATCH 3/4] update test
---
llvm/test/CodeGen/ARM/fpcmp-opt.ll | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/llvm/test/CodeGen/ARM/fpcmp-opt.ll b/llvm/test/CodeGen/ARM/fpcmp-opt.ll
index 447e470b2363a..a40fd4244af17 100644
--- a/llvm/test/CodeGen/ARM/fpcmp-opt.ll
+++ b/llvm/test/CodeGen/ARM/fpcmp-opt.ll
@@ -1,4 +1,4 @@
-; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 -mattr=+vfp2 -enable-unsafe-fp-math %s -o - \
+; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 -mattr=+vfp2 %s -o - \
; RUN: | FileCheck %s
; rdar://7461510
@@ -42,7 +42,7 @@ entry:
; CHECK-NOT: vmrs
; CHECK: bne
%0 = load double, ptr %a
- %1 = fcmp oeq double %0, 0.000000e+00
+ %1 = fcmp nnan oeq double %0, 0.000000e+00
br i1 %1, label %bb1, label %bb2
bb1:
@@ -65,7 +65,7 @@ entry:
; CHECK-NOT: vmrs
; CHECK: bne
%0 = load float, ptr %a
- %1 = fcmp oeq float %0, 0.000000e+00
+ %1 = fcmp nnan oeq float %0, 0.000000e+00
br i1 %1, label %bb1, label %bb2
bb1:
>From b39a740f3c9f6eb9793eca971335adc3e9b7c5c9 Mon Sep 17 00:00:00 2001
From: PaperChalice <liujunchang97 at outlook.com>
Date: Thu, 4 Sep 2025 19:14:57 +0800
Subject: [PATCH 4/4] Move out flags
---
llvm/lib/Target/ARM/ARMISelLowering.cpp | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index cfd15284ea6dd..3058d93c4d2e2 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -5712,8 +5712,8 @@ SDValue ARMTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
return DAG.getNode(ARMISD::BRCOND, dl, MVT::Other, Chain, Dest, ARMcc, Cmp);
}
- if (SDNodeFlags Flags = Op->getFlags();
- (getTargetMachine().Options.UnsafeFPMath || Flags.hasNoNaNs()) &&
+ SDNodeFlags Flags = Op->getFlags();
+ if ((getTargetMachine().Options.UnsafeFPMath || Flags.hasNoNaNs()) &&
(DAG.getDenormalMode(MVT::f32) == DenormalMode::getIEEE() &&
DAG.getDenormalMode(MVT::f64) == DenormalMode::getIEEE()) &&
(CC == ISD::SETEQ || CC == ISD::SETOEQ || CC == ISD::SETNE ||
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