[llvm] [AArch64] Improve lowering for scalable masked interleaving stores (PR #156718)

[Cullen Rhodes via llvm-commits]

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@@ -0,0 +1,288 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
+
+define void @foo_st2_nxv16i8(<vscale x 16 x i1> %mask, <vscale x 16 x i8> %val1, <vscale x 16 x i8> %val2, ptr %p) {
+; CHECK-LABEL: foo_st2_nxv16i8:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    // kill: def $z1 killed $z1 killed $z0_z1 def $z0_z1
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c-rhodes wrote:

add `-asm-verbose=0` to get rid of all this MI metadata?

https://github.com/llvm/llvm-project/pull/156718