[llvm] [AArch64] Transform add(x, abs(y)) -> saba(x, y, 0) (PR #156615)

[Hari Limaye via llvm-commits]

hazzlim wrote:

> We generate the instructions directly in some of the raddhn patterns
> 
> ```
> def : Pat<(v8i8 (trunc (AArch64vlshr (add (v8i16 V128:$Vn), VImm0080), (i32 8)))),
>           (RADDHNv8i16_v8i8 V128:$Vn, (v8i16 (MOVIv2d_ns (i32 0))))>;
> ```
> 
> Generating two instructions in a pattern has it's down sides, so they both have advantages and disadvantages, but it is likely a little better than a new AArch64ISD node that isn't otherwise optimized.

Thanks for the pointer here - I have reverted the AArch64ISD node/combine changes and done this directly in tablegen. 

https://github.com/llvm/llvm-project/pull/156615