[llvm] AMDGPU: Change DS classes to use RegisterOperand parameters (PR #156580)

[Matt Arsenault via llvm-commits]

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@@ -1303,6 +1303,22 @@ def VGPRSrc_16 : RegisterOperand<VGPR_16> {
   let EncoderMethod = "getMachineOpValueT16";
 }
 
+// TODO: These cases should use default target alignment
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arsenm wrote:

All of the DecoderMethods set on the VGPRSrc* ops are just explicitly setting it to default value tablegen computes for the RegClass

https://github.com/llvm/llvm-project/pull/156580