[llvm] [RISCV] Fold (X & (3 << 30)) == 0 -> (srliw X, 30) == 0 for RV64. (PR #156769)
Sergei Barannikov via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 3 15:55:26 PDT 2025
================
@@ -64,3 +64,37 @@ define i1 @test4(i64 %x) {
%b = icmp eq i64 %a, 0
ret i1 %b
}
+
+define i1 @test5(i64 %x) {
+; RV32-LABEL: test5:
+; RV32: # %bb.0:
+; RV32-NEXT: srli a0, a0, 29
+; RV32-NEXT: seqz a0, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test5:
+; RV64: # %bb.0:
+; RV64-NEXT: srliw a0, a0, 29
+; RV64-NEXT: seqz a0, a0
+; RV64-NEXT: ret
+ %a = and i64 %x, 3758096384
+ %b = icmp eq i64 %a, 0
+ ret i1 %b
+}
+
+define i1 @test6(i64 %x) {
+; RV32-LABEL: test6:
+; RV32: # %bb.0:
+; RV32-NEXT: srli a0, a0, 29
+; RV32-NEXT: snez a0, a0
+; RV32-NEXT: ret
+;
+; RV64-LABEL: test6:
+; RV64: # %bb.0:
+; RV64-NEXT: srliw a0, a0, 29
+; RV64-NEXT: snez a0, a0
+; RV64-NEXT: ret
+ %a = and i64 %x, 3758096384
----------------
s-barannikov wrote:
Maybe I'm missing something, but this is 7 << 29 and the PR title mentions 3 << 30
https://github.com/llvm/llvm-project/pull/156769
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