[llvm] [WebAssembly] Fix lowering of (extending) loads from addrspace(1) globals (PR #155937)

[via llvm-commits]

QuantumSegfault wrote:

Okay, so examining the DAGs, it seems to be a problem with when our instructions our lowered. Without SIMD, the type-legalized DAG already has a `load anyext` + `and` that the optimization can combine into a zext load.

When SIMD128 is enabled, the load is not introduced into the full legalization phase (as the lowering of `extract_vector_elt`. It can't assume that ZEXTLOAD is legal (due being marked as Custom) and can't safely combine at this point.

So how can I tell it it's allowed to recombine after legalization, as long is the load is not from addrspace(1)?

---


### No SIMD
Type-legalized DAG
```
        t64: i32 = and t34, Constant:i32<15>
        t66: i32 = mul t64, Constant:i32<1>
    t67: i32 = add FrameIndex:i32<0>, t66
    t68: i32,ch = load<(load (s8)), anyext from i8> t101, t67, undef:i32
t59: i32 = and t68, Constant:i32<255>
```
Optimized type-legalized DAG
```
            t34: i32 = WebAssemblyISD::ARGUMENT TargetConstant:i32<16>
    t64: i32 = and t34, Constant:i32<15>
    t241: i32 = or disjoint FrameIndex:i32<0>, t64
t243: i32,ch = load<(load (s8)), zext from i8> t239, t241, undef:i32
```

Legalized DAG
```
        t34: i32 = WebAssemblyISD::ARGUMENT TargetConstant:i32<16>
    t64: i32 = and t34, Constant:i32<15>
    t241: i32 = or disjoint TargetFrameIndex:i32<0>, t64
t243: i32,ch = load<(load (s8)), zext from i8> t239, t241, undef:i32
```

----

### +SIMD128
Type-legalized DAG
```
    t8: i32 = extract_vector_elt t2, t4
t10: i32 = and t8, Constant:i32<255>
```

Optimized type-legalized DAG
```
    t8: i32 = extract_vector_elt t2, t4
t10: i32 = and t8, Constant:i32<255>
```

Legalized DAG
```
            t4: i32 = WebAssemblyISD::ARGUMENT TargetConstant:i32<1>
        t15: i32 = and t4, Constant:i32<15>
        t17: i32 = mul t15, Constant:i32<1>
    t18: i32 = add TargetFrameIndex:i32<0>, t17
    t19: i32,ch = load<(load (s8), align 4), anyext from i8> t13, t18, undef:i32
t10: i32 = and t19, Constant:i32<255>
```

Optimized legalized DAG
```
        t15: i32 = and t4, Constant:i32<15>
    t21: i32 = or disjoint TargetFrameIndex:i32<0>, t15
    t19: i32,ch = load<(load (s8), align 4), anyext from i8> t13, t21, undef:i32
t10: i32 = and t19, Constant:i32<255>
```

https://github.com/llvm/llvm-project/pull/155937