[llvm] 4d72bb3 - [PowerPC][NFC] Refactor PPCInstrFutureMMA.td to combine sections (#151194)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 3 10:48:36 PDT 2025
Author: Lei Huang
Date: 2025-09-03T13:48:32-04:00
New Revision: 4d72bb381bf2aff8aa84c0b70d8384b6fdf98d1d
URL: https://github.com/llvm/llvm-project/commit/4d72bb381bf2aff8aa84c0b70d8384b6fdf98d1d
DIFF: https://github.com/llvm/llvm-project/commit/4d72bb381bf2aff8aa84c0b70d8384b6fdf98d1d.diff
LOG: [PowerPC][NFC] Refactor PPCInstrFutureMMA.td to combine sections (#151194)
Combine same predicate sections into one and move some mma instructions
into the proper section.
Added:
Modified:
llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td b/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
index 4de1fc3d29cd7..94af8a65b8228 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td
@@ -8,6 +8,7 @@
//===----------------------------------------------------------------------===//
//
// This file describes the instructions introduced for the Future CPU for MMA.
+// Please reference "PPCInstrVSX.td" for file structure.
//
//===----------------------------------------------------------------------===//
@@ -390,7 +391,12 @@ class XX2Form_AT3_XB6_ID2_E1_BL2<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
let Inst{31} = 0;
}
-let Predicates = [IsISAFuture] in {
+//-------------------------- Instruction definitions -------------------------//
+// Predicate combinations available:
+// [MMA, IsISAFuture]
+// [MMA, PrefixInstrs, IsISAFuture]
+
+let Predicates = [MMA, IsISAFuture] in {
def DMXXEXTFDMR512 : XX3Form_AT3_XABp5_P1<60, 226,
(outs vsrprc:$XAp, vsrprc:$XBp),
(ins wacc:$AT),
@@ -437,188 +443,187 @@ let Predicates = [IsISAFuture] in {
def DMSETDMRZ : XForm_AT3<31, 2, 177, (outs dmr:$AT), (ins),
"dmsetdmrz $AT", NoItinerary,
[(set v1024i1:$AT, (int_ppc_mma_dmsetdmrz))]>;
-}
-
-// MMA+ accumulating/non-accumulating instructions.
-// DMXVI8GERX4, DMXVI8GERX4PP, PMDMXVI8GERX4, PMDMXVI8GERX4PP
-defm DMXVI8GERX4 : DMR_UM_M448_XOEO<59, 10, (ins vsrprc:$XAp, vsrc:$XB),
- "dmxvi8gerx4", "$AT, $XAp, $XB">;
-
-let Predicates = [MMA, IsISAFuture] in {
- def DMXVI8GERX4SPP :
- XX3Form_AT3_XAp5B6<59, 98, (outs dmr:$AT), (ins dmr:$ATi, vsrprc:$XAp, vsrc:$XB),
- "dmxvi8gerx4spp $AT, $XAp, $XB", IIC_VecGeneral, []>,
- RegConstraint<"$ATi = $AT">;
-}
+ // DMXVI8GERX4, DMXVI8GERX4PP, PMDMXVI8GERX4, PMDMXVI8GERX4PP
+ defm DMXVI8GERX4 : DMR_UM_M448_XOEO<59, 10, (ins vsrprc:$XAp, vsrc:$XB),
+ "dmxvi8gerx4", "$AT, $XAp, $XB">;
+
+ // DMXVBF16GERX2, DMXVBF16GERX2PP, DMXVBF16GERX2PN, dMXVBF16GERX2NP,
+ // DMXVBF16GERX2NN PMDMXVBF16GERX2, PMDMXVBF16GERX2PP, PMDMXVBF16GERX2PN,
+ // PMDMXVBF16GERX2NP, PMDMXVBF16GERX2NN
+ defm DMXVBF16GERX2
+ : DMR_NEG_UM_M284_XOXORf939a0<59, 74, (ins vsrprc:$XAp, vsrc:$XB),
+ "dmxvbf16gerx2", "$AT, $XAp, $XB">;
+
+ // DMXVF16GERX2, DMXVF16GERX2PP, DMXVF16GERX2PN, dMXVF16GERX2NP,
+ // DMXVF16GERX2NN PMDMXVF16GERX2, PMDMXVF16GERX2PP, PMDMXVF16GERX2PN,
+ // PMDMXVF16GERX2NP, PMDMXVF16GERX2NN
+ defm DMXVF16GERX2
+ : DMR_NEG_UM_M284_XOXORd11188<59, 66, (ins vsrprc:$XAp, vsrc:$XB),
+ "dmxvf16gerx2", "$AT, $XAp, $XB">;
+
+ // DMF cryptography [support] Instructions
+ def DMSHA2HASH
+ : XForm_AT3_T1_AB3<
+ 31, 14, 177, (outs dmr:$AT), (ins dmr:$ATi, dmr:$AB, u1imm:$T),
+ "dmsha2hash $AT, $AB, $T",
+ [(set v1024i1:$AT, (int_ppc_mma_dmsha2hash v1024i1:$ATi,
+ v1024i1:$AB, timm:$T))]>,
+ RegConstraint<"$ATi = $AT">;
+ def DMSHA3HASH
+ : XForm_ATp2_SR5<31, 15, 177, (outs dmrp:$ATp),
+ (ins dmrp:$ATpi, u5imm:$SR), "dmsha3hash $ATp, $SR",
+ [(set v2048i1:$ATp,
+ (int_ppc_mma_dmsha3hash v2048i1:$ATpi, timm:$SR))]>,
+ RegConstraint<"$ATpi = $ATp">;
+ def DMXXSHAPAD
+ : XX2Form_AT3_XB6_ID2_E1_BL2<60, 421, (outs dmr:$AT),
+ (ins dmr:$ATi, vsrc:$XB, u2imm:$ID, u1imm:$E,
+ u2imm:$BL),
+ "dmxxshapad $AT, $XB, $ID, $E, $BL", []>,
+ RegConstraint<"$ATi = $AT">;
+
+ // MMA+ accumulating/non-accumulating instructions.
+ def DMXVI8GERX4SPP
+ : XX3Form_AT3_XAp5B6<59, 98, (outs dmr:$AT),
+ (ins dmr:$ATi, vsrprc:$XAp, vsrc:$XB),
+ "dmxvi8gerx4spp $AT, $XAp, $XB", IIC_VecGeneral, []>,
+ RegConstraint<"$ATi = $AT">;
+
+} // End of [MMA, IsISAFuture]
let Predicates = [MMA, PrefixInstrs, IsISAFuture] in {
- def PMDMXVI8GERX4SPP :
- MMIRR_XX3Form_X8YP4_XAp5B6<59, 98, (outs dmr:$AT),
- (ins dmr:$ATi, vsrprc:$XAp,vsrc:$XB, u8imm:$XMSK,
- u4imm:$YMSK, u4imm:$PMSK),
- "pmdmxvi8gerx4spp $AT, $XAp, $XB, $XMSK, $YMSK, $PMSK",
- IIC_VecGeneral, []>,
- RegConstraint<"$ATi = $AT">;
+ def PMDMXVI8GERX4SPP
+ : MMIRR_XX3Form_X8YP4_XAp5B6<
+ 59, 98, (outs dmr:$AT),
+ (ins dmr:$ATi, vsrprc:$XAp, vsrc:$XB, u8imm:$XMSK, u4imm:$YMSK,
+ u4imm:$PMSK),
+ "pmdmxvi8gerx4spp $AT, $XAp, $XB, $XMSK, $YMSK, $PMSK",
+ IIC_VecGeneral, []>,
+ RegConstraint<"$ATi = $AT">;
}
-// DMXVBF16GERX2, DMXVBF16GERX2PP, DMXVBF16GERX2PN, dMXVBF16GERX2NP, DMXVBF16GERX2NN
-// PMDMXVBF16GERX2, PMDMXVBF16GERX2PP, PMDMXVBF16GERX2PN, PMDMXVBF16GERX2NP, PMDMXVBF16GERX2NN
-defm DMXVBF16GERX2 : DMR_NEG_UM_M284_XOXORf939a0<59, 74, (ins vsrprc:$XAp, vsrc:$XB),
- "dmxvbf16gerx2", "$AT, $XAp, $XB">;
-
-// DMXVF16GERX2, DMXVF16GERX2PP, DMXVF16GERX2PN, dMXVF16GERX2NP, DMXVF16GERX2NN
-// PMDMXVF16GERX2, PMDMXVF16GERX2PP, PMDMXVF16GERX2PN, PMDMXVF16GERX2NP, PMDMXVF16GERX2NN
-defm DMXVF16GERX2 : DMR_NEG_UM_M284_XOXORd11188<59, 66, (ins vsrprc:$XAp, vsrc:$XB),
- "dmxvf16gerx2", "$AT, $XAp, $XB">;
-
-// DMF cryptography [support] Instructions
-let Predicates = [IsISAFuture] in {
- def DMSHA2HASH :
- XForm_AT3_T1_AB3<31, 14, 177, (outs dmr:$AT), (ins dmr:$ATi, dmr:$AB, u1imm:$T),
- "dmsha2hash $AT, $AB, $T",
- [(set v1024i1:$AT, (int_ppc_mma_dmsha2hash v1024i1:$ATi, v1024i1:$AB, timm:$T))]>,
- RegConstraint<"$ATi = $AT">;
-
- def DMSHA3HASH :
- XForm_ATp2_SR5<31, 15, 177, (outs dmrp:$ATp), (ins dmrp:$ATpi , u5imm:$SR),
- "dmsha3hash $ATp, $SR",
- [(set v2048i1:$ATp, (int_ppc_mma_dmsha3hash v2048i1:$ATpi, timm:$SR))]>,
- RegConstraint<"$ATpi = $ATp">;
-
- def DMXXSHAPAD :
- XX2Form_AT3_XB6_ID2_E1_BL2<60, 421, (outs dmr:$AT),
- (ins dmr:$ATi, vsrc:$XB, u2imm:$ID, u1imm:$E, u2imm:$BL),
- "dmxxshapad $AT, $XB, $ID, $E, $BL", []>,
- RegConstraint<"$ATi = $AT">;
-}
+//---------------------------- Anonymous Patterns ----------------------------//
+// Predicate combinations available:
+// [MMA, IsISAFuture]
+// [MMA, PrefixInstrs, IsISAFuture]
-// MMA+ Intrinsics
let Predicates = [MMA, IsISAFuture] in {
- def : Pat<(v1024i1 (int_ppc_mma_dmxvi8gerx4 v256i1:$XAp, v16i8:$XB)),
+ // MMA+ Intrinsics
+ def : Pat<(v1024i1(int_ppc_mma_dmxvi8gerx4 v256i1:$XAp, v16i8:$XB)),
(DMXVI8GERX4 $XAp, RCCp.BToVSRC)>;
- def : Pat<(v1024i1 (int_ppc_mma_dmxvi8gerx4pp v1024i1:$ATi, v256i1:$XAp, v16i8:$XB)),
+ def : Pat<(v1024i1(int_ppc_mma_dmxvi8gerx4pp v1024i1:$ATi, v256i1:$XAp,
+ v16i8:$XB)),
(DMXVI8GERX4PP $ATi, $XAp, RCCp.BToVSRC)>;
-
- def : Pat<(v1024i1 (int_ppc_mma_dmxvi8gerx4spp v1024i1:$ATi, v256i1:$XAp, v16i8:$XB)),
+ def : Pat<(v1024i1(int_ppc_mma_dmxvi8gerx4spp v1024i1:$ATi, v256i1:$XAp,
+ v16i8:$XB)),
(DMXVI8GERX4SPP $ATi, $XAp, RCCp.BToVSRC)>;
-
- def : Pat<(v1024i1 (int_ppc_mma_dmxvbf16gerx2 v256i1:$XAp, v16i8:$XB)),
+ def : Pat<(v1024i1(int_ppc_mma_dmxvbf16gerx2 v256i1:$XAp, v16i8:$XB)),
(DMXVBF16GERX2 $XAp, RCCp.BToVSRC)>;
-
- def : Pat<(v1024i1 (int_ppc_mma_dmxvbf16gerx2pp v1024i1:$ATi, v256i1:$XAp, v16i8:$XB)),
+ def : Pat<(v1024i1(int_ppc_mma_dmxvbf16gerx2pp v1024i1:$ATi, v256i1:$XAp,
+ v16i8:$XB)),
(DMXVBF16GERX2PP $ATi, $XAp, RCCp.BToVSRC)>;
-
- def : Pat<(v1024i1 (int_ppc_mma_dmxvbf16gerx2pn v1024i1:$ATi, v256i1:$XAp, v16i8:$XB)),
+ def : Pat<(v1024i1(int_ppc_mma_dmxvbf16gerx2pn v1024i1:$ATi, v256i1:$XAp,
+ v16i8:$XB)),
(DMXVBF16GERX2PN $ATi, $XAp, RCCp.BToVSRC)>;
-
- def : Pat<(v1024i1 (int_ppc_mma_dmxvbf16gerx2np v1024i1:$ATi, v256i1:$XAp, v16i8:$XB)),
+ def : Pat<(v1024i1(int_ppc_mma_dmxvbf16gerx2np v1024i1:$ATi, v256i1:$XAp,
+ v16i8:$XB)),
(DMXVBF16GERX2NP $ATi, $XAp, RCCp.BToVSRC)>;
-
- def : Pat<(v1024i1 (int_ppc_mma_dmxvbf16gerx2nn v1024i1:$ATi, v256i1:$XAp, v16i8:$XB)),
+ def : Pat<(v1024i1(int_ppc_mma_dmxvbf16gerx2nn v1024i1:$ATi, v256i1:$XAp,
+ v16i8:$XB)),
(DMXVBF16GERX2NN $ATi, $XAp, RCCp.BToVSRC)>;
-
- def : Pat<(v1024i1 (int_ppc_mma_dmxvf16gerx2 v256i1:$XAp, v16i8:$XB)),
+ def : Pat<(v1024i1(int_ppc_mma_dmxvf16gerx2 v256i1:$XAp, v16i8:$XB)),
(DMXVF16GERX2 $XAp, RCCp.BToVSRC)>;
-
- def : Pat<(v1024i1 (int_ppc_mma_dmxvf16gerx2pp v1024i1:$ATi, v256i1:$XAp, v16i8:$XB)),
+ def : Pat<(v1024i1(int_ppc_mma_dmxvf16gerx2pp v1024i1:$ATi, v256i1:$XAp,
+ v16i8:$XB)),
(DMXVF16GERX2PP $ATi, $XAp, RCCp.BToVSRC)>;
-
- def : Pat<(v1024i1 (int_ppc_mma_dmxvf16gerx2pn v1024i1:$ATi, v256i1:$XAp, v16i8:$XB)),
+ def : Pat<(v1024i1(int_ppc_mma_dmxvf16gerx2pn v1024i1:$ATi, v256i1:$XAp,
+ v16i8:$XB)),
(DMXVF16GERX2PN $ATi, $XAp, RCCp.BToVSRC)>;
-
- def : Pat<(v1024i1 (int_ppc_mma_dmxvf16gerx2np v1024i1:$ATi, v256i1:$XAp, v16i8:$XB)),
+ def : Pat<(v1024i1(int_ppc_mma_dmxvf16gerx2np v1024i1:$ATi, v256i1:$XAp,
+ v16i8:$XB)),
(DMXVF16GERX2NP $ATi, $XAp, RCCp.BToVSRC)>;
-
- def : Pat<(v1024i1 (int_ppc_mma_dmxvf16gerx2nn v1024i1:$ATi, v256i1:$XAp, v16i8:$XB)),
+ def : Pat<(v1024i1(int_ppc_mma_dmxvf16gerx2nn v1024i1:$ATi, v256i1:$XAp,
+ v16i8:$XB)),
(DMXVF16GERX2NN $ATi, $XAp, RCCp.BToVSRC)>;
+
+ // Cryptography Intrinsic
+ def : Pat<(v1024i1(int_ppc_mma_dmxxshapad v1024i1:$ATi, v16i8:$XB, timm:$ID,
+ timm:$E, timm:$BL)),
+ (DMXXSHAPAD $ATi, RCCp.BToVSRC, $ID, $E, $BL)>;
}
let Predicates = [MMA, PrefixInstrs, IsISAFuture] in {
- def : Pat<(v1024i1 (int_ppc_mma_pmdmxvi8gerx4 v256i1:$XAp, v16i8:$XB, Msk8Imm:$XMSK,
- Msk4Imm:$YMSK, Msk4Imm:$PMSK)),
- (PMDMXVI8GERX4 $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
- Msk4Imm:$YMSK, Msk4Imm:$PMSK)>;
-
- def : Pat<(v1024i1 (int_ppc_mma_pmdmxvi8gerx4pp v1024i1:$ATi, v256i1:$XAp, v16i8:$XB,
- Msk8Imm:$XMSK, Msk4Imm:$YMSK,
- Msk4Imm:$PMSK)),
+ def : Pat<(v1024i1(int_ppc_mma_pmdmxvi8gerx4 v256i1:$XAp, v16i8:$XB,
+ Msk8Imm:$XMSK, Msk4Imm:$YMSK, Msk4Imm:$PMSK)),
+ (PMDMXVI8GERX4 $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK, Msk4Imm:$YMSK,
+ Msk4Imm:$PMSK)>;
+
+ def : Pat<(v1024i1(int_ppc_mma_pmdmxvi8gerx4pp v1024i1:$ATi, v256i1:$XAp,
+ v16i8:$XB, Msk8Imm:$XMSK, Msk4Imm:$YMSK, Msk4Imm:$PMSK)),
(PMDMXVI8GERX4PP $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
- Msk4Imm:$YMSK, Msk4Imm:$PMSK)>;
+ Msk4Imm:$YMSK, Msk4Imm:$PMSK)>;
- def : Pat<(v1024i1 (int_ppc_mma_pmdmxvi8gerx4spp v1024i1:$ATi, v256i1:$XAp, v16i8:$XB,
- Msk8Imm:$XMSK, Msk4Imm:$YMSK,
- Msk4Imm:$PMSK)),
+ def : Pat<(v1024i1(int_ppc_mma_pmdmxvi8gerx4spp v1024i1:$ATi, v256i1:$XAp,
+ v16i8:$XB, Msk8Imm:$XMSK, Msk4Imm:$YMSK, Msk4Imm:$PMSK)),
(PMDMXVI8GERX4SPP $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
- Msk4Imm:$YMSK, Msk4Imm:$PMSK)>;
+ Msk4Imm:$YMSK, Msk4Imm:$PMSK)>;
- def : Pat<(v1024i1 (int_ppc_mma_pmdmxvbf16gerx2 v256i1:$XAp, v16i8:$XB, Msk8Imm:$XMSK,
- Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
- (PMDMXVBF16GERX2 $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
- Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
+ def : Pat<(v1024i1(int_ppc_mma_pmdmxvbf16gerx2 v256i1:$XAp, v16i8:$XB,
+ Msk8Imm:$XMSK, Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
+ (PMDMXVBF16GERX2 $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK, Msk4Imm:$YMSK,
+ Msk2Imm:$PMSK)>;
- def : Pat<(v1024i1 (int_ppc_mma_pmdmxvbf16gerx2pp v1024i1:$ATi, v256i1:$XAp, v16i8:$XB,
- Msk8Imm:$XMSK, Msk4Imm:$YMSK,
- Msk2Imm:$PMSK)),
+ def : Pat<(v1024i1(int_ppc_mma_pmdmxvbf16gerx2pp v1024i1:$ATi, v256i1:$XAp,
+ v16i8:$XB, Msk8Imm:$XMSK, Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
(PMDMXVBF16GERX2PP $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
- Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
+ Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
- def : Pat<(v1024i1 (int_ppc_mma_pmdmxvbf16gerx2pn v1024i1:$ATi, v256i1:$XAp, v16i8:$XB,
- Msk8Imm:$XMSK, Msk4Imm:$YMSK,
- Msk2Imm:$PMSK)),
+ def : Pat<(v1024i1(int_ppc_mma_pmdmxvbf16gerx2pn v1024i1:$ATi, v256i1:$XAp,
+ v16i8:$XB, Msk8Imm:$XMSK, Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
(PMDMXVBF16GERX2PN $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
- Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
+ Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
- def : Pat<(v1024i1 (int_ppc_mma_pmdmxvbf16gerx2np v1024i1:$ATi, v256i1:$XAp, v16i8:$XB,
- Msk8Imm:$XMSK, Msk4Imm:$YMSK,
- Msk2Imm:$PMSK)),
+ def : Pat<(v1024i1(int_ppc_mma_pmdmxvbf16gerx2np v1024i1:$ATi, v256i1:$XAp,
+ v16i8:$XB, Msk8Imm:$XMSK, Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
(PMDMXVBF16GERX2NP $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
- Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
+ Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
- def : Pat<(v1024i1 (int_ppc_mma_pmdmxvbf16gerx2nn v1024i1:$ATi, v256i1:$XAp, v16i8:$XB,
- Msk8Imm:$XMSK, Msk4Imm:$YMSK,
- Msk2Imm:$PMSK)),
+ def : Pat<(v1024i1(int_ppc_mma_pmdmxvbf16gerx2nn v1024i1:$ATi, v256i1:$XAp,
+ v16i8:$XB, Msk8Imm:$XMSK, Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
(PMDMXVBF16GERX2NN $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
- Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
+ Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
- def : Pat<(v1024i1 (int_ppc_mma_pmdmxvf16gerx2 v256i1:$XAp, v16i8:$XB, Msk8Imm:$XMSK,
- Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
- (PMDMXVF16GERX2 $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
- Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
+ def : Pat<(v1024i1(int_ppc_mma_pmdmxvf16gerx2 v256i1:$XAp, v16i8:$XB,
+ Msk8Imm:$XMSK, Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
+ (PMDMXVF16GERX2 $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK, Msk4Imm:$YMSK,
+ Msk2Imm:$PMSK)>;
- def : Pat<(v1024i1 (int_ppc_mma_pmdmxvf16gerx2pp v1024i1:$ATi, v256i1:$XAp, v16i8:$XB,
- Msk8Imm:$XMSK, Msk4Imm:$YMSK,
- Msk2Imm:$PMSK)),
+ def : Pat<(v1024i1(int_ppc_mma_pmdmxvf16gerx2pp v1024i1:$ATi, v256i1:$XAp,
+ v16i8:$XB, Msk8Imm:$XMSK, Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
(PMDMXVF16GERX2PP $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
- Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
+ Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
- def : Pat<(v1024i1 (int_ppc_mma_pmdmxvf16gerx2pn v1024i1:$ATi, v256i1:$XAp, v16i8:$XB,
- Msk8Imm:$XMSK, Msk4Imm:$YMSK,
- Msk2Imm:$PMSK)),
+ def : Pat<(v1024i1(int_ppc_mma_pmdmxvf16gerx2pn v1024i1:$ATi, v256i1:$XAp,
+ v16i8:$XB, Msk8Imm:$XMSK, Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
(PMDMXVF16GERX2PN $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
- Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
+ Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
- def : Pat<(v1024i1 (int_ppc_mma_pmdmxvf16gerx2np v1024i1:$ATi, v256i1:$XAp, v16i8:$XB,
- Msk8Imm:$XMSK, Msk4Imm:$YMSK,
- Msk2Imm:$PMSK)),
+ def : Pat<(v1024i1(int_ppc_mma_pmdmxvf16gerx2np v1024i1:$ATi, v256i1:$XAp,
+ v16i8:$XB, Msk8Imm:$XMSK, Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
(PMDMXVF16GERX2NP $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
- Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
+ Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
- def : Pat<(v1024i1 (int_ppc_mma_pmdmxvf16gerx2nn v1024i1:$ATi, v256i1:$XAp, v16i8:$XB,
- Msk8Imm:$XMSK, Msk4Imm:$YMSK,
- Msk2Imm:$PMSK)),
+ def : Pat<(v1024i1(int_ppc_mma_pmdmxvf16gerx2nn v1024i1:$ATi, v256i1:$XAp,
+ v16i8:$XB, Msk8Imm:$XMSK, Msk4Imm:$YMSK, Msk2Imm:$PMSK)),
(PMDMXVF16GERX2NN $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
- Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
+ Msk4Imm:$YMSK, Msk2Imm:$PMSK)>;
}
-// Cryptography Intrinsic
-let Predicates = [IsISAFuture] in {
- def : Pat<(v1024i1 (int_ppc_mma_dmxxshapad v1024i1:$ATi, v16i8:$XB, timm:$ID,
- timm:$E, timm:$BL)), (DMXXSHAPAD $ATi, RCCp.BToVSRC, $ID, $E, $BL)>;
-}
-// MMA+ Instruction aliases
-let Predicates = [IsISAFuture] in {
+//---------------------------- Instruction aliases ---------------------------//
+
+let Predicates = [MMA, IsISAFuture] in {
def : InstAlias<"dmsha256hash $AT, $AB",
(DMSHA2HASH dmr:$AT, dmr:$AB, 0)>;
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