[llvm] [X86] Recognise VPMADD52L pattern with AVX512IFMA/AVXIFMA (#153787) (PR #156714)
Simon Pilgrim via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 3 10:09:11 PDT 2025
================
@@ -57966,6 +57966,51 @@ static SDValue pushAddIntoCmovOfConsts(SDNode *N, const SDLoc &DL,
Cmov.getOperand(3));
}
+static SDValue matchIntegerMultiplyAdd(SDNode *N, SelectionDAG &DAG,
+ SDValue Op0, SDValue Op1,
+ const SDLoc &DL, EVT VT,
+ const X86Subtarget &Subtarget) {
+ using namespace SDPatternMatch;
+ if (!VT.isVector() || VT.getScalarType() != MVT::i64 ||
+ !Subtarget.hasAVX512() ||
+ (!Subtarget.hasAVXIFMA() && !Subtarget.hasIFMA()) ||
+ !DAG.getTargetLoweringInfo().isOperationLegalOrCustom(X86ISD::VPMADD52L,
+ VT) ||
+ Op0.getValueType() != VT || Op1.getValueType() != VT)
+ return SDValue();
+
+ SDValue X, Y, Acc;
+ if (!sd_match(N, m_Add(m_Mul(m_Value(X), m_Value(Y)), m_Value(Acc))))
+ return SDValue();
+
+ auto CheckMulOperand = [&DAG, &VT](const SDValue &M, SDValue &Xval,
----------------
RKSimon wrote:
Do you need all this? Surely you just need to check that the knownbits of X, Y and KnownBits::mul(X,y) are all known zero in the upper 12 bits?
https://github.com/llvm/llvm-project/pull/156714
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