[llvm] [X86][GlobalISel] Added support for llvm.set.rounding (PR #156591)
via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 3 09:03:53 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-globalisel
Author: None (JaydeepChauhan14)
<details>
<summary>Changes</summary>
- This implementation is adapted from **SDAG X86TargetLowering::LowerSET_ROUNDING**.
---
Patch is 32.85 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/156591.diff
12 Files Affected:
- (modified) llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h (+5)
- (modified) llvm/include/llvm/Support/TargetOpcodes.def (+1)
- (modified) llvm/include/llvm/Target/GenericOpcodes.td (+6)
- (modified) llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp (+3)
- (modified) llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp (+115-1)
- (modified) llvm/lib/Target/X86/GISel/X86LegalizerInfo.h (+3)
- (modified) llvm/lib/Target/X86/X86InstrGISel.td (+8)
- (modified) llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir (+3)
- (modified) llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir (+3)
- (modified) llvm/test/CodeGen/X86/isel-llvm.set.rounding.ll (+340-8)
- (modified) llvm/test/TableGen/FixedLenDecoderEmitter/big-filter.td (+2-2)
- (modified) llvm/test/TableGen/GlobalISelEmitter/GlobalISelEmitter.td (+1-1)
``````````diff
diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
index 99d3cd0aac85c..0b6033b4ba60a 100644
--- a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
+++ b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h
@@ -2463,6 +2463,11 @@ class LLVM_ABI MachineIRBuilder {
return buildInstr(TargetOpcode::G_GET_ROUNDING, {Dst}, {});
}
+ /// Build and insert G_SET_ROUNDING
+ MachineInstrBuilder buildSetRounding(const SrcOp &Src) {
+ return buildInstr(TargetOpcode::G_SET_ROUNDING, {}, {Src});
+ }
+
virtual MachineInstrBuilder
buildInstr(unsigned Opc, ArrayRef<DstOp> DstOps, ArrayRef<SrcOp> SrcOps,
std::optional<unsigned> Flags = std::nullopt);
diff --git a/llvm/include/llvm/Support/TargetOpcodes.def b/llvm/include/llvm/Support/TargetOpcodes.def
index b905576b61791..7710e2fc2f22b 100644
--- a/llvm/include/llvm/Support/TargetOpcodes.def
+++ b/llvm/include/llvm/Support/TargetOpcodes.def
@@ -745,6 +745,7 @@ HANDLE_TARGET_OPCODE(G_SET_FPMODE)
HANDLE_TARGET_OPCODE(G_RESET_FPMODE)
HANDLE_TARGET_OPCODE(G_GET_ROUNDING)
+HANDLE_TARGET_OPCODE(G_SET_ROUNDING)
/// Generic pointer offset
HANDLE_TARGET_OPCODE(G_PTR_ADD)
diff --git a/llvm/include/llvm/Target/GenericOpcodes.td b/llvm/include/llvm/Target/GenericOpcodes.td
index ce4750db88c9a..733d10b1c5f3c 100644
--- a/llvm/include/llvm/Target/GenericOpcodes.td
+++ b/llvm/include/llvm/Target/GenericOpcodes.td
@@ -1273,6 +1273,12 @@ def G_GET_ROUNDING : GenericInstruction {
let hasSideEffects = true;
}
+def G_SET_ROUNDING : GenericInstruction {
+ let OutOperandList = (outs);
+ let InOperandList = (ins type0:$src);
+ let hasSideEffects = true;
+}
+
//------------------------------------------------------------------------------
// Memory ops
//------------------------------------------------------------------------------
diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
index 541269ab6bfce..dbf482dba7c44 100644
--- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp
@@ -2607,6 +2607,9 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID,
case Intrinsic::get_rounding:
MIRBuilder.buildGetRounding(getOrCreateVReg(CI));
return true;
+ case Intrinsic::set_rounding:
+ MIRBuilder.buildSetRounding(getOrCreateVReg(*CI.getOperand(0)));
+ return true;
case Intrinsic::vscale: {
MIRBuilder.buildVScale(getOrCreateVReg(CI), 1);
return true;
diff --git a/llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp b/llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
index 7fe58539cd4ec..6a63cb327b783 100644
--- a/llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
+++ b/llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
@@ -21,6 +21,7 @@
#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/DerivedTypes.h"
+#include "llvm/IR/IntrinsicsX86.h"
#include "llvm/IR/Type.h"
using namespace llvm;
@@ -109,7 +110,8 @@ X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI,
.legalFor(HasSSE2 || UseX87, {s64})
.legalFor(UseX87, {s80});
- getActionDefinitionsBuilder(G_GET_ROUNDING).customFor({s32});
+ getActionDefinitionsBuilder({G_GET_ROUNDING, G_SET_ROUNDING})
+ .customFor({s32});
// merge/unmerge
for (unsigned Op : {G_MERGE_VALUES, G_UNMERGE_VALUES}) {
@@ -616,6 +618,8 @@ bool X86LegalizerInfo::legalizeCustom(LegalizerHelper &Helper, MachineInstr &MI,
return legalizeFPTOSI(MI, MRI, Helper);
case TargetOpcode::G_GET_ROUNDING:
return legalizeGETROUNDING(MI, MRI, Helper);
+ case TargetOpcode::G_SET_ROUNDING:
+ return legalizeSETROUNDING(MI, MRI, Helper);
}
llvm_unreachable("expected switch to return");
}
@@ -858,6 +862,116 @@ bool X86LegalizerInfo::legalizeGETROUNDING(MachineInstr &MI,
return true;
}
+bool X86LegalizerInfo::legalizeSETROUNDING(MachineInstr &MI,
+ MachineRegisterInfo &MRI,
+ LegalizerHelper &Helper) const {
+ MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
+ MachineFunction &MF = MIRBuilder.getMF();
+ Register Src = MI.getOperand(0).getReg();
+ const LLT s8 = LLT::scalar(8);
+ const LLT s16 = LLT::scalar(16);
+ const LLT s32 = LLT::scalar(32);
+
+ // Allocate stack slot for control word and MXCSR (4 bytes).
+ int MemSize = 4;
+ Align Alignment = Align(4);
+ MachinePointerInfo PtrInfo;
+ auto StackTemp = Helper.createStackTemporary(TypeSize::getFixed(MemSize),
+ Alignment, PtrInfo);
+ Register StackPtr = StackTemp.getReg(0);
+
+ auto StoreMMO =
+ MF.getMachineMemOperand(PtrInfo, MachineMemOperand::MOStore, 2, Align(2));
+ MIRBuilder.buildInstr(X86::G_FNSTCW16)
+ .addUse(StackPtr)
+ .addMemOperand(StoreMMO);
+
+ auto LoadMMO =
+ MF.getMachineMemOperand(PtrInfo, MachineMemOperand::MOLoad, 2, Align(2));
+ auto CWD16 = MIRBuilder.buildLoad(s16, StackPtr, *LoadMMO);
+
+ // Clear RM field (bits 11:10)
+ auto ClearedCWD =
+ MIRBuilder.buildAnd(s16, CWD16, MIRBuilder.buildConstant(s16, 0xf3ff));
+
+ // Convert Src (rounding mode) to bits for control word
+ // (0xc9 << (2 * Src + 4)) & 0xc00
+ LLT SrcTy = MRI.getType(Src);
+ Register Src32;
+ if (SrcTy.getSizeInBits() < 32)
+ Src32 = MIRBuilder.buildZExt(s32, Src).getReg(0);
+ else if (SrcTy.getSizeInBits() > 32)
+ Src32 = MIRBuilder.buildTrunc(s32, Src).getReg(0);
+ else
+ Src32 = Src;
+ auto ShiftAmt = MIRBuilder.buildAdd(
+ s32, MIRBuilder.buildShl(s32, Src32, MIRBuilder.buildConstant(s32, 1)),
+ MIRBuilder.buildConstant(s32, 4));
+ auto ShiftAmt8 = MIRBuilder.buildTrunc(s8, ShiftAmt);
+ auto Shifted =
+ MIRBuilder.buildShl(s16, MIRBuilder.buildConstant(s16, 0xc9), ShiftAmt8);
+ auto RMBits =
+ MIRBuilder.buildAnd(s16, Shifted, MIRBuilder.buildConstant(s16, 0xc00));
+
+ // Update rounding mode bits
+ auto NewCWD = MIRBuilder.buildOr(s16, ClearedCWD, RMBits);
+
+ // Store new FP Control Word to stack
+ auto StoreNewMMO =
+ MF.getMachineMemOperand(PtrInfo, MachineMemOperand::MOStore, 2, Align(2));
+ MIRBuilder.buildStore(NewCWD, StackPtr, *StoreNewMMO);
+
+ // Load FP control word from the slot using G_FLDCW16
+ auto LoadNewMMO =
+ MF.getMachineMemOperand(PtrInfo, MachineMemOperand::MOLoad, 2, Align(2));
+ MIRBuilder.buildInstr(X86::G_FLDCW16)
+ .addUse(StackPtr)
+ .addMemOperand(LoadNewMMO);
+
+ if (Subtarget.hasSSE1()) {
+ // Store MXCSR to stack (use STMXCSR)
+ auto StoreMXCSRMMO = MF.getMachineMemOperand(
+ PtrInfo, MachineMemOperand::MOStore, 4, Align(4));
+ MIRBuilder.buildInstr(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS)
+ .addIntrinsicID(Intrinsic::x86_sse_stmxcsr)
+ .addUse(StackPtr)
+ .addMemOperand(StoreMXCSRMMO);
+
+ // Load MXCSR from stack
+ auto LoadMXCSRMMO = MF.getMachineMemOperand(
+ PtrInfo, MachineMemOperand::MOLoad, 4, Align(4));
+ auto MXCSR = MIRBuilder.buildLoad(s32, StackPtr, *LoadMXCSRMMO);
+
+ // Clear RM field (bits 14:13)
+ auto ClearedMXCSR = MIRBuilder.buildAnd(
+ s32, MXCSR, MIRBuilder.buildConstant(s32, 0xffff9fff));
+
+ // Shift x87 RM bits from 11:10 to 14:13
+ auto RMBits32 = MIRBuilder.buildZExt(s32, RMBits);
+ auto MXCSRRMBits =
+ MIRBuilder.buildShl(s32, RMBits32, MIRBuilder.buildConstant(s32, 3));
+
+ // Update rounding mode bits
+ auto NewMXCSR = MIRBuilder.buildOr(s32, ClearedMXCSR, MXCSRRMBits);
+
+ // Store new MXCSR to stack
+ auto StoreNewMXCSRMMO = MF.getMachineMemOperand(
+ PtrInfo, MachineMemOperand::MOStore, 4, Align(4));
+ MIRBuilder.buildStore(NewMXCSR, StackPtr, *StoreNewMXCSRMMO);
+
+ // Load MXCSR from stack (use LDMXCSR)
+ auto LoadNewMXCSRMMO = MF.getMachineMemOperand(
+ PtrInfo, MachineMemOperand::MOLoad, 4, Align(4));
+ MIRBuilder.buildInstr(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS)
+ .addIntrinsicID(Intrinsic::x86_sse_ldmxcsr)
+ .addUse(StackPtr)
+ .addMemOperand(LoadNewMXCSRMMO);
+ }
+
+ MI.eraseFromParent();
+ return true;
+}
+
bool X86LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper,
MachineInstr &MI) const {
return true;
diff --git a/llvm/lib/Target/X86/GISel/X86LegalizerInfo.h b/llvm/lib/Target/X86/GISel/X86LegalizerInfo.h
index 0003552d70ee0..09c727c8e8685 100644
--- a/llvm/lib/Target/X86/GISel/X86LegalizerInfo.h
+++ b/llvm/lib/Target/X86/GISel/X86LegalizerInfo.h
@@ -57,6 +57,9 @@ class X86LegalizerInfo : public LegalizerInfo {
bool legalizeGETROUNDING(MachineInstr &MI, MachineRegisterInfo &MRI,
LegalizerHelper &Helper) const;
+
+ bool legalizeSETROUNDING(MachineInstr &MI, MachineRegisterInfo &MRI,
+ LegalizerHelper &Helper) const;
};
} // namespace llvm
#endif
diff --git a/llvm/lib/Target/X86/X86InstrGISel.td b/llvm/lib/Target/X86/X86InstrGISel.td
index 39198214037a3..b0c6bb6f61ad8 100644
--- a/llvm/lib/Target/X86/X86InstrGISel.td
+++ b/llvm/lib/Target/X86/X86InstrGISel.td
@@ -34,6 +34,14 @@ def G_FNSTCW16 : X86GenericInstruction {
let mayStore = true;
}
+def G_FLDCW16 : X86GenericInstruction {
+ let OutOperandList = (outs);
+ let InOperandList = (ins ptype0:$src);
+ let hasSideEffects = true;
+ let mayLoad = true;
+}
+
def : GINodeEquiv<G_FILD, X86fild>;
def : GINodeEquiv<G_FIST, X86fp_to_mem>;
def : GINodeEquiv<G_FNSTCW16, X86fp_cwd_get16>;
+def : GINodeEquiv<G_FLDCW16, X86fp_cwd_set16>;
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
index 040f97f96ee21..9ad28a5487233 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
@@ -642,6 +642,9 @@
# DEBUG-NEXT: G_GET_ROUNDING (opcode {{[0-9]+}}): 1 type index, 0 imm indices
# DEBUG-NEXT:.. type index coverage check SKIPPED: no rules defined
# DEBUG-NEXT:.. imm index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: G_SET_ROUNDING (opcode {{[0-9]+}}): 1 type index, 0 imm indices
+# DEBUG-NEXT:.. type index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT:.. imm index coverage check SKIPPED: no rules defined
# DEBUG-NEXT: G_PTR_ADD (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
# DEBUG-NEXT: .. the first uncovered type index: 2, OK
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
index 9d68a6d72c486..f56e78a645d50 100644
--- a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir
@@ -629,6 +629,9 @@
# DEBUG-NEXT: G_GET_ROUNDING (opcode {{[0-9]+}}): 1 type index, 0 imm indices
# DEBUG-NEXT:.. type index coverage check SKIPPED: no rules defined
# DEBUG-NEXT:.. imm index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT: G_SET_ROUNDING (opcode {{[0-9]+}}): 1 type index, 0 imm indices
+# DEBUG-NEXT:.. type index coverage check SKIPPED: no rules defined
+# DEBUG-NEXT:.. imm index coverage check SKIPPED: no rules defined
# DEBUG-NEXT: G_PTR_ADD (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
# DEBUG-NEXT: .. the first uncovered type index: 2, OK
# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
diff --git a/llvm/test/CodeGen/X86/isel-llvm.set.rounding.ll b/llvm/test/CodeGen/X86/isel-llvm.set.rounding.ll
index 688add1e92ab1..f589c16ff18da 100644
--- a/llvm/test/CodeGen/X86/isel-llvm.set.rounding.ll
+++ b/llvm/test/CodeGen/X86/isel-llvm.set.rounding.ll
@@ -1,16 +1,16 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=i686-- -mattr=-sse | FileCheck %s --check-prefixes=X86-NOSSE,SDAG-X86-NOSSE
; RUN: llc < %s -mtriple=i686-- -fast-isel -fast-isel-abort=1 -mattr=-sse | FileCheck %s --check-prefixes=X86-NOSSE,FASTISEL-X86-NOSSE
-; RUN: llc < %s -mtriple=i686-- -global-isel -global-isel-abort=2 -mattr=-sse | FileCheck %s --check-prefixes=X86-NOSSE,GISEL-X86-NOSSE
+; RUN: llc < %s -mtriple=i686-- -global-isel -global-isel-abort=1 -mattr=-sse | FileCheck %s --check-prefixes=GISEL-X86-NOSSE
; RUN: llc < %s -mtriple=x86_64-- -mattr=-sse | FileCheck %s --check-prefixes=X64-NOSSE,SDAG-X64-NOSSE
; RUN: llc < %s -mtriple=x86_64-- -fast-isel -fast-isel-abort=1 -mattr=-sse | FileCheck %s --check-prefixes=X64-NOSSE,FASTISEL-X64-NOSSE
-; RUN: llc < %s -mtriple=x86_64-- -global-isel -global-isel-abort=2 -mattr=-sse | FileCheck %s --check-prefixes=X64-NOSSE,GISEL-X64-NOSSE
+; RUN: llc < %s -mtriple=x86_64-- -global-isel -global-isel-abort=1 -mattr=-sse | FileCheck %s --check-prefixes=GISEL-X64-NOSSE
; RUN: llc < %s -mtriple=i686-- | FileCheck %s --check-prefixes=X86,SDAG-X86
; RUN: llc < %s -mtriple=i686-- -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefixes=X86,FASTISEL-X86
-; RUN: llc < %s -mtriple=i686-- -global-isel -global-isel-abort=2 | FileCheck %s --check-prefixes=X86,GISEL-X86
+; RUN: llc < %s -mtriple=i686-- -global-isel -global-isel-abort=1 | FileCheck %s --check-prefixes=GISEL-X86
; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s --check-prefixes=X64,SDAG-X64
; RUN: llc < %s -mtriple=x86_64-- -fast-isel -fast-isel-abort=1 | FileCheck %s --check-prefixes=X64,FASTISEL-X64
-; RUN: llc < %s -mtriple=x86_64-- -global-isel -global-isel-abort=2 | FileCheck %s --check-prefixes=X64,GISEL-X64
+; RUN: llc < %s -mtriple=x86_64-- -global-isel -global-isel-abort=1 | FileCheck %s --check-prefixes=GISEL-X64
declare void @llvm.set.rounding(i32 %x)
@@ -24,6 +24,21 @@ define void @func_01() nounwind {
; X86-NOSSE-NEXT: popl %eax
; X86-NOSSE-NEXT: retl
;
+; GISEL-X86-NOSSE-LABEL: func_01:
+; GISEL-X86-NOSSE: # %bb.0:
+; GISEL-X86-NOSSE-NEXT: pushl %eax
+; GISEL-X86-NOSSE-NEXT: fnstcw (%esp)
+; GISEL-X86-NOSSE-NEXT: movw $-3073, %ax # imm = 0xF3FF
+; GISEL-X86-NOSSE-NEXT: andw (%esp), %ax
+; GISEL-X86-NOSSE-NEXT: movw $201, %cx
+; GISEL-X86-NOSSE-NEXT: shlw $4, %cx
+; GISEL-X86-NOSSE-NEXT: andw $3072, %cx # imm = 0xC00
+; GISEL-X86-NOSSE-NEXT: orw %ax, %cx
+; GISEL-X86-NOSSE-NEXT: movw %cx, (%esp)
+; GISEL-X86-NOSSE-NEXT: fldcw (%esp)
+; GISEL-X86-NOSSE-NEXT: popl %eax
+; GISEL-X86-NOSSE-NEXT: retl
+;
; X64-NOSSE-LABEL: func_01:
; X64-NOSSE: # %bb.0:
; X64-NOSSE-NEXT: fnstcw -{{[0-9]+}}(%rsp)
@@ -31,6 +46,19 @@ define void @func_01() nounwind {
; X64-NOSSE-NEXT: fldcw -{{[0-9]+}}(%rsp)
; X64-NOSSE-NEXT: retq
;
+; GISEL-X64-NOSSE-LABEL: func_01:
+; GISEL-X64-NOSSE: # %bb.0:
+; GISEL-X64-NOSSE-NEXT: fnstcw -{{[0-9]+}}(%rsp)
+; GISEL-X64-NOSSE-NEXT: movw $-3073, %ax # imm = 0xF3FF
+; GISEL-X64-NOSSE-NEXT: andw -{{[0-9]+}}(%rsp), %ax
+; GISEL-X64-NOSSE-NEXT: movw $201, %cx
+; GISEL-X64-NOSSE-NEXT: shlw $4, %cx
+; GISEL-X64-NOSSE-NEXT: andw $3072, %cx # imm = 0xC00
+; GISEL-X64-NOSSE-NEXT: orw %ax, %cx
+; GISEL-X64-NOSSE-NEXT: movw %cx, -{{[0-9]+}}(%rsp)
+; GISEL-X64-NOSSE-NEXT: fldcw -{{[0-9]+}}(%rsp)
+; GISEL-X64-NOSSE-NEXT: retq
+;
; X86-LABEL: func_01:
; X86: # %bb.0:
; X86-NEXT: pushl %eax
@@ -40,6 +68,21 @@ define void @func_01() nounwind {
; X86-NEXT: popl %eax
; X86-NEXT: retl
;
+; GISEL-X86-LABEL: func_01:
+; GISEL-X86: # %bb.0:
+; GISEL-X86-NEXT: pushl %eax
+; GISEL-X86-NEXT: fnstcw (%esp)
+; GISEL-X86-NEXT: movw $-3073, %ax # imm = 0xF3FF
+; GISEL-X86-NEXT: andw (%esp), %ax
+; GISEL-X86-NEXT: movw $201, %cx
+; GISEL-X86-NEXT: shlw $4, %cx
+; GISEL-X86-NEXT: andw $3072, %cx # imm = 0xC00
+; GISEL-X86-NEXT: orw %ax, %cx
+; GISEL-X86-NEXT: movw %cx, (%esp)
+; GISEL-X86-NEXT: fldcw (%esp)
+; GISEL-X86-NEXT: popl %eax
+; GISEL-X86-NEXT: retl
+;
; X64-LABEL: func_01:
; X64: # %bb.0:
; X64-NEXT: fnstcw -{{[0-9]+}}(%rsp)
@@ -49,6 +92,27 @@ define void @func_01() nounwind {
; X64-NEXT: orb $96, -{{[0-9]+}}(%rsp)
; X64-NEXT: ldmxcsr -{{[0-9]+}}(%rsp)
; X64-NEXT: retq
+;
+; GISEL-X64-LABEL: func_01:
+; GISEL-X64: # %bb.0:
+; GISEL-X64-NEXT: fnstcw -{{[0-9]+}}(%rsp)
+; GISEL-X64-NEXT: movw $-3073, %ax # imm = 0xF3FF
+; GISEL-X64-NEXT: andw -{{[0-9]+}}(%rsp), %ax
+; GISEL-X64-NEXT: movw $201, %cx
+; GISEL-X64-NEXT: shlw $4, %cx
+; GISEL-X64-NEXT: andw $3072, %cx # imm = 0xC00
+; GISEL-X64-NEXT: orw %cx, %ax
+; GISEL-X64-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
+; GISEL-X64-NEXT: fldcw -{{[0-9]+}}(%rsp)
+; GISEL-X64-NEXT: stmxcsr -{{[0-9]+}}(%rsp)
+; GISEL-X64-NEXT: movl $-24577, %eax # imm = 0x9FFF
+; GISEL-X64-NEXT: andl -{{[0-9]+}}(%rsp), %eax
+; GISEL-X64-NEXT: movzwl %cx, %ecx
+; GISEL-X64-NEXT: shll $3, %ecx
+; GISEL-X64-NEXT: orl %eax, %ecx
+; GISEL-X64-NEXT: movl %ecx, -{{[0-9]+}}(%rsp)
+; GISEL-X64-NEXT: ldmxcsr -{{[0-9]+}}(%rsp)
+; GISEL-X64-NEXT: retq
call void @llvm.set.rounding(i32 0) ; TowardZero (CW[11-10] = 11)
ret void
}
@@ -63,6 +127,21 @@ define void @func_02() nounwind {
; X86-NOSSE-NEXT: popl %eax
; X86-NOSSE-NEXT: retl
;
+; GISEL-X86-NOSSE-LABEL: func_02:
+; GISEL-X86-NOSSE: # %bb.0:
+; GISEL-X86-NOSSE-NEXT: pushl %eax
+; GISEL-X86-NOSSE-NEXT: fnstcw (%esp)
+; GISEL-X86-NOSSE-NEXT: movw $-3073, %ax # imm = 0xF3FF
+; GISEL-X86-NOSSE-NEXT: andw (%esp), %ax
+; GISEL-X86-NOSSE-NEXT: movw $201, %cx
+; GISEL-X86-NOSSE-NEXT: shlw $6, %cx
+; GISEL-X86-NOSSE-NEXT: andw $3072, %cx # imm = 0xC00
+; GISEL-X86-NOSSE-NEXT: orw %ax, %cx
+; GISEL-X86-NOSSE-NEXT: movw %cx, (%esp)
+; GISEL-X86-NOSSE-NEXT: fldcw (%esp)
+; GISEL-X86-NOSSE-NEXT: popl %eax
+; GISEL-X86-NOSSE-NEXT: retl
+;
; X64-NOSSE-LABEL: func_02:
; X64-NOSSE: # %bb.0:
; X64-NOSSE-NEXT: fnstcw -{{[0-9]+}}(%rsp)
@@ -70,6 +149,19 @@ define void @func_02() nounwind {
; X64-NOSSE-NEXT: fldcw -{{[0-9]+}}(%rsp)
; X64-NOSSE-NEXT: retq
;
+; GISEL-X64-NOSSE-LABEL: func_02:
+; GISEL-X64-NOSSE: # %bb.0:
+; GISEL-X64-NOSSE-NEXT: fnstcw -{{[0-9]+}}(%rsp)
+; GISEL-X64-NOSSE-NEXT: movw $-3073, %ax # imm = 0xF3FF
+; GISEL-X64-NOSSE-NEXT: andw -{{[0-9]+}}(%rsp), %ax
+; GISEL-X64-NOSSE-NEXT: movw $201, %cx
+; GISEL-X64-NOSSE-NEXT: shlw $6, %cx
+; GISEL-X64-NOSSE-NEXT: andw $3072, %cx # imm = 0xC00
+; GISEL-X64-NOSSE-NEXT: orw %ax, %cx
+; GISEL-X64-NOSSE-NEXT: movw %cx, -{{[0-9]+}}(%rsp)
+; GISEL-X64-NOSSE-NEXT: fldcw -{{[0-9]+}}(%rsp)
+; GISEL-X64-NOSSE-NEXT: retq
+;
; X86-LABEL: func_02:
; X86: # %bb.0:
; X86-NEXT: pushl %eax
@@ -79,6 +171,21 @@ define void @func_02() nounwind {
; X86-NEXT: popl %eax
; X86-NEXT: retl
;
+; GISEL-X86-LABEL: func_02:
+; GISEL-X86: # %bb.0:
+; GISEL-X86-NEXT: pushl %eax
+; GISEL-X86-NEXT: fnstcw (%esp)
+; GISEL-X86-NEXT: movw $-3073, %ax # imm = 0xF3FF
+; GISEL-X86-NEXT: andw (%esp), %ax
+; GISEL-X86-NEXT: movw $201, %cx
+; GISEL-X86-NEXT: shlw $6, %cx
+; GISEL-X86-NEXT: andw $3072, %cx # imm = 0xC00
+; GISEL-X86-NEXT: orw %ax, %cx
+; GISEL-X86-NEXT: movw %cx, (%esp)
+; GISEL-X86-NEXT: fldcw (%esp)
+; GISEL-X86-NEXT: popl %eax
+; GISEL-X86-NEXT: retl
+;
; X64-LABEL: func_02:
; X64: # %bb.0:
; X64-NEXT: fnstcw -{{[0-9]+}}(%rsp)
@@ -88,6 +195,27 @@ define void @func_02() nounwind {
; X64-NEXT: andb $-97, -{{[0-9]+}}(%rsp)
; X64-NEXT: ldmxcsr -{{[0-9]+}}(%rsp)
; X64-NEXT: retq
+;
+; GISEL-X64-LABEL: func_02:
+; GISEL-X64: # %bb.0:
+; GISEL-X64-NEXT: fnstcw -{{[0-9]+}}(%rsp)
+; GISEL-X64-NEXT: movw $-3073, %ax # imm = 0xF3FF
+; GISEL-X64-NEXT: andw -{{[0-9]+}}(%rsp), %ax
+; GISEL-X64-NEXT: movw $201, %cx
+; GISEL-X64-NEXT: shlw $6, %cx
+; GISEL-X64-NEXT: andw $3072, %cx # imm = 0xC00
+; GISEL-X64-NEXT: orw %cx, %ax
+; GISEL-X64-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
+; GISEL-X64-NEXT: fldcw -{{[0-9]+}}(%rsp)
+; GISEL-X64-NEXT: stmxcsr -{{[0-9]+}}(%rsp)
+; GISEL-X64-NEXT: movl $-24577, %eax # imm = 0x9FFF
+; GISEL-X64-NEXT: andl -{{[0-9]+}}(%rsp), %eax
+; GISEL-X64-NEXT: movzwl %cx, %ecx
+; GISEL-X64-NEXT: shll $3, %ecx
+; GISEL-X64-NEXT: orl %eax, %ecx
+; GISEL-X64-NEXT: mov...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/156591
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