[llvm] [NFC][MC][ARM] Reorder decoder functions 4/N (PR #156690)

via llvm-commits llvm-commits at lists.llvm.org
Wed Sep 3 08:21:49 PDT 2025


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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
``````````

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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 41d554f2c..6d7d40a5f 100644
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -6045,29 +6045,30 @@ static DecodeStatus checkDecodedInstruction(MCInst &MI, uint64_t &Size,
                                             uint32_t Insn,
                                             DecodeStatus Result) {
   switch (MI.getOpcode()) {
-    case ARM::HVC: {
-      // HVC is undefined if condition = 0xf otherwise upredictable
-      // if condition != 0xe
-      uint32_t Cond = (Insn >> 28) & 0xF;
-      if (Cond == 0xF)
-        return MCDisassembler::Fail;
-      if (Cond != 0xE)
-        return MCDisassembler::SoftFail;
-      return Result;
-    }
-    case ARM::t2ADDri:
-    case ARM::t2ADDri12:
-    case ARM::t2ADDrr:
-    case ARM::t2ADDrs:
-    case ARM::t2SUBri:
-    case ARM::t2SUBri12:
-    case ARM::t2SUBrr:
-    case ARM::t2SUBrs:
-      if (MI.getOperand(0).getReg() == ARM::SP &&
-          MI.getOperand(1).getReg() != ARM::SP)
-        return MCDisassembler::SoftFail;
-      return Result;
-    default: return Result;
+  case ARM::HVC: {
+    // HVC is undefined if condition = 0xf otherwise upredictable
+    // if condition != 0xe
+    uint32_t Cond = (Insn >> 28) & 0xF;
+    if (Cond == 0xF)
+      return MCDisassembler::Fail;
+    if (Cond != 0xE)
+      return MCDisassembler::SoftFail;
+    return Result;
+  }
+  case ARM::t2ADDri:
+  case ARM::t2ADDri12:
+  case ARM::t2ADDrr:
+  case ARM::t2ADDrs:
+  case ARM::t2SUBri:
+  case ARM::t2SUBri12:
+  case ARM::t2SUBrr:
+  case ARM::t2SUBrs:
+    if (MI.getOperand(0).getReg() == ARM::SP &&
+        MI.getOperand(1).getReg() != ARM::SP)
+      return MCDisassembler::SoftFail;
+    return Result;
+  default:
+    return Result;
   }
 }
 

``````````

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https://github.com/llvm/llvm-project/pull/156690


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