[llvm] [RISCV] Handle non uimm5 VL constants in isVLKnownLE (PR #156639)
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 3 07:31:11 PDT 2025
================
@@ -4807,9 +4820,11 @@ bool RISCV::isVLKnownLE(const MachineOperand &LHS, const MachineOperand &RHS) {
return true;
if (LHS.isImm() && LHS.getImm() == RISCV::VLMaxSentinel)
return false;
- if (!LHS.isImm() || !RHS.isImm())
+ std::optional<int64_t> LHSImm = getEffectiveImm(LHS, MRI),
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preames wrote:
Are you sure the new logic works properly with VLMaxSentinel? In particular, what if you get an ADDI which happens to encode -1?
I think this is correct, just flagging it for extra consideration.
https://github.com/llvm/llvm-project/pull/156639
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