[llvm] [PowerPC] Add intrinsic definition for load and store with Right Length Left-justified (PR #148873)

[Amy Kwan via llvm-commits]

================
@@ -82,3 +82,23 @@ let Predicates = [HasVSX, IsISAFuture] in {
                                    "stxvprll $XTp, $RA, $RB", IIC_LdStLFD, []>;
   }
 }
+
+// Load/Store VSX Vector with Right Length Left-justified.
+foreach Ty = [v4i32, v2i64] in {
+  def : Pat<(Ty (int_ppc_vsx_lxvrl addr:$RA, i64:$RB)),
+            (LXVRL memr:$RA, g8rc:$RB)>;
----------------
amy-kwan wrote:

I might be missing something in my understanding, but is the `memr` and `g8rc` necessary just for this pattern?

https://github.com/llvm/llvm-project/pull/148873