[llvm] [llvm-exegesis] [AArch64] Reland Resolving "not all operands are initialized by snippet generator" (PR #156423)

[Sjoerd Meijer via llvm-commits]

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@@ -152,6 +156,56 @@ class ExegesisAArch64Target : public ExegesisTarget {
   }
 };
 
+Error ExegesisAArch64Target::randomizeTargetMCOperand(
+    const Instruction &Instr, const Variable &Var, MCOperand &AssignedValue,
+    const BitVector &ForbiddenRegs) const {
+  const Operand &Op = Instr.getPrimaryOperand(Var);
+  const auto OperandType = Op.getExplicitOperandInfo().OperandType;
+  // NOTE: To resolve "Not all operands were initialized by snippet generator"
+  // Requires OperandType to be defined for such opcode's operands in AArch64
+  // tablegen files. And omit introduced OperandType(s).
+
+  // Hacky temporary fix works by defaulting all OPERAND_UNKNOWN to
+  // immediate value 0, but this introduce illegal instruction error for below
+  // system instructions will need to be omitted with OperandType or opcode
+  // specific values to avoid generating invalid encodings or unreliable
+  // benchmark results for these system-level instructions.
+  //  Implement opcode-specific immediate value handling for system instrs:
+  //   - MRS/MSR: Use valid system register encodings (e.g., NZCV, FPCR, FPSR)
+  //   - MSRpstatesvcrImm1: Use valid PSTATE field encodings (e.g., SPSel,
+  //   DAIFSet)
+  //   - SYSLxt/SYSxt: Use valid system instruction encodings with proper
+  //   CRn/CRm/op values
+  //   - UDF: Use valid undefined instruction immediate ranges (0-65535)
+
+  switch (OperandType) {
+  // MSL (Masking Shift Left) imm operand for 32-bit splatted SIMD constants
+  // Correspond to AArch64InstructionSelector::tryAdvSIMDModImm321s()
+  case llvm::AArch64::OPERAND_SHIFT_MSL: {
+    // There are two valid encodings:
+    //   - Type 7: imm at [15:8], [47:40], shift = 264 (0x108) → msl #8
+    //   - Type 8: imm at [23:16], [55:48], shift = 272 (0x110) → msl #16
+    //     Corresponds AArch64_AM::encodeAdvSIMDModImmType7()
+    // But, v2s_msl and v4s_msl instructions accept either form,
+    // Thus, Arbitrarily chosing 264 (msl #8) for simplicity.
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sjoerdmeijer wrote:

Agree, this area needs some work in follow ups, but let's start somewhere with this, so is okay as a start. 

https://github.com/llvm/llvm-project/pull/156423