[llvm] [RISCV] Use vleff's AVL when output VL doesn't dominate in RISCVVLOptimizer (PR #156618)

[Luke Lau via llvm-commits]

================
@@ -1464,6 +1464,15 @@ bool RISCVVLOptimizer::tryReduceVL(MachineInstr &MI) const {
   assert((CommonVL->isImm() || CommonVL->getReg().isVirtual()) &&
          "Expected VL to be an Imm or virtual Reg");
 
+  // If the VL is defined by a vleff that doesn't dominate MI, try using the
+  // vleff's AVL. It will be greater than or equal to the output VL.
+  if (CommonVL->isReg()) {
+    const MachineInstr *VLMI = MRI->getVRegDef(CommonVL->getReg());
----------------
lukel97 wrote:

The only VLs that are registers here should be virtual registers, and we're in SSA form so it should always return a definition. The other call to getVRegDef below on line 1493 doesn't check for nullptr either

https://github.com/llvm/llvm-project/pull/156618