[llvm] 653c403 - [X86] Generate test checks (NFC)

[Nikita Popov via llvm-commits]

Author: Nikita Popov
Date: 2025-09-03T10:14:17+02:00
New Revision: 653c40365b9adf43ef766aeb7b6ef341598cceb5

URL: https://github.com/llvm/llvm-project/commit/653c40365b9adf43ef766aeb7b6ef341598cceb5
DIFF: https://github.com/llvm/llvm-project/commit/653c40365b9adf43ef766aeb7b6ef341598cceb5.diff

LOG: [X86] Generate test checks (NFC)

Added: 
    

Modified: 
    llvm/test/CodeGen/X86/bswap-inline-asm.ll

Removed: 
    


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diff  --git a/llvm/test/CodeGen/X86/bswap-inline-asm.ll b/llvm/test/CodeGen/X86/bswap-inline-asm.ll
index f8f154c0688fe..e5ffec7801fc5 100644
--- a/llvm/test/CodeGen/X86/bswap-inline-asm.ll
+++ b/llvm/test/CodeGen/X86/bswap-inline-asm.ll
@@ -1,88 +1,122 @@
-; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck -check-prefix CHK %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
 ; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck %s
 
-; CHK-NOT: InlineAsm
-
-; CHECK-LABEL: foo:
-; CHECK: bswapq
 define i64 @foo(i64 %x) nounwind {
+; CHECK-LABEL: foo:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    movq %rdi, %rax
+; CHECK-NEXT:    bswapq %rax
+; CHECK-NEXT:    retq
 	%asmtmp = tail call i64 asm "bswap $0", "=r,0,~{dirflag},~{fpsr},~{flags}"(i64 %x) nounwind
 	ret i64 %asmtmp
 }
 
-; CHECK-LABEL: bar:
-; CHECK: bswapq
 define i64 @bar(i64 %x) nounwind {
+; CHECK-LABEL: bar:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    movq %rdi, %rax
+; CHECK-NEXT:    bswapq %rax
+; CHECK-NEXT:    retq
 	%asmtmp = tail call i64 asm "bswapq ${0:q}", "=r,0,~{dirflag},~{fpsr},~{flags}"(i64 %x) nounwind
 	ret i64 %asmtmp
 }
 
-; CHECK-LABEL: pen:
-; CHECK: bswapl
 define i32 @pen(i32 %x) nounwind {
+; CHECK-LABEL: pen:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    bswapl %eax
+; CHECK-NEXT:    retq
 	%asmtmp = tail call i32 asm "bswapl ${0:q}", "=r,0,~{dirflag},~{fpsr},~{flags}"(i32 %x) nounwind
 	ret i32 %asmtmp
 }
 
-; CHECK-LABEL: s16:
-; CHECK: rolw    $8,
 define zeroext i16 @s16(i16 zeroext %x) nounwind {
+; CHECK-LABEL: s16:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    rolw $8, %di
+; CHECK-NEXT:    movzwl %di, %eax
+; CHECK-NEXT:    retq
   %asmtmp = tail call i16 asm "rorw $$8, ${0:w}", "=r,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i16 %x) nounwind
   ret i16 %asmtmp
 }
 
-; CHECK-LABEL: t16:
-; CHECK: rolw    $8,
 define zeroext i16 @t16(i16 zeroext %x) nounwind {
+; CHECK-LABEL: t16:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    rolw $8, %di
+; CHECK-NEXT:    movzwl %di, %eax
+; CHECK-NEXT:    retq
   %asmtmp = tail call i16 asm "rorw $$8, ${0:w}", "=r,0,~{cc},~{dirflag},~{fpsr},~{flags}"(i16 %x) nounwind
   ret i16 %asmtmp
 }
 
-; CHECK-LABEL: u16:
-; CHECK: rolw    $8,
 define zeroext i16 @u16(i16 zeroext %x) nounwind {
+; CHECK-LABEL: u16:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    rolw $8, %di
+; CHECK-NEXT:    movzwl %di, %eax
+; CHECK-NEXT:    retq
   %asmtmp = tail call i16 asm "rolw $$8, ${0:w}", "=r,0,~{dirflag},~{fpsr},~{flags},~{cc}"(i16 %x) nounwind
   ret i16 %asmtmp
 }
 
-; CHECK-LABEL: v16:
-; CHECK: rolw    $8,
 define zeroext i16 @v16(i16 zeroext %x) nounwind {
+; CHECK-LABEL: v16:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    rolw $8, %di
+; CHECK-NEXT:    movzwl %di, %eax
+; CHECK-NEXT:    retq
   %asmtmp = tail call i16 asm "rolw $$8, ${0:w}", "=r,0,~{cc},~{dirflag},~{fpsr},~{flags}"(i16 %x) nounwind
   ret i16 %asmtmp
 }
 
-; CHECK-LABEL: s32:
-; CHECK: bswapl
 define i32 @s32(i32 %x) nounwind {
+; CHECK-LABEL: s32:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    bswapl %eax
+; CHECK-NEXT:    retq
   %asmtmp = tail call i32 asm "bswap $0", "=r,0,~{dirflag},~{fpsr},~{flags}"(i32 %x) nounwind
   ret i32 %asmtmp
 }
 
-; CHECK-LABEL: t32:
-; CHECK: bswapl
 define i32 @t32(i32 %x) nounwind {
+; CHECK-LABEL: t32:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    bswapl %eax
+; CHECK-NEXT:    retq
   %asmtmp = tail call i32 asm "bswap $0", "=r,0,~{dirflag},~{flags},~{fpsr}"(i32 %x) nounwind
   ret i32 %asmtmp
 }
 
-; CHECK-LABEL: u32:
-; CHECK: bswapl
 define i32 @u32(i32 %x) nounwind {
+; CHECK-LABEL: u32:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    movl %edi, %eax
+; CHECK-NEXT:    bswapl %eax
+; CHECK-NEXT:    retq
   %asmtmp = tail call i32 asm "rorw $$8, ${0:w};rorl $$16, $0;rorw $$8, ${0:w}", "=r,0,~{cc},~{dirflag},~{flags},~{fpsr}"(i32 %x) nounwind
   ret i32 %asmtmp
 }
 
-; CHECK-LABEL: s64:
-; CHECK: bswapq
 define i64 @s64(i64 %x) nounwind {
+; CHECK-LABEL: s64:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    movq %rdi, %rax
+; CHECK-NEXT:    bswapq %rax
+; CHECK-NEXT:    retq
   %asmtmp = tail call i64 asm "bswap ${0:q}", "=r,0,~{dirflag},~{fpsr},~{flags}"(i64 %x) nounwind
   ret i64 %asmtmp
 }
 
-; CHECK-LABEL: t64:
-; CHECK: bswapq
 define i64 @t64(i64 %x) nounwind {
+; CHECK-LABEL: t64:
+; CHECK:       ## %bb.0:
+; CHECK-NEXT:    movq %rdi, %rax
+; CHECK-NEXT:    bswapq %rax
+; CHECK-NEXT:    retq
   %asmtmp = tail call i64 asm "bswap ${0:q}", "=r,0,~{fpsr},~{dirflag},~{flags}"(i64 %x) nounwind
   ret i64 %asmtmp
 }