[llvm] [AMDGPU][LIT][NFC] Adding -mtriple for AMDGPUAnnotateUniformValues Pass tests (PR #156437)

[Vikash Gupta via llvm-commits]

https://github.com/vg0204 updated https://github.com/llvm/llvm-project/pull/156437

>From af8b027d68f89d701ef9b13547a364e949a2bc83 Mon Sep 17 00:00:00 2001
From: vg0204 <Vikash.Gupta at amd.com>
Date: Tue, 2 Sep 2025 15:51:11 +0530
Subject: [PATCH 1/3] [AMDGPU][LIT] Adding -mtriple to a Codegen LIT test.

Addition of amdgpu -mtriple for AMDGPUAnnotateUniformValues lit
tests as they depends on the uniformity analysis.
---
 .../test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll | 4 ++--
 llvm/test/CodeGen/AMDGPU/store-clobbers-load.ll               | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll b/llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
index 8c3d20ffb02fd..fcb567bb351ec 100644
--- a/llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
+++ b/llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
@@ -5,8 +5,8 @@
 ;       cannot be expressed reliably by the generated checks.
 
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s -check-prefix=ISA
-; RUN: opt --amdgpu-annotate-uniform -S %s |  FileCheck %s -check-prefix=UNIFORM
-; RUN: opt --amdgpu-annotate-uniform --si-annotate-control-flow -S %s |  FileCheck %s -check-prefix=CONTROLFLOW
+; RUN: opt -mtriple=amdgcn -mcpu=gfx900 --amdgpu-annotate-uniform -S %s |  FileCheck %s -check-prefix=UNIFORM
+; RUN: opt -mtriple=amdgcn -mcpu=gfx900 --amdgpu-annotate-uniform --si-annotate-control-flow -S %s |  FileCheck %s -check-prefix=CONTROLFLOW
 
 ; This module creates a divergent branch in block Flow2. The branch is
 ; marked as divergent by the divergence analysis but the condition is
diff --git a/llvm/test/CodeGen/AMDGPU/store-clobbers-load.ll b/llvm/test/CodeGen/AMDGPU/store-clobbers-load.ll
index f4947f6229dea..786f44dc220f1 100644
--- a/llvm/test/CodeGen/AMDGPU/store-clobbers-load.ll
+++ b/llvm/test/CodeGen/AMDGPU/store-clobbers-load.ll
@@ -1,4 +1,4 @@
-; RUN: opt -S --amdgpu-annotate-uniform < %s | FileCheck -check-prefix=OPT %s
+; RUN: opt -S -mtriple=amdgcn-amd-amdhsa --amdgpu-annotate-uniform < %s | FileCheck -check-prefix=OPT %s
 
 ; "load vaddr" depends on the store, so we should not mark vaddr as amdgpu.noclobber.
 
@@ -24,7 +24,7 @@ declare i32 @llvm.amdgcn.workitem.id.x()
 ; To check that %arrayidx0 is not marked as amdgpu.noclobber.
 
 ; OPT-LABEL: @atomicrmw_clobbers_load(
-; OPT:       %arrayidx0 = getelementptr inbounds [512 x i32], ptr addrspace(3) @lds0, i32 0, i32 %idx.0, !amdgpu.uniform !0
+; OPT:       %arrayidx0 = getelementptr inbounds [512 x i32], ptr addrspace(3) @lds0, i32 0, i32 %idx.0
 ; OPT-NEXT:  %val = atomicrmw xchg ptr addrspace(3) %arrayidx0, i32 3 seq_cst
 
 define amdgpu_kernel void @atomicrmw_clobbers_load(ptr addrspace(1) %out0, ptr addrspace(1) %out1) {

>From eaca745d5e2bfd84711d1e7d934552c8f02b8c5c Mon Sep 17 00:00:00 2001
From: vg0204 <Vikash.Gupta at amd.com>
Date: Tue, 2 Sep 2025 17:04:31 +0530
Subject: [PATCH 2/3] updated the test to have identical -mtriple.

---
 .../test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll b/llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
index fcb567bb351ec..80258be19d915 100644
--- a/llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
+++ b/llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
@@ -5,8 +5,8 @@
 ;       cannot be expressed reliably by the generated checks.
 
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s -check-prefix=ISA
-; RUN: opt -mtriple=amdgcn -mcpu=gfx900 --amdgpu-annotate-uniform -S %s |  FileCheck %s -check-prefix=UNIFORM
-; RUN: opt -mtriple=amdgcn -mcpu=gfx900 --amdgpu-annotate-uniform --si-annotate-control-flow -S %s |  FileCheck %s -check-prefix=CONTROLFLOW
+; RUN: opt -mtriple=amdgcn-mesa-mesa3d --amdgpu-annotate-uniform -S %s |  FileCheck %s -check-prefix=UNIFORM
+; RUN: opt -mtriple=amdgcn-mesa-mesa3d --amdgpu-annotate-uniform --si-annotate-control-flow -S %s |  FileCheck %s -check-prefix=CONTROLFLOW
 
 ; This module creates a divergent branch in block Flow2. The branch is
 ; marked as divergent by the divergence analysis but the condition is

>From e64e8725a84bd0e75714b03859040b0ee87187e1 Mon Sep 17 00:00:00 2001
From: vg0204 <Vikash.Gupta at amd.com>
Date: Wed, 3 Sep 2025 12:20:08 +0530
Subject: [PATCH 3/3] Reverted the changes for
 divergent-branch-uniform-condition.ll

---
 .../test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll b/llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
index 80258be19d915..8c3d20ffb02fd 100644
--- a/llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
+++ b/llvm/test/CodeGen/AMDGPU/divergent-branch-uniform-condition.ll
@@ -5,8 +5,8 @@
 ;       cannot be expressed reliably by the generated checks.
 
 ; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s -check-prefix=ISA
-; RUN: opt -mtriple=amdgcn-mesa-mesa3d --amdgpu-annotate-uniform -S %s |  FileCheck %s -check-prefix=UNIFORM
-; RUN: opt -mtriple=amdgcn-mesa-mesa3d --amdgpu-annotate-uniform --si-annotate-control-flow -S %s |  FileCheck %s -check-prefix=CONTROLFLOW
+; RUN: opt --amdgpu-annotate-uniform -S %s |  FileCheck %s -check-prefix=UNIFORM
+; RUN: opt --amdgpu-annotate-uniform --si-annotate-control-flow -S %s |  FileCheck %s -check-prefix=CONTROLFLOW
 
 ; This module creates a divergent branch in block Flow2. The branch is
 ; marked as divergent by the divergence analysis but the condition is