[clang] [llvm] [SPIRV] Add OpInf support for isinf hlsl intrinsic (PR #156570)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp,h -- clang/lib/CodeGen/CGHLSLBuiltins.cpp clang/lib/CodeGen/CGHLSLRuntime.h llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
``````````

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``````````diff
diff --git a/clang/lib/CodeGen/CGHLSLBuiltins.cpp b/clang/lib/CodeGen/CGHLSLBuiltins.cpp
index 7962dec4d..00c218285 100644
--- a/clang/lib/CodeGen/CGHLSLBuiltins.cpp
+++ b/clang/lib/CodeGen/CGHLSLBuiltins.cpp
@@ -536,8 +536,9 @@ Value *CodeGenFunction::EmitHLSLBuiltinExpr(unsigned BuiltinID,
     }
     if (!E->getArg(0)->getType()->hasFloatingRepresentation())
       llvm_unreachable("isinf operand must have a float representation");
-    return Builder.CreateIntrinsic(retType, CGM.getHLSLRuntime().getIsInfIntrinsic(),
-                                   ArrayRef<Value *>{Op0}, nullptr, "hlsl.isinf");
+    return Builder.CreateIntrinsic(
+        retType, CGM.getHLSLRuntime().getIsInfIntrinsic(),
+        ArrayRef<Value *>{Op0}, nullptr, "hlsl.isinf");
   }
   case Builtin::BI__builtin_hlsl_mad: {
     Value *M = EmitScalarExpr(E->getArg(0));
diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
index f00ac4790..3ad5528fa 100644
--- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp
@@ -205,7 +205,7 @@ private:
                                  MachineInstr &I) const;
 
   bool selectOpIsInf(Register ResVReg, const SPIRVType *ResType,
-                 MachineInstr &I) const;
+                     MachineInstr &I) const;
 
   template <bool Signed>
   bool selectDot4AddPacked(Register ResVReg, const SPIRVType *ResType,
@@ -2046,8 +2046,8 @@ bool SPIRVInstructionSelector::selectIntegerDotExpansion(
 }
 
 bool SPIRVInstructionSelector::selectOpIsInf(Register ResVReg,
-                                                   const SPIRVType *ResType,
-                                                   MachineInstr &I) const {
+                                             const SPIRVType *ResType,
+                                             MachineInstr &I) const {
   MachineBasicBlock &BB = *I.getParent();
   return BuildMI(BB, I, I.getDebugLoc(), TII.get(SPIRV::OpIsInf))
       .addDef(ResVReg)

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https://github.com/llvm/llvm-project/pull/156570