[llvm] [RISCV][GISel] Add initial support for rvv intrinsics (PR #156415)

[Min-Yih Hsu via llvm-commits]

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@@ -0,0 +1,764 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \
+; RUN:   -verify-machineinstrs -target-abi=ilp32d -global-isel | FileCheck %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zvfh \
+; RUN:   -verify-machineinstrs -target-abi=ilp32d -global-isel | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zvfh \
+; RUN:   -verify-machineinstrs -target-abi=lp64d -global-isel | FileCheck %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfhmin,+zvfh \
+; RUN:   -verify-machineinstrs -target-abi=ilp32d -global-isel | FileCheck %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfhmin,+zvfh \
+; RUN:   -verify-machineinstrs -target-abi=lp64d -global-isel | FileCheck %s
+
+declare <vscale x 1 x half> @llvm.riscv.vfadd.nxv1f16.nxv1f16(
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  <vscale x 1 x half>,
+  iXLen, iXLen);
+
+define <vscale x 1 x half> @intrinsic_vfadd_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, iXLen %2) nounwind {
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mshockwave wrote:

nit: for most of the intrinsics here, their operands should have the same type, so a function like `intrinsic_vfadd_vv_nxv1f16` should suffice

https://github.com/llvm/llvm-project/pull/156415