[llvm] [AArch64] Combine SEXT_INREG(CSET) to CSETM. (PR #156429)

[Paul Walker via llvm-commits]

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@@ -26585,6 +26585,26 @@ performSignExtendInRegCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
     return DAG.getNode(SOpc, DL, N->getValueType(0), Ext);
   }
 
+  // Sign extend of CSET -> CSETM.
+  if (Opc == AArch64ISD::CSEL &&
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paulwalker-arm wrote:

It's not backed by any science I just wasn't sure if having two instructions requiring the same CC flags might hinder scheduling more? It seems an unlikely scenario so I'm happy to defer the decision until we have a real world use case to analyse.

https://github.com/llvm/llvm-project/pull/156429