[llvm] [AMDGPU][True16][CodeGen] update zext pattern with reg_sequence (PR #154952)

[Brox Chen via llvm-commits]

https://github.com/broxigarchen updated https://github.com/llvm/llvm-project/pull/154952

>From 01480d7248eb6c10e969235fe6e9abec4775f615 Mon Sep 17 00:00:00 2001
From: guochen2 <guochen2 at amd.com>
Date: Fri, 22 Aug 2025 09:56:51 -0400
Subject: [PATCH 1/2] update one with reg_sequence

---
 llvm/lib/Target/AMDGPU/SIInstructions.td | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index e8b4501226732..ed5df2c55db1b 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -3106,9 +3106,7 @@ def : GCNPat<
 
 def : GCNPat<
   (i64 (DivergentUnaryFrag<zext> i16:$src)),
-  (REG_SEQUENCE VReg_64,
-    (INSERT_SUBREG (i32 (V_MOV_B32_e32 (i32 0))), VGPR_16:$src, lo16), sub0,
-    (S_MOV_B32 (i32 0)), sub1)
+  (REG_SEQUENCE VReg_64, $src, lo16, (V_MOV_B16_t16_e64 0, (i16 0), 0), hi16, (S_MOV_B32 (i32 0)), sub1)
 >;
 
 def : GCNPat<

>From 799ff371207eabb86f5ce9d530b0de802815e6d4 Mon Sep 17 00:00:00 2001
From: guochen2 <guochen2 at amd.com>
Date: Tue, 2 Sep 2025 12:39:44 -0400
Subject: [PATCH 2/2] use v_mov_b32

---
 llvm/lib/Target/AMDGPU/SIInstructions.td | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index ed5df2c55db1b..d6f8ccf1bae28 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -3106,7 +3106,7 @@ def : GCNPat<
 
 def : GCNPat<
   (i64 (DivergentUnaryFrag<zext> i16:$src)),
-  (REG_SEQUENCE VReg_64, $src, lo16, (V_MOV_B16_t16_e64 0, (i16 0), 0), hi16, (S_MOV_B32 (i32 0)), sub1)
+  (REG_SEQUENCE VReg_64, $src, lo16, (V_MOV_B16_t16_e64 0, (i16 0), 0), hi16, (V_MOV_B32_e32 (i32 0)), sub1)
 >;
 
 def : GCNPat<