[llvm] [ARM] hasAndNot in ARM supports vectors. (PR #156488)

[via llvm-commits]

https://github.com/AZero13 created https://github.com/llvm/llvm-project/pull/156488

None

>From 7efad6b42f6eb12ec7e824428c3b60416fef4e5b Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Tue, 2 Sep 2025 12:40:27 -0400
Subject: [PATCH] hasAndNot in ARM supports vectors.

---
 llvm/lib/Target/ARM/ARMISelLowering.cpp | 12 ++++++++++++
 llvm/lib/Target/ARM/ARMISelLowering.h   |  2 ++
 2 files changed, 14 insertions(+)

diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp
index b5c01eafcf108..221d5ae0054ec 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.cpp
+++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp
@@ -16125,6 +16125,18 @@ static bool TryCombineBaseUpdate(struct BaseUpdateTarget &Target,
   return true;
 }
 
+bool ARMTargetLowering::hasAndNot(SDValue Y) const {
+  EVT VT = Y.getValueType();
+
+  if (!VT.isVector())
+    return hasAndNotCompare(Y);
+
+  if (Subtarget->hasNEON() || Subtarget->hasMVEIntegerOps())
+    return VT.getFixedSizeInBits() >= 64; // vector 'bic'
+
+  return false;
+}
+
 // If (opcode ptr inc) is and ADD-like instruction, return the
 // increment value. Otherwise return 0.
 static unsigned getPointerConstIncrement(unsigned Opcode, SDValue Ptr,
diff --git a/llvm/lib/Target/ARM/ARMISelLowering.h b/llvm/lib/Target/ARM/ARMISelLowering.h
index 196ecb1b9f678..c36be449b1a4a 100644
--- a/llvm/lib/Target/ARM/ARMISelLowering.h
+++ b/llvm/lib/Target/ARM/ARMISelLowering.h
@@ -611,6 +611,8 @@ class VectorType;
 
     bool isMaskAndCmp0FoldingBeneficial(const Instruction &AndI) const override;
 
+    bool hasAndNot(SDValue Y) const override;
+
     bool hasAndNotCompare(SDValue V) const override {
       // We can use bics for any scalar.
       return V.getValueType().isScalarInteger();