[llvm] [LoongArch] Optimize extractelement containing variable index (PR #151475)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 2 00:51:05 PDT 2025
================
@@ -2608,14 +2613,91 @@ SDValue LoongArchTargetLowering::lowerCONCAT_VECTORS(SDValue Op,
SDValue
LoongArchTargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,
SelectionDAG &DAG) const {
- EVT VecTy = Op->getOperand(0)->getValueType(0);
+ MVT EltVT = Op.getSimpleValueType();
+ SDValue Vec = Op->getOperand(0);
+ EVT VecTy = Vec->getValueType(0);
SDValue Idx = Op->getOperand(1);
- unsigned NumElts = VecTy.getVectorNumElements();
+ SDLoc DL(Op);
+ MVT GRLenVT = Subtarget.getGRLenVT();
+
+ assert(VecTy.is256BitVector() && "Unexpected EXTRACT_VECTOR_ELT vector type");
- if (isa<ConstantSDNode>(Idx) && Idx->getAsZExtVal() < NumElts)
+ if (isa<ConstantSDNode>(Idx))
return Op;
- return SDValue();
+ switch (VecTy.getSimpleVT().SimpleTy) {
+ default:
+ llvm_unreachable("Unexpected type");
+ case MVT::v32i8:
+ case MVT::v16i16: {
+ // Consider the source vector as v8i32 type.
+ SDValue NewVec = DAG.getBitcast(MVT::v8i32, Vec);
+
+ // Compute the adjusted index and use it to broadcast the vector.
+ // The original desired i8/i16 element is now replicated in each
+ // i32 lane of the splatted vector.
+ SDValue NewIdx = DAG.getNode(
+ LoongArchISD::BSTRPICK, DL, GRLenVT, Idx,
----------------
heiher wrote:
`BSTRPICK` instruction requires the `32s` target feature. Replace it with an arithmetic right shift?
https://github.com/llvm/llvm-project/pull/151475
More information about the llvm-commits
mailing list