[llvm] [AMDGPU] SIFoldOperands check that shrunk op is valid (PR #156298)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 1 21:20:07 PDT 2025
================
@@ -0,0 +1,41 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=amdgcn -mcpu=gfx1250 -run-pass=si-fold-operands %s -o - | FileCheck %s
+
+--- |
+ @sym = external constant i32
+ define void @fn() { ret void }
+ define void @fn2() { ret void }
+...
+
+---
+name: fn
+tracksRegLiveness: true
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: fn
+ ; CHECK: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 target-flags(amdgpu-abs64) @sym
+ ; CHECK-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 undef [[DEF]].sub0, undef [[S_MOV_B64_]].sub0, 0, implicit $exec
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e64_]]
+ %0:vreg_64 = IMPLICIT_DEF
+ %1:sreg_64 = S_MOV_B64 target-flags(amdgpu-abs64) @sym
+ %2:vgpr_32, %3:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 undef %1.sub0, undef %0.sub0, 0, implicit $exec
+ S_ENDPGM 0, implicit %2
+...
+
+---
+name: fn2
+tracksRegLiveness: true
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: fn2
+ ; CHECK: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
+ ; CHECK-NEXT: [[V_ADD_CO_U32_e64_:%[0-9]+]]:vgpr_32, [[V_ADD_CO_U32_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 591751049, undef [[DEF]].sub0, 0, implicit $exec
+ ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_ADD_CO_U32_e64_]]
+ %0:vreg_64 = IMPLICIT_DEF
+ %1:sreg_64 = S_MOV_B64 4886718345
+ %2:vgpr_32, %3:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 undef %1.sub0, undef %0.sub0, 0, implicit $exec
+ S_ENDPGM 0, implicit %2
+...
+## NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+# CHECK: {{.*}}
----------------
arsenm wrote:
This is broken, looks like a leftover from trying to use update_llc_test_checks on this?
https://github.com/llvm/llvm-project/pull/156298
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