[clang] [llvm] [RISCV][MC] Add MC support of Zibi experimental extension (PR #127463)

[Alexander Richardson via llvm-commits]

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@@ -0,0 +1,44 @@
+//===-- RISCVInstrInfoZibi.td - 'Zibi' instructions --------*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+///
+/// This file describes the RISC-V instructions for 'Zibi' (branch with imm).
+///
+//===----------------------------------------------------------------------===//
+
+// A 5-bit unsigned immediate representing 1-31 and -1. 00000 represents -1.
+def uimm5_zibi : RISCVOp<XLenVT>, ImmLeaf<XLenVT, [{
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arichardson wrote:

Since this is not unsigned, the uimm prefix is somewhat misleading. How about zibi_imm5 or imm5_zibi?

https://github.com/llvm/llvm-project/pull/127463