[llvm] [TableGen][Decoder] Decode operands with zero width or all bits known (PR #156358)

[Sergei Barannikov via llvm-commits]

s-barannikov wrote:

Locally I have fixes for all targets except ARM and AMDGPU. They turned out to be the most difficult to fix, but I might try again later.


https://github.com/llvm/llvm-project/pull/156358