[llvm] [Intrinsics][AArch64] Add intrinsics for masking off aliasing vector lanes (PR #117007)

[Sam Tebbs via llvm-commits]

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@@ -24212,8 +24216,8 @@ The element of the result mask is active when storing to %ptrA then loading from
 %ptrB is safe and doesn't result in aliasing, meaning that:
 
 * abs(ptrB - ptrA) >= elementSize * lane (guarantees that the store of this lane
-  occurs before loading from this address)
-* ptrA == ptrB doesn't introduce any new hazards and is safe
+  occurs before loading from this address), or
+* ptrA == ptrB, doesn't introduce any new hazards
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SamTebbs33 wrote:

Done.

https://github.com/llvm/llvm-project/pull/117007