[llvm] b980ff7 - [LoongArch][NFC] Fix missing check prefixes in LSX build-vector.ll
WANG Rui via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 1 03:40:54 PDT 2025
Author: WANG Rui
Date: 2025-09-01T18:42:27+08:00
New Revision: b980ff795096ce95236b3e6f0f63cc9d1510fcec
URL: https://github.com/llvm/llvm-project/commit/b980ff795096ce95236b3e6f0f63cc9d1510fcec
DIFF: https://github.com/llvm/llvm-project/commit/b980ff795096ce95236b3e6f0f63cc9d1510fcec.diff
LOG: [LoongArch][NFC] Fix missing check prefixes in LSX build-vector.ll
Added:
Modified:
llvm/test/CodeGen/LoongArch/lsx/build-vector.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/LoongArch/lsx/build-vector.ll b/llvm/test/CodeGen/LoongArch/lsx/build-vector.ll
index abe954c70374e..24df71c2ad71b 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/build-vector.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/build-vector.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
-; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
-; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64
define void @buildvector_v16i8_splat(ptr %dst, i8 %a0) nounwind {
; CHECK-LABEL: buildvector_v16i8_splat:
@@ -42,6 +42,20 @@ entry:
}
define void @buildvector_v2i64_splat(ptr %dst, i64 %a0) nounwind {
+; LA32-LABEL: buildvector_v2i64_splat:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
+; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 2
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 3
+; LA32-NEXT: vst $vr0, $a0, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: buildvector_v2i64_splat:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: vreplgr2vr.d $vr0, $a1
+; LA64-NEXT: vst $vr0, $a0, 0
+; LA64-NEXT: ret
entry:
%insert = insertelement <2 x i64> undef, i64 %a0, i8 0
%splat = shufflevector <2 x i64> %insert, <2 x i64> undef, <2 x i32> zeroinitializer
@@ -134,6 +148,19 @@ entry:
}
define void @buildvector_v2f64_const_splat(ptr %dst) nounwind {
+; LA32-LABEL: buildvector_v2f64_const_splat:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI11_0)
+; LA32-NEXT: vld $vr0, $a1, %pc_lo12(.LCPI11_0)
+; LA32-NEXT: vst $vr0, $a0, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: buildvector_v2f64_const_splat:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: lu52i.d $a1, $zero, 1023
+; LA64-NEXT: vreplgr2vr.d $vr0, $a1
+; LA64-NEXT: vst $vr0, $a0, 0
+; LA64-NEXT: ret
entry:
store <2 x double> <double 1.0, double 1.0>, ptr %dst
ret void
@@ -212,6 +239,65 @@ entry:
}
define void @buildvector_v16i8(ptr %dst, i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4, i8 %a5, i8 %a6, i8 %a7, i8 %a8, i8 %a9, i8 %a10, i8 %a11, i8 %a12, i8 %a13, i8 %a14, i8 %a15) nounwind {
+; LA32-LABEL: buildvector_v16i8:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: ld.b $t0, $sp, 32
+; LA32-NEXT: ld.b $t1, $sp, 28
+; LA32-NEXT: ld.b $t2, $sp, 24
+; LA32-NEXT: ld.b $t3, $sp, 20
+; LA32-NEXT: ld.b $t4, $sp, 16
+; LA32-NEXT: ld.b $t5, $sp, 12
+; LA32-NEXT: ld.b $t6, $sp, 8
+; LA32-NEXT: ld.b $t7, $sp, 4
+; LA32-NEXT: ld.b $t8, $sp, 0
+; LA32-NEXT: vinsgr2vr.b $vr0, $a1, 0
+; LA32-NEXT: vinsgr2vr.b $vr0, $a2, 1
+; LA32-NEXT: vinsgr2vr.b $vr0, $a3, 2
+; LA32-NEXT: vinsgr2vr.b $vr0, $a4, 3
+; LA32-NEXT: vinsgr2vr.b $vr0, $a5, 4
+; LA32-NEXT: vinsgr2vr.b $vr0, $a6, 5
+; LA32-NEXT: vinsgr2vr.b $vr0, $a7, 6
+; LA32-NEXT: vinsgr2vr.b $vr0, $t8, 7
+; LA32-NEXT: vinsgr2vr.b $vr0, $t7, 8
+; LA32-NEXT: vinsgr2vr.b $vr0, $t6, 9
+; LA32-NEXT: vinsgr2vr.b $vr0, $t5, 10
+; LA32-NEXT: vinsgr2vr.b $vr0, $t4, 11
+; LA32-NEXT: vinsgr2vr.b $vr0, $t3, 12
+; LA32-NEXT: vinsgr2vr.b $vr0, $t2, 13
+; LA32-NEXT: vinsgr2vr.b $vr0, $t1, 14
+; LA32-NEXT: vinsgr2vr.b $vr0, $t0, 15
+; LA32-NEXT: vst $vr0, $a0, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: buildvector_v16i8:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: ld.b $t0, $sp, 64
+; LA64-NEXT: ld.b $t1, $sp, 56
+; LA64-NEXT: ld.b $t2, $sp, 48
+; LA64-NEXT: ld.b $t3, $sp, 40
+; LA64-NEXT: ld.b $t4, $sp, 32
+; LA64-NEXT: ld.b $t5, $sp, 24
+; LA64-NEXT: ld.b $t6, $sp, 16
+; LA64-NEXT: ld.b $t7, $sp, 8
+; LA64-NEXT: ld.b $t8, $sp, 0
+; LA64-NEXT: vinsgr2vr.b $vr0, $a1, 0
+; LA64-NEXT: vinsgr2vr.b $vr0, $a2, 1
+; LA64-NEXT: vinsgr2vr.b $vr0, $a3, 2
+; LA64-NEXT: vinsgr2vr.b $vr0, $a4, 3
+; LA64-NEXT: vinsgr2vr.b $vr0, $a5, 4
+; LA64-NEXT: vinsgr2vr.b $vr0, $a6, 5
+; LA64-NEXT: vinsgr2vr.b $vr0, $a7, 6
+; LA64-NEXT: vinsgr2vr.b $vr0, $t8, 7
+; LA64-NEXT: vinsgr2vr.b $vr0, $t7, 8
+; LA64-NEXT: vinsgr2vr.b $vr0, $t6, 9
+; LA64-NEXT: vinsgr2vr.b $vr0, $t5, 10
+; LA64-NEXT: vinsgr2vr.b $vr0, $t4, 11
+; LA64-NEXT: vinsgr2vr.b $vr0, $t3, 12
+; LA64-NEXT: vinsgr2vr.b $vr0, $t2, 13
+; LA64-NEXT: vinsgr2vr.b $vr0, $t1, 14
+; LA64-NEXT: vinsgr2vr.b $vr0, $t0, 15
+; LA64-NEXT: vst $vr0, $a0, 0
+; LA64-NEXT: ret
entry:
%ins0 = insertelement <16 x i8> undef, i8 %a0, i32 0
%ins1 = insertelement <16 x i8> %ins0, i8 %a1, i32 1
@@ -621,6 +707,21 @@ entry:
}
define void @buildvector_v2i64(ptr %dst, i64 %a0, i64 %a1) nounwind {
+; LA32-LABEL: buildvector_v2i64:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
+; LA32-NEXT: vinsgr2vr.w $vr0, $a3, 2
+; LA32-NEXT: vinsgr2vr.w $vr0, $a4, 3
+; LA32-NEXT: vst $vr0, $a0, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: buildvector_v2i64:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: vinsgr2vr.d $vr0, $a1, 0
+; LA64-NEXT: vinsgr2vr.d $vr0, $a2, 1
+; LA64-NEXT: vst $vr0, $a0, 0
+; LA64-NEXT: ret
entry:
%ins0 = insertelement <2 x i64> undef, i64 %a0, i32 0
%ins1 = insertelement <2 x i64> %ins0, i64 %a1, i32 1
@@ -629,6 +730,18 @@ entry:
}
define void @buildvector_v2i64_partial(ptr %dst, i64 %a0) nounwind {
+; LA32-LABEL: buildvector_v2i64_partial:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 1
+; LA32-NEXT: vst $vr0, $a0, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: buildvector_v2i64_partial:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: vinsgr2vr.d $vr0, $a1, 0
+; LA64-NEXT: vst $vr0, $a0, 0
+; LA64-NEXT: ret
entry:
%ins0 = insertelement <2 x i64> undef, i64 %a0, i32 0
%ins1 = insertelement <2 x i64> %ins0, i64 undef, i32 1
@@ -637,6 +750,20 @@ entry:
}
define void @buildvector_v2i64_with_constant(ptr %dst, i64 %a1) nounwind {
+; LA32-LABEL: buildvector_v2i64_with_constant:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: vrepli.b $vr0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 2
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 3
+; LA32-NEXT: vst $vr0, $a0, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: buildvector_v2i64_with_constant:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: vrepli.b $vr0, 0
+; LA64-NEXT: vinsgr2vr.d $vr0, $a1, 1
+; LA64-NEXT: vst $vr0, $a0, 0
+; LA64-NEXT: ret
entry:
%ins0 = insertelement <2 x i64> undef, i64 0, i32 0
%ins1 = insertelement <2 x i64> %ins0, i64 %a1, i32 1
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