[llvm] 1debf23 - [RISC-V] Added the mips extension instructions like ehb,ihb and pause etc for MIPS RV64 P8700. (#155747)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 1 01:40:33 PDT 2025
Author: UmeshKalappa
Date: 2025-09-01T10:40:28+02:00
New Revision: 1debf23d7a3393234f59b4884ad680995b304c49
URL: https://github.com/llvm/llvm-project/commit/1debf23d7a3393234f59b4884ad680995b304c49
DIFF: https://github.com/llvm/llvm-project/commit/1debf23d7a3393234f59b4884ad680995b304c49.diff
LOG: [RISC-V] Added the mips extension instructions like ehb,ihb and pause etc for MIPS RV64 P8700. (#155747)
Please refer the
https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf
for more information .
and files like RISCVInstrInfoXMips.td clang formatted .
No Regression found.
---------
Co-authored-by: Craig Topper <craig.topper at sifive.com>
Added:
Modified:
clang/test/Driver/print-supported-extensions-riscv.c
llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td
llvm/lib/Target/RISCV/RISCVProcessors.td
llvm/test/CodeGen/RISCV/features-info.ll
llvm/test/MC/RISCV/xmips-invalid.s
llvm/test/MC/RISCV/xmips-valid.s
llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
Removed:
################################################################################
diff --git a/clang/test/Driver/print-supported-extensions-riscv.c b/clang/test/Driver/print-supported-extensions-riscv.c
index 3fa5ef9afd143..413275dba8438 100644
--- a/clang/test/Driver/print-supported-extensions-riscv.c
+++ b/clang/test/Driver/print-supported-extensions-riscv.c
@@ -175,6 +175,7 @@
// CHECK-NEXT: xcvsimd 1.0 'XCVsimd' (CORE-V SIMD ALU)
// CHECK-NEXT: xmipscbop 1.0 'XMIPSCBOP' (MIPS Software Prefetch)
// CHECK-NEXT: xmipscmov 1.0 'XMIPSCMov' (MIPS conditional move instruction (mips.ccmov))
+// CHECK-NEXT: xmipsexectl 1.0 'XMIPSEXECTL' (MIPS execution control)
// CHECK-NEXT: xmipslsp 1.0 'XMIPSLSP' (MIPS optimization for hardware load-store bonding)
// CHECK-NEXT: xsfcease 1.0 'XSfcease' (SiFive sf.cease Instruction)
// CHECK-NEXT: xsfmm128t 0.6 'XSfmm128t' (TE=128 configuration)
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
index dbb16fce8390a..de1bdb4a8811c 100644
--- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
+++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
@@ -656,6 +656,13 @@ static constexpr FeatureBitset XSfSystemGroup = {
RISCV::FeatureVendorXSiFivecflushdlone,
};
+static constexpr FeatureBitset XMIPSGroup = {
+ RISCV::FeatureVendorXMIPSLSP,
+ RISCV::FeatureVendorXMIPSCMov,
+ RISCV::FeatureVendorXMIPSCBOP,
+ RISCV::FeatureVendorXMIPSEXECTL,
+};
+
static constexpr FeatureBitset XTHeadGroup = {
RISCV::FeatureVendorXTHeadBa, RISCV::FeatureVendorXTHeadBb,
RISCV::FeatureVendorXTHeadBs, RISCV::FeatureVendorXTHeadCondMov,
@@ -684,13 +691,7 @@ static constexpr DecoderListEntry DecoderList32[]{
{DecoderTableXSfvector32, XSfVectorGroup, "SiFive vector extensions"},
{DecoderTableXSfsystem32, XSfSystemGroup, "SiFive system extensions"},
{DecoderTableXSfcease32, {RISCV::FeatureVendorXSfcease}, "SiFive sf.cease"},
- {DecoderTableXmipslsp32, {RISCV::FeatureVendorXMIPSLSP}, "MIPS mips.lsp"},
- {DecoderTableXmipscmov32,
- {RISCV::FeatureVendorXMIPSCMov},
- "MIPS mips.ccmov"},
- {DecoderTableXmipscbop32,
- {RISCV::FeatureVendorXMIPSCBOP},
- "MIPS mips.pref"},
+ {DecoderTableXMIPS32, XMIPSGroup, "Mips extensions"},
{DecoderTableXAndes32, XAndesGroup, "Andes extensions"},
{DecoderTableXSMT32, XSMTGroup, "SpacemiT extensions"},
// Standard Extensions
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td
index fa8272b239d99..bf5dca481cd2b 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1403,20 +1403,27 @@ def HasVendorXMIPSCMov
AssemblerPredicate<(all_of FeatureVendorXMIPSCMov),
"'Xmipscmov' ('mips.ccmov' instruction)">;
def UseCCMovInsn : Predicate<"Subtarget->useCCMovInsn()">;
+
def FeatureVendorXMIPSLSP
: RISCVExtension<1, 0, "MIPS optimization for hardware load-store bonding">;
def HasVendorXMIPSLSP
: Predicate<"Subtarget->hasVendorXMIPSLSP()">,
AssemblerPredicate<(all_of FeatureVendorXMIPSLSP),
"'Xmipslsp' (load and store pair instructions)">;
-def FeatureVendorXMIPSCBOP
- : RISCVExtension<1, 0, "MIPS Software Prefetch">;
+
+def FeatureVendorXMIPSCBOP : RISCVExtension<1, 0, "MIPS Software Prefetch">;
def HasVendorXMIPSCBOP
: Predicate<"Subtarget->hasVendorXMIPSCBOP()">,
AssemblerPredicate<(all_of FeatureVendorXMIPSCBOP),
"'Xmipscbop' (MIPS hardware prefetch)">;
def NoVendorXMIPSCBOP : Predicate<"!Subtarget->hasVendorXMIPSCBOP()">;
+def FeatureVendorXMIPSEXECTL : RISCVExtension<1, 0, "MIPS execution control">;
+def HasVendorXMIPSEXECTL
+ : Predicate<"Subtarget->hasVendorXMIPSEXT()">,
+ AssemblerPredicate<(all_of FeatureVendorXMIPSEXECTL),
+ "'Xmipsexectl' (MIPS execution control)">;
+
// WCH / Nanjing Qinheng Microelectronics Extension(s)
def FeatureVendorXwchc
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td
index 889ea98022572..d615094329b28 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td
@@ -125,10 +125,25 @@ class Mips_prefetch_ri<dag outs, dag ins, string opcodestr, string argstr>
let Inst{6-0} = OPC_CUSTOM_0.Value;
}
+// MIPS Custom Barrier Insns Format.
+let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
+class MIPSExtInst_ri<bits<6> shimm5, string opcodestr>
+ : RVInstIShift<0b00000, 0b001, OPC_OP_IMM, (outs), (ins), opcodestr, ""> {
+ let shamt = shimm5;
+ let rd = 0;
+ let rs1 = 0;
+}
+
//===----------------------------------------------------------------------===//
// MIPS extensions
//===----------------------------------------------------------------------===//
-let Predicates = [HasVendorXMIPSCBOP] ,DecoderNamespace = "Xmipscbop" in {
+let Predicates = [HasVendorXMIPSEXECTL], DecoderNamespace = "XMIPS" in {
+ def MIPS_EHB : MIPSExtInst_ri<0b000011, "mips.ehb">;
+ def MIPS_IHB : MIPSExtInst_ri<0b000001, "mips.ihb">;
+ def MIPS_PAUSE : MIPSExtInst_ri<0b000101, "mips.pause">;
+}
+
+let Predicates = [HasVendorXMIPSCBOP], DecoderNamespace = "XMIPS" in {
def MIPS_PREF : Mips_prefetch_ri<(outs), (ins GPR:$rs1, uimm9:$imm9, uimm5:$hint),
"mips.pref", "$hint, ${imm9}(${rs1})">,
Sched<[]>;
@@ -146,7 +161,7 @@ let Predicates = [HasVendorXMIPSCBOP] in {
}
let Predicates = [HasVendorXMIPSCMov], hasSideEffects = 0, mayLoad = 0, mayStore = 0,
- DecoderNamespace = "Xmipscmov" in {
+ DecoderNamespace = "XMIPS" in {
def MIPS_CCMOV : RVInstR4<0b11, 0b011, OPC_CUSTOM_0, (outs GPR:$rd),
(ins GPR:$rs1, GPR:$rs2, GPR:$rs3),
"mips.ccmov", "$rd, $rs2, $rs1, $rs3">,
@@ -166,7 +181,7 @@ def : Pat<(select (XLenVT GPR:$rs2), (XLenVT GPR:$rs1), (XLenVT GPR:$rs3)),
}
let Predicates = [HasVendorXMIPSLSP], hasSideEffects = 0,
- DecoderNamespace = "Xmipslsp" in {
+ DecoderNamespace = "XMIPS" in {
let mayLoad = 1, mayStore = 0 in {
def MIPS_LWP : LWPFormat<(outs GPR:$rd1, GPR:$rd2), (ins GPR:$rs1, uimm7_lsb00:$imm7),
"mips.lwp", "$rd1, $rd2, ${imm7}(${rs1})">,
@@ -184,4 +199,4 @@ def MIPS_SDP : SDPFormat<(outs), (ins GPR:$rs2, GPR:$rs3, GPR:$rs1, uimm7_lsb000
"mips.sdp", "$rs2, $rs3, ${imm7}(${rs1})">,
Sched<[WriteSTD, ReadStoreData, ReadStoreData, ReadMemBase]>;
} // mayLoad = 0, mayStore = 1
-} // Predicates = [HasVendorXMIPSLSP], hasSideEffects = 0, DecoderNamespace = "Xmipslsp"
+} // Predicates = [HasVendorXMIPSLSP], hasSideEffects = 0, DecoderNamespace = "XMIPS"
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
index f89d94f41b69f..36d63ed23b925 100644
--- a/llvm/lib/Target/RISCV/RISCVProcessors.td
+++ b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -121,7 +121,8 @@ def MIPS_P8700 : RISCVProcessorModel<"mips-p8700",
FeatureStdExtZicsr,
FeatureVendorXMIPSCMov,
FeatureVendorXMIPSLSP,
- FeatureVendorXMIPSCBOP],
+ FeatureVendorXMIPSCBOP,
+ FeatureVendorXMIPSEXECTL],
[TuneMIPSP8700]>;
def ROCKET_RV32 : RISCVProcessorModel<"rocket-rv32",
diff --git a/llvm/test/CodeGen/RISCV/features-info.ll b/llvm/test/CodeGen/RISCV/features-info.ll
index d13a5a4e2b9be..01b8c0eaadb05 100644
--- a/llvm/test/CodeGen/RISCV/features-info.ll
+++ b/llvm/test/CodeGen/RISCV/features-info.ll
@@ -199,6 +199,7 @@
; CHECK-NEXT: xcvsimd - 'XCVsimd' (CORE-V SIMD ALU).
; CHECK-NEXT: xmipscbop - 'XMIPSCBOP' (MIPS Software Prefetch).
; CHECK-NEXT: xmipscmov - 'XMIPSCMov' (MIPS conditional move instruction (mips.ccmov)).
+; CHECK-NEXT: mipsexectl - 'XMIPSEXECTL' (MIPS execution control).
; CHECK-NEXT: xmipslsp - 'XMIPSLSP' (MIPS optimization for hardware load-store bonding).
; CHECK-NEXT: xsfcease - 'XSfcease' (SiFive sf.cease Instruction).
; CHECK-NEXT: xsfmm128t - 'XSfmm128t' (TE=128 configuration).
diff --git a/llvm/test/MC/RISCV/xmips-invalid.s b/llvm/test/MC/RISCV/xmips-invalid.s
index a17d2e347f8d9..b63e3a8bdcdf1 100644
--- a/llvm/test/MC/RISCV/xmips-invalid.s
+++ b/llvm/test/MC/RISCV/xmips-invalid.s
@@ -1,5 +1,14 @@
# RUN: not llvm-mc -triple=riscv64 < %s 2>&1 | FileCheck %s -check-prefixes=CHECK-FEATURE
-# RUN: not llvm-mc -triple=riscv64 -mattr=+xmipslsp,+xmipscmov,+Xmipscbop < %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple=riscv64 -mattr=+xmipslsp,+xmipscmov,+xmipscbop,+xmipsexectl < %s 2>&1 | FileCheck %s
+
+mips.pause 10
+# CHECK: error: invalid operand for instruction
+
+mips.ehb 10
+# CHECK: error: invalid operand for instruction
+
+mips.ihb 10
+# CHECK: error: invalid operand for instruction
mips.pref 8, 512(a0)
# CHECK: error: immediate offset must be in the range [0, 511]
diff --git a/llvm/test/MC/RISCV/xmips-valid.s b/llvm/test/MC/RISCV/xmips-valid.s
index c5755ee81b499..d5f5ab06d2df0 100644
--- a/llvm/test/MC/RISCV/xmips-valid.s
+++ b/llvm/test/MC/RISCV/xmips-valid.s
@@ -1,9 +1,27 @@
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+xmipslsp,+xmipscmov,+xmipscbop -M no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+xmipslsp,+xmipscmov,+xmipscbop,+xmipsexectl -M no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+xmipslsp,+xmipscmov,+xmipscbop < %s \
-# RUN: | llvm-objdump --mattr=+xmipslsp,+xmipscmov,+xmipscbop -M no-aliases -d - \
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+xmipslsp,+xmipscmov,+xmipscbop,+xmipsexectl < %s \
+# RUN: | llvm-objdump --mattr=+xmipslsp,+xmipscmov,+xmipscbop,+xmipsexectl -M no-aliases -d - \
# RUN: | FileCheck -check-prefix=CHECK-DIS %s
+# CHECK-INST: mips.pause
+# CHECK-ENC: encoding: [0x13,0x10,0x50,0x00]
+mips.pause
+
+# CHECK-DIS: mips.pause
+
+# CHECK-INST: mips.ehb
+# CHECK-ENC: encoding: [0x13,0x10,0x30,0x00]
+mips.ehb
+
+# CHECK-DIS: mips.ehb
+
+# CHECK-INST: mips.ihb
+# CHECK-ENC: encoding: [0x13,0x10,0x10,0x00]
+mips.ihb
+
+# CHECK-DIS: mips.ihb
+
# CHECK-INST: mips.pref 8, 511(a0)
# CHECK-ENC: encoding: [0x0b,0x04,0xf5,0x1f]
mips.pref 8, 511(a0)
diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
index cb4fbcae2f4da..d10dcb683652a 100644
--- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
+++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
@@ -1146,6 +1146,7 @@ R"(All available -march extensions for RISC-V
xcvsimd 1.0
xmipscbop 1.0
xmipscmov 1.0
+ xmipsexectl 1.0
xmipslsp 1.0
xsfcease 1.0
xsfmm128t 0.6
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