[llvm] 46dc8ef - [RISCV] Compress shxadd to qc.c.muliadd when rd = rs2 (#155843)

[via llvm-commits]

Author: Sudharsan Veeravalli
Date: 2025-09-01T12:34:25+05:30
New Revision: 46dc8ef2d3eebb6f588354d442ce4c07d46e9ea3

URL: https://github.com/llvm/llvm-project/commit/46dc8ef2d3eebb6f588354d442ce4c07d46e9ea3
DIFF: https://github.com/llvm/llvm-project/commit/46dc8ef2d3eebb6f588354d442ce4c07d46e9ea3.diff

LOG: [RISCV] Compress shxadd to qc.c.muliadd when rd = rs2 (#155843)

Do this when Zba and Xqciac are both enabled.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
    llvm/test/CodeGen/RISCV/xqciac.ll
    llvm/test/MC/RISCV/xqciac-valid.s

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 2c64b0c220fba..31ea1b4c70a14 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -1738,10 +1738,19 @@ def : CompressPat<(QC_E_XORAI GPRNoX0:$rd, simm12:$imm),
                   (XORI GPRNoX0:$rd, GPRNoX0:$rd, simm12:$imm)>;
 } // let isCompressOnly = true, Predicates = [HasVendorXqcilia, IsRV32]
 
-let Predicates = [HasVendorXqciac, IsRV32] in {
+let isCompressOnly = true, Predicates = [HasVendorXqciac, IsRV32] in {
 def : CompressPat<(QC_MULIADD GPRC:$rd, GPRC:$rs1, uimm5:$imm5),
                   (QC_C_MULIADD GPRC:$rd, GPRC:$rs1, uimm5:$imm5)>;
-}
+} // isCompressOnly = true, Predicates = [HasVendorXqciac, IsRV32]
+
+let isCompressOnly = true, Predicates = [HasVendorXqciac, HasStdExtZba, IsRV32] in {
+def : CompressPat<(SH1ADD GPRC:$rd, GPRC:$rs1, GPRC:$rd),
+                  (QC_C_MULIADD GPRC:$rd, GPRC:$rs1, 2)>;
+def : CompressPat<(SH2ADD GPRC:$rd, GPRC:$rs1, GPRC:$rd),
+                  (QC_C_MULIADD GPRC:$rd, GPRC:$rs1, 4)>;
+def : CompressPat<(SH3ADD GPRC:$rd, GPRC:$rs1, GPRC:$rd),
+                  (QC_C_MULIADD GPRC:$rd, GPRC:$rs1, 8)>;
+} // isCompressOnly = true, Predicates = [HasVendorXqciac, HasStdExtZba, IsRV32]
 
 let isCompressOnly = true, Predicates = [HasVendorXqcibi, IsRV32] in {
 def : CompressPat<(QC_E_BEQI GPRNoX0:$rs1, simm5nonzero:$imm5, bare_simm13_lsb0:$imm12),

diff  --git a/llvm/test/CodeGen/RISCV/xqciac.ll b/llvm/test/CodeGen/RISCV/xqciac.ll
index 934deb5a0c327..c76e1a9d64f17 100644
--- a/llvm/test/CodeGen/RISCV/xqciac.ll
+++ b/llvm/test/CodeGen/RISCV/xqciac.ll
@@ -259,7 +259,7 @@ define dso_local i32 @shxadd(i32 %a, i32 %b) local_unnamed_addr #0 {
 ;
 ; RV32IZBAMXQCIAC-LABEL: shxadd:
 ; RV32IZBAMXQCIAC:       # %bb.0: # %entry
-; RV32IZBAMXQCIAC-NEXT:    sh1add a0, a1, a0
+; RV32IZBAMXQCIAC-NEXT:    qc.c.muliadd a0, a1, 2
 ; RV32IZBAMXQCIAC-NEXT:    ret
 entry:
   %mul = mul nsw i32 %b, 2

diff  --git a/llvm/test/MC/RISCV/xqciac-valid.s b/llvm/test/MC/RISCV/xqciac-valid.s
index 1afebc75cb45a..02e63a0e7f12a 100644
--- a/llvm/test/MC/RISCV/xqciac-valid.s
+++ b/llvm/test/MC/RISCV/xqciac-valid.s
@@ -1,27 +1,27 @@
 # Xqciac - Qualcomm uC Load-Store Address Calculation Extension
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqciac -M no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqciac,+zba -M no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-NOALIAS %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqciac < %s \
-# RUN:     | llvm-objdump --mattr=+experimental-xqciac -M no-aliases --no-print-imm-hex -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqciac,+zba < %s \
+# RUN:     | llvm-objdump --mattr=+experimental-xqciac,+zba -M no-aliases --no-print-imm-hex -d - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST %s
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqciac -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqciac,+zba -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-ALIAS %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqciac < %s \
-# RUN:     | llvm-objdump --mattr=+experimental-xqciac --no-print-imm-hex -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqciac,+zba < %s \
+# RUN:     | llvm-objdump --mattr=+experimental-xqciac,+zba --no-print-imm-hex -d - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST %s
 
 # CHECK-NOALIAS: qc.c.muliadd    a0, a1, 0
-# CHECK-ALIAS: qc.muliadd    a0, a1, 0
+# CHECK-ALIAS: qc.c.muliadd    a0, a1, 0
 # CHECK-ENC: encoding: [0x8a,0x21]
 qc.c.muliadd x10, x11, 0
 
 # CHECK-NOALIAS: qc.c.muliadd    a0, a1, 31
-# CHECK-ALIAS: qc.muliadd    a0, a1, 31
+# CHECK-ALIAS: qc.c.muliadd    a0, a1, 31
 # CHECK-ENC: encoding: [0xea,0x3d]
 qc.c.muliadd x10, x11, 31
 
 # CHECK-NOALIAS: qc.c.muliadd    a0, a1, 16
-# CHECK-ALIAS: qc.muliadd    a0, a1, 16
+# CHECK-ALIAS: qc.c.muliadd    a0, a1, 16
 # CHECK-ENC: encoding: [0xaa,0x21]
 qc.c.muliadd x10, x11, 16
 
@@ -54,7 +54,21 @@ qc.shladd x10, x11, x12, 31
 # Check that compress pattern for qc.muliadd works
 
 # CHECK-NOALIAS: qc.c.muliadd    a0, a1, 16
-# CHECK-ALIAS: qc.muliadd    a0, a1, 16
+# CHECK-ALIAS: qc.c.muliadd    a0, a1, 16
 # CHECK-ENC: encoding: [0xaa,0x21]
 qc.muliadd x10, x11, 16
 
+# CHECK-NOALIAS: qc.c.muliadd    a0, a1, 2
+# CHECK-ALIAS: qc.c.muliadd    a0, a1, 2
+# CHECK-ENC: encoding: [0x8a,0x25]
+sh1add x10, x11, x10
+
+# CHECK-NOALIAS: qc.c.muliadd    a0, a1, 4
+# CHECK-ALIAS: qc.c.muliadd    a0, a1, 4
+# CHECK-ENC: encoding: [0x8a,0x29]
+sh2add x10, x11, x10
+
+# CHECK-NOALIAS: qc.c.muliadd    a0, a1, 8
+# CHECK-ALIAS: qc.c.muliadd    a0, a1, 8
+# CHECK-ENC: encoding: [0x8a,0x31]
+sh3add x10, x11, x10