[llvm] [LoongArch] Enable vector tests for 32-bit target (PR #152094)
via llvm-commits
llvm-commits at lists.llvm.org
Sun Aug 31 19:51:39 PDT 2025
https://github.com/heiher updated https://github.com/llvm/llvm-project/pull/152094
>From be722bb8b4455a97df323cb03a43fe124723442e Mon Sep 17 00:00:00 2001
From: WANG Rui <wangrui at loongson.cn>
Date: Tue, 5 Aug 2025 12:04:33 +0800
Subject: [PATCH] [LoongArch] Enable vector tests for 32-bit target
---
.../LoongArch/LoongArchISelDAGToDAG.cpp | 13 +-
.../LoongArch/LoongArchISelLowering.cpp | 128 +-
.../Target/LoongArch/LoongArchLSXInstrInfo.td | 2 +-
.../CodeGen/LoongArch/lasx/broadcast-load.ll | 101 +-
llvm/test/CodeGen/LoongArch/lasx/bswap.ll | 1 +
.../CodeGen/LoongArch/lasx/build-vector.ll | 1414 +++++++++-----
.../CodeGen/LoongArch/lasx/concat-vectors.ll | 1 +
.../test/CodeGen/LoongArch/lasx/ctpop-ctlz.ll | 1 +
.../lasx/fdiv-reciprocal-estimate.ll | 163 +-
llvm/test/CodeGen/LoongArch/lasx/fma-v4f64.ll | 1688 +++++++++++------
llvm/test/CodeGen/LoongArch/lasx/fma-v8f32.ll | 1688 +++++++++++------
.../lasx/fsqrt-reciprocal-estimate.ll | 271 ++-
llvm/test/CodeGen/LoongArch/lasx/fsqrt.ll | 198 +-
.../lasx/inline-asm-operand-modifier.ll | 1 +
.../LoongArch/lasx/inline-asm-reg-names.ll | 34 +-
.../lasx/insert-extract-subvector.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-absd.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-add.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-adda.ll | 1 +
.../lasx/intrinsic-addi-invalid-imm.ll | 1 +
.../LoongArch/lasx/intrinsic-addi-non-imm.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-addi.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-addw.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-and.ll | 1 +
.../lasx/intrinsic-andi-invalid-imm.ll | 1 +
.../LoongArch/lasx/intrinsic-andi-non-imm.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-andi.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-andn.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-avg.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-avgr.ll | 1 +
.../lasx/intrinsic-bitclr-invalid-imm.ll | 1 +
.../lasx/intrinsic-bitclr-non-imm.ll | 1 +
.../LoongArch/lasx/intrinsic-bitclr.ll | 22 +-
.../lasx/intrinsic-bitrev-invalid-imm.ll | 1 +
.../lasx/intrinsic-bitrev-non-imm.ll | 1 +
.../LoongArch/lasx/intrinsic-bitrev.ll | 20 +-
.../LoongArch/lasx/intrinsic-bitsel.ll | 1 +
.../lasx/intrinsic-bitseli-invalid-imm.ll | 1 +
.../lasx/intrinsic-bitseli-non-imm.ll | 1 +
.../LoongArch/lasx/intrinsic-bitseli.ll | 1 +
.../lasx/intrinsic-bitset-invalid-imm.ll | 1 +
.../lasx/intrinsic-bitset-non-imm.ll | 1 +
.../LoongArch/lasx/intrinsic-bitset.ll | 20 +-
.../lasx/intrinsic-bsll-invalid-imm.ll | 1 +
.../LoongArch/lasx/intrinsic-bsll-non-imm.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-bsll.ll | 1 +
.../lasx/intrinsic-bsrl-invalid-imm.ll | 1 +
.../LoongArch/lasx/intrinsic-bsrl-non-imm.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-bsrl.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-clo.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-clz.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-div.ll | 1 +
.../LoongArch/lasx/intrinsic-ext2xv.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-exth.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-extl.ll | 1 +
.../lasx/intrinsic-extrins-invalid-imm.ll | 1 +
.../lasx/intrinsic-extrins-non-imm.ll | 1 +
.../LoongArch/lasx/intrinsic-extrins.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-fadd.ll | 1 +
.../LoongArch/lasx/intrinsic-fclass.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-fcmp.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-fcvt.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-fcvth.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-fcvtl.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-fdiv.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-ffint.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-flogb.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-fmadd.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-fmax.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-fmaxa.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-fmin.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-fmina.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-fmsub.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-fmul.ll | 1 +
.../LoongArch/lasx/intrinsic-fnmadd.ll | 1 +
.../LoongArch/lasx/intrinsic-fnmsub.ll | 1 +
.../LoongArch/lasx/intrinsic-frecip.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-frint.ll | 1 +
.../LoongArch/lasx/intrinsic-frsqrt.ll | 1 +
.../lasx/intrinsic-frstp-invalid-imm.ll | 1 +
.../LoongArch/lasx/intrinsic-frstp-non-imm.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-frstp.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-fsqrt.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-fsub.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-ftint.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-haddw.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-hsubw.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-ilv.ll | 1 +
.../lasx/intrinsic-insgr2vr-invalid-imm.ll | 1 +
.../lasx/intrinsic-insgr2vr-non-imm.ll | 1 +
.../LoongArch/lasx/intrinsic-insgr2vr.ll | 20 +-
.../lasx/intrinsic-insve0-invalid-imm.ll | 1 +
.../lasx/intrinsic-insve0-non-imm.ll | 1 +
.../LoongArch/lasx/intrinsic-insve0.ll | 1 +
.../lasx/intrinsic-ld-invalid-imm.ll | 1 +
.../LoongArch/lasx/intrinsic-ld-non-imm.ll | 1 +
.../lasx/intrinsic-ldi-invalid-imm.ll | 1 +
.../LoongArch/lasx/intrinsic-ldi-non-imm.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-ldi.ll | 1 +
.../lasx/intrinsic-ldrepl-invalid-imm.ll | 1 +
.../lasx/intrinsic-ldrepl-non-imm.ll | 1 +
.../LoongArch/lasx/intrinsic-ldrepl.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-madd.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-maddw.ll | 1 +
.../LoongArch/lasx/intrinsic-max-non-imm.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-max.ll | 1 +
.../LoongArch/lasx/intrinsic-min-non-imm.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-min.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-mod.ll | 1 +
.../LoongArch/lasx/intrinsic-mskgez.ll | 1 +
.../LoongArch/lasx/intrinsic-mskltz.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-msknz.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-msub.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-muh.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-mul.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-mulw.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-neg.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-nor.ll | 1 +
.../lasx/intrinsic-nori-invalid-imm.ll | 1 +
.../LoongArch/lasx/intrinsic-nori-non-imm.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-nori.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-or.ll | 1 +
.../lasx/intrinsic-ori-invalid-imm.ll | 1 +
.../LoongArch/lasx/intrinsic-ori-non-imm.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-ori.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-orn.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-pack.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-pcnt.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-perm.ll | 1 +
.../lasx/intrinsic-permi-invalid-imm.ll | 1 +
.../LoongArch/lasx/intrinsic-permi-non-imm.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-permi.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-pick.ll | 1 +
.../lasx/intrinsic-pickve-invalid-imm.ll | 1 +
.../lasx/intrinsic-pickve-non-imm.ll | 1 +
.../LoongArch/lasx/intrinsic-pickve.ll | 1 +
.../lasx/intrinsic-pickve2gr-non-imm.ll | 1 +
.../lasx/intrinsic-repl128vei-invalid-imm.ll | 1 +
.../lasx/intrinsic-repl128vei-non-imm.ll | 1 +
.../LoongArch/lasx/intrinsic-repl128vei.ll | 1 +
.../LoongArch/lasx/intrinsic-replve.ll | 1 +
.../LoongArch/lasx/intrinsic-replve0.ll | 1 +
.../lasx/intrinsic-rotr-invalid-imm.ll | 1 +
.../LoongArch/lasx/intrinsic-rotr-non-imm.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-rotr.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-sadd.ll | 1 +
.../lasx/intrinsic-sat-invalid-imm.ll | 1 +
.../LoongArch/lasx/intrinsic-sat-non-imm.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-sat.ll | 1 +
.../lasx/intrinsic-seq-invalid-imm.ll | 1 +
.../LoongArch/lasx/intrinsic-seq-non-imm.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-seq.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-shuf.ll | 1 +
.../lasx/intrinsic-shuf4i-invalid-imm.ll | 1 +
.../lasx/intrinsic-shuf4i-non-imm.ll | 1 +
.../LoongArch/lasx/intrinsic-shuf4i.ll | 1 +
.../LoongArch/lasx/intrinsic-signcov.ll | 1 +
.../lasx/intrinsic-sle-invalid-imm.ll | 1 +
.../LoongArch/lasx/intrinsic-sle-non-imm.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-sle.ll | 1 +
.../lasx/intrinsic-sll-invalid-imm.ll | 1 +
.../LoongArch/lasx/intrinsic-sll-non-imm.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-sll.ll | 18 +-
.../lasx/intrinsic-sllwil-invalid-imm.ll | 1 +
.../lasx/intrinsic-sllwil-non-imm.ll | 1 +
.../LoongArch/lasx/intrinsic-sllwil.ll | 1 +
.../lasx/intrinsic-slt-invalid-imm.ll | 1 +
.../LoongArch/lasx/intrinsic-slt-non-imm.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-slt.ll | 1 +
.../lasx/intrinsic-sra-invalid-imm.ll | 1 +
.../LoongArch/lasx/intrinsic-sra-non-imm.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-sra.ll | 18 +-
.../CodeGen/LoongArch/lasx/intrinsic-sran.ll | 1 +
.../lasx/intrinsic-srani-invalid-imm.ll | 1 +
.../LoongArch/lasx/intrinsic-srani-non-imm.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-srani.ll | 1 +
.../lasx/intrinsic-srar-invalid-imm.ll | 1 +
.../LoongArch/lasx/intrinsic-srar-non-imm.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-srar.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-srarn.ll | 1 +
.../lasx/intrinsic-srarni-invalid-imm.ll | 1 +
.../lasx/intrinsic-srarni-non-imm.ll | 1 +
.../LoongArch/lasx/intrinsic-srarni.ll | 1 +
.../lasx/intrinsic-srl-invalid-imm.ll | 1 +
.../LoongArch/lasx/intrinsic-srl-non-imm.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-srl.ll | 18 +-
.../CodeGen/LoongArch/lasx/intrinsic-srln.ll | 1 +
.../lasx/intrinsic-srlni-invalid-imm.ll | 1 +
.../LoongArch/lasx/intrinsic-srlni-non-imm.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-srlni.ll | 1 +
.../lasx/intrinsic-srlr-invalid-imm.ll | 1 +
.../LoongArch/lasx/intrinsic-srlr-non-imm.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-srlr.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-srlrn.ll | 1 +
.../lasx/intrinsic-srlrni-invalid-imm.ll | 1 +
.../lasx/intrinsic-srlrni-non-imm.ll | 1 +
.../LoongArch/lasx/intrinsic-srlrni.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-ssran.ll | 1 +
.../lasx/intrinsic-ssrani-invalid-imm.ll | 1 +
.../lasx/intrinsic-ssrani-non-imm.ll | 1 +
.../LoongArch/lasx/intrinsic-ssrani.ll | 1 +
.../LoongArch/lasx/intrinsic-ssrarn.ll | 1 +
.../lasx/intrinsic-ssrarni-invalid-imm.ll | 1 +
.../lasx/intrinsic-ssrarni-non-imm.ll | 1 +
.../LoongArch/lasx/intrinsic-ssrarni.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-ssrln.ll | 1 +
.../lasx/intrinsic-ssrlni-invalid-imm.ll | 1 +
.../lasx/intrinsic-ssrlni-non-imm.ll | 1 +
.../LoongArch/lasx/intrinsic-ssrlni.ll | 1 +
.../LoongArch/lasx/intrinsic-ssrlrn.ll | 1 +
.../lasx/intrinsic-ssrlrni-invalid-imm.ll | 1 +
.../lasx/intrinsic-ssrlrni-non-imm.ll | 1 +
.../LoongArch/lasx/intrinsic-ssrlrni.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-ssub.ll | 1 +
.../lasx/intrinsic-st-invalid-imm.ll | 1 +
.../LoongArch/lasx/intrinsic-st-non-imm.ll | 1 +
.../lasx/intrinsic-stelm-invalid-imm.ll | 1 +
.../LoongArch/lasx/intrinsic-stelm-non-imm.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-stelm.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-sub.ll | 1 +
.../lasx/intrinsic-subi-invalid-imm.ll | 1 +
.../LoongArch/lasx/intrinsic-subi-non-imm.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-subi.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-subw.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-xor.ll | 1 +
.../lasx/intrinsic-xori-invalid-imm.ll | 1 +
.../LoongArch/lasx/intrinsic-xori-non-imm.ll | 1 +
.../CodeGen/LoongArch/lasx/intrinsic-xori.ll | 1 +
.../LoongArch/lasx/ir-instruction/absd.ll | 1 +
.../LoongArch/lasx/ir-instruction/add.ll | 1 +
.../LoongArch/lasx/ir-instruction/and.ll | 1 +
.../LoongArch/lasx/ir-instruction/ashr.ll | 1 +
.../ir-instruction/bitcast-extract-element.ll | 32 +-
.../LoongArch/lasx/ir-instruction/fadd.ll | 1 +
.../LoongArch/lasx/ir-instruction/fcmp.ll | 1 +
.../LoongArch/lasx/ir-instruction/fdiv.ll | 24 +-
.../lasx/ir-instruction/fix-xvshuf.ll | 1 +
.../LoongArch/lasx/ir-instruction/fmul.ll | 1 +
.../LoongArch/lasx/ir-instruction/fneg.ll | 1 +
.../LoongArch/lasx/ir-instruction/fptosi.ll | 1 +
.../LoongArch/lasx/ir-instruction/fptoui.ll | 1 +
.../LoongArch/lasx/ir-instruction/fsub.ll | 1 +
.../LoongArch/lasx/ir-instruction/icmp.ll | 1 +
.../ir-instruction/insert-bitcast-element.ll | 32 +-
.../LoongArch/lasx/ir-instruction/lshr.ll | 1 +
.../LoongArch/lasx/ir-instruction/mul.ll | 1 +
.../LoongArch/lasx/ir-instruction/or.ll | 1 +
.../LoongArch/lasx/ir-instruction/sdiv.ll | 1 +
.../LoongArch/lasx/ir-instruction/shl.ll | 1 +
.../lasx/ir-instruction/shuffle-as-xvilv.ll | 1 +
.../lasx/ir-instruction/shuffle-as-xvpack.ll | 1 +
.../lasx/ir-instruction/shuffle-as-xvpick.ll | 1 +
.../LoongArch/lasx/ir-instruction/sitofp.ll | 1 +
.../LoongArch/lasx/ir-instruction/sub.ll | 1 +
.../LoongArch/lasx/ir-instruction/udiv.ll | 1 +
.../LoongArch/lasx/ir-instruction/uitofp.ll | 1 +
.../LoongArch/lasx/ir-instruction/xor.ll | 1 +
.../CodeGen/LoongArch/lasx/issue107355.ll | 65 +-
llvm/test/CodeGen/LoongArch/lasx/mulh.ll | 1 +
.../LoongArch/lasx/scalar-to-vector.ll | 17 +-
.../LoongArch/lasx/vec-shuffle-bit-shift.ll | 1 +
.../LoongArch/lasx/vec-shuffle-byte-shift.ll | 1 +
llvm/test/CodeGen/LoongArch/lasx/vselect.ll | 33 +-
.../LoongArch/lasx/widen-shuffle-mask.ll | 1 +
.../CodeGen/LoongArch/lsx/broadcast-load.ll | 83 +-
llvm/test/CodeGen/LoongArch/lsx/bswap.ll | 3 +-
.../CodeGen/LoongArch/lsx/build-vector.ll | 58 +-
llvm/test/CodeGen/LoongArch/lsx/ctpop-ctlz.ll | 3 +-
.../LoongArch/lsx/fdiv-reciprocal-estimate.ll | 135 +-
llvm/test/CodeGen/LoongArch/lsx/fma-v2f64.ll | 6 +
llvm/test/CodeGen/LoongArch/lsx/fma-v4f32.ll | 6 +
llvm/test/CodeGen/LoongArch/lsx/fpowi.ll | 222 ++-
.../lsx/fsqrt-reciprocal-estimate.ll | 116 +-
llvm/test/CodeGen/LoongArch/lsx/fsqrt.ll | 25 +-
.../lsx/inline-asm-operand-modifier.ll | 3 +-
.../LoongArch/lsx/inline-asm-reg-names.ll | 34 +-
.../CodeGen/LoongArch/lsx/intrinsic-absd.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-add.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-adda.ll | 1 +
.../lsx/intrinsic-addi-invalid-imm.ll | 1 +
.../LoongArch/lsx/intrinsic-addi-non-imm.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-addi.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-addw.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-and.ll | 1 +
.../lsx/intrinsic-andi-invalid-imm.ll | 1 +
.../LoongArch/lsx/intrinsic-andi-non-imm.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-andi.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-andn.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-avg.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-avgr.ll | 1 +
.../lsx/intrinsic-bitclr-invalid-imm.ll | 1 +
.../LoongArch/lsx/intrinsic-bitclr-non-imm.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-bitclr.ll | 37 +-
.../lsx/intrinsic-bitrev-invalid-imm.ll | 1 +
.../LoongArch/lsx/intrinsic-bitrev-non-imm.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-bitrev.ll | 35 +-
.../CodeGen/LoongArch/lsx/intrinsic-bitsel.ll | 1 +
.../lsx/intrinsic-bitseli-invalid-imm.ll | 1 +
.../lsx/intrinsic-bitseli-non-imm.ll | 1 +
.../LoongArch/lsx/intrinsic-bitseli.ll | 1 +
.../lsx/intrinsic-bitset-invalid-imm.ll | 1 +
.../LoongArch/lsx/intrinsic-bitset-non-imm.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-bitset.ll | 35 +-
.../lsx/intrinsic-bsll-invalid-imm.ll | 1 +
.../LoongArch/lsx/intrinsic-bsll-non-imm.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-bsll.ll | 1 +
.../lsx/intrinsic-bsrl-invalid-imm.ll | 1 +
.../LoongArch/lsx/intrinsic-bsrl-non-imm.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-bsrl.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-clo.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-clz.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-div.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-exth.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-extl.ll | 1 +
.../lsx/intrinsic-extrins-invalid-imm.ll | 1 +
.../lsx/intrinsic-extrins-non-imm.ll | 1 +
.../LoongArch/lsx/intrinsic-extrins.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-fadd.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-fclass.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-fcvt.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-fcvth.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-fcvtl.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-fdiv.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-ffint.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-flogb.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-fmadd.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-fmax.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-fmaxa.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-fmin.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-fmina.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-fmsub.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-fmul.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-fnmadd.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-fnmsub.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-frecip.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-frint.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-frsqrt.ll | 1 +
.../lsx/intrinsic-frstp-invalid-imm.ll | 1 +
.../LoongArch/lsx/intrinsic-frstp-non-imm.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-frstp.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-fsqrt.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-fsub.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-ftint.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-haddw.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-hsubw.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-ilv.ll | 1 +
.../lsx/intrinsic-insgr2vr-invalid-imm.ll | 1 +
.../lsx/intrinsic-insgr2vr-non-imm.ll | 1 +
.../LoongArch/lsx/intrinsic-insgr2vr.ll | 20 +-
.../LoongArch/lsx/intrinsic-ld-invalid-imm.ll | 1 +
.../LoongArch/lsx/intrinsic-ld-non-imm.ll | 1 +
.../lsx/intrinsic-ldi-invalid-imm.ll | 1 +
.../LoongArch/lsx/intrinsic-ldi-non-imm.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-ldi.ll | 1 +
.../lsx/intrinsic-ldrepl-invalid-imm.ll | 1 +
.../LoongArch/lsx/intrinsic-ldrepl-non-imm.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-ldrepl.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-madd.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-maddw.ll | 1 +
.../LoongArch/lsx/intrinsic-max-non-imm.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-max.ll | 1 +
.../LoongArch/lsx/intrinsic-min-non-imm.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-min.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-mod.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-mskgez.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-mskltz.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-msknz.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-msub.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-muh.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-mul.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-mulw.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-neg.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-nor.ll | 1 +
.../lsx/intrinsic-nori-invalid-imm.ll | 1 +
.../LoongArch/lsx/intrinsic-nori-non-imm.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-nori.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-or.ll | 1 +
.../lsx/intrinsic-ori-invalid-imm.ll | 1 +
.../LoongArch/lsx/intrinsic-ori-non-imm.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-ori.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-orn.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-pack.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-pcnt.ll | 1 +
.../lsx/intrinsic-permi-invalid-imm.ll | 1 +
.../LoongArch/lsx/intrinsic-permi-non-imm.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-permi.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-pick.ll | 1 +
.../lsx/intrinsic-pickve2gr-non-imm.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-replve.ll | 1 +
.../lsx/intrinsic-replvei-invalid-imm.ll | 1 +
.../lsx/intrinsic-replvei-non-imm.ll | 1 +
.../LoongArch/lsx/intrinsic-replvei.ll | 1 +
.../lsx/intrinsic-rotr-invalid-imm.ll | 1 +
.../LoongArch/lsx/intrinsic-rotr-non-imm.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-rotr.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-sadd.ll | 1 +
.../lsx/intrinsic-sat-invalid-imm.ll | 1 +
.../LoongArch/lsx/intrinsic-sat-non-imm.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-sat.ll | 1 +
.../lsx/intrinsic-seq-invalid-imm.ll | 1 +
.../LoongArch/lsx/intrinsic-seq-non-imm.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-seq.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-shuf.ll | 1 +
.../lsx/intrinsic-shuf4i-invalid-imm.ll | 1 +
.../LoongArch/lsx/intrinsic-shuf4i-non-imm.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-shuf4i.ll | 1 +
.../LoongArch/lsx/intrinsic-signcov.ll | 1 +
.../lsx/intrinsic-sle-invalid-imm.ll | 1 +
.../LoongArch/lsx/intrinsic-sle-non-imm.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-sle.ll | 1 +
.../lsx/intrinsic-sll-invalid-imm.ll | 1 +
.../LoongArch/lsx/intrinsic-sll-non-imm.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-sll.ll | 18 +-
.../lsx/intrinsic-sllwil-invalid-imm.ll | 1 +
.../LoongArch/lsx/intrinsic-sllwil-non-imm.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-sllwil.ll | 1 +
.../lsx/intrinsic-slt-invalid-imm.ll | 1 +
.../LoongArch/lsx/intrinsic-slt-non-imm.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-slt.ll | 1 +
.../lsx/intrinsic-sra-invalid-imm.ll | 1 +
.../LoongArch/lsx/intrinsic-sra-non-imm.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-sra.ll | 18 +-
.../CodeGen/LoongArch/lsx/intrinsic-sran.ll | 1 +
.../lsx/intrinsic-srani-invalid-imm.ll | 1 +
.../LoongArch/lsx/intrinsic-srani-non-imm.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-srani.ll | 1 +
.../lsx/intrinsic-srar-invalid-imm.ll | 1 +
.../LoongArch/lsx/intrinsic-srar-non-imm.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-srar.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-srarn.ll | 1 +
.../lsx/intrinsic-srarni-invalid-imm.ll | 1 +
.../LoongArch/lsx/intrinsic-srarni-non-imm.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-srarni.ll | 1 +
.../lsx/intrinsic-srl-invalid-imm.ll | 1 +
.../LoongArch/lsx/intrinsic-srl-non-imm.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-srl.ll | 18 +-
.../CodeGen/LoongArch/lsx/intrinsic-srln.ll | 1 +
.../lsx/intrinsic-srlni-invalid-imm.ll | 1 +
.../LoongArch/lsx/intrinsic-srlni-non-imm.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-srlni.ll | 1 +
.../lsx/intrinsic-srlr-invalid-imm.ll | 1 +
.../LoongArch/lsx/intrinsic-srlr-non-imm.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-srlr.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-srlrn.ll | 1 +
.../lsx/intrinsic-srlrni-invalid-imm.ll | 1 +
.../LoongArch/lsx/intrinsic-srlrni-non-imm.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-srlrni.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-ssran.ll | 1 +
.../lsx/intrinsic-ssrani-invalid-imm.ll | 1 +
.../LoongArch/lsx/intrinsic-ssrani-non-imm.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-ssrani.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-ssrarn.ll | 1 +
.../lsx/intrinsic-ssrarni-invalid-imm.ll | 1 +
.../lsx/intrinsic-ssrarni-non-imm.ll | 1 +
.../LoongArch/lsx/intrinsic-ssrarni.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-ssrln.ll | 1 +
.../lsx/intrinsic-ssrlni-invalid-imm.ll | 1 +
.../LoongArch/lsx/intrinsic-ssrlni-non-imm.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-ssrlni.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-ssrlrn.ll | 1 +
.../lsx/intrinsic-ssrlrni-invalid-imm.ll | 1 +
.../lsx/intrinsic-ssrlrni-non-imm.ll | 1 +
.../LoongArch/lsx/intrinsic-ssrlrni.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-ssub.ll | 1 +
.../LoongArch/lsx/intrinsic-st-invalid-imm.ll | 1 +
.../LoongArch/lsx/intrinsic-st-non-imm.ll | 1 +
.../lsx/intrinsic-stelm-invalid-imm.ll | 1 +
.../LoongArch/lsx/intrinsic-stelm-non-imm.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-stelm.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-sub.ll | 1 +
.../lsx/intrinsic-subi-invalid-imm.ll | 1 +
.../LoongArch/lsx/intrinsic-subi-non-imm.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-subi.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-subw.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-xor.ll | 1 +
.../lsx/intrinsic-xori-invalid-imm.ll | 1 +
.../LoongArch/lsx/intrinsic-xori-non-imm.ll | 1 +
.../CodeGen/LoongArch/lsx/intrinsic-xori.ll | 1 +
.../LoongArch/lsx/ir-instruction/absd.ll | 1 +
.../LoongArch/lsx/ir-instruction/add.ll | 1 +
.../LoongArch/lsx/ir-instruction/and.ll | 1 +
.../LoongArch/lsx/ir-instruction/ashr.ll | 1 +
.../ir-instruction/bitcast-extract-element.ll | 32 +-
.../LoongArch/lsx/ir-instruction/fadd.ll | 1 +
.../LoongArch/lsx/ir-instruction/fcmp.ll | 1 +
.../LoongArch/lsx/ir-instruction/fdiv.ll | 24 +-
.../LoongArch/lsx/ir-instruction/fmul.ll | 1 +
.../LoongArch/lsx/ir-instruction/fneg.ll | 1 +
.../LoongArch/lsx/ir-instruction/fptosi.ll | 1 +
.../LoongArch/lsx/ir-instruction/fptoui.ll | 1 +
.../LoongArch/lsx/ir-instruction/fsub.ll | 1 +
.../LoongArch/lsx/ir-instruction/icmp.ll | 1 +
.../ir-instruction/insert-bitcast-element.ll | 32 +-
.../ir-instruction/insert-extract-element.ll | 19 +-
.../LoongArch/lsx/ir-instruction/lshr.ll | 1 +
.../LoongArch/lsx/ir-instruction/mul.ll | 1 +
.../LoongArch/lsx/ir-instruction/or.ll | 1 +
.../LoongArch/lsx/ir-instruction/sdiv.ll | 1 +
.../LoongArch/lsx/ir-instruction/shl.ll | 1 +
.../lsx/ir-instruction/shuffle-as-vilv.ll | 1 +
.../lsx/ir-instruction/shuffle-as-vpack.ll | 1 +
.../lsx/ir-instruction/shuffle-as-vpick.ll | 1 +
.../LoongArch/lsx/ir-instruction/sitofp.ll | 1 +
.../LoongArch/lsx/ir-instruction/sub.ll | 1 +
.../LoongArch/lsx/ir-instruction/udiv.ll | 1 +
.../LoongArch/lsx/ir-instruction/uitofp.ll | 1 +
.../LoongArch/lsx/ir-instruction/xor.ll | 1 +
llvm/test/CodeGen/LoongArch/lsx/mulh.ll | 1 +
llvm/test/CodeGen/LoongArch/lsx/pr116008.ll | 1 +
.../CodeGen/LoongArch/lsx/scalar-to-vector.ll | 17 +-
.../LoongArch/lsx/vec-shuffle-bit-shift.ll | 1 +
.../LoongArch/lsx/vec-shuffle-sign-ext.ll | 83 +-
llvm/test/CodeGen/LoongArch/lsx/vec-zext.ll | 83 +-
llvm/test/CodeGen/LoongArch/lsx/vselect.ll | 33 +-
514 files changed, 5396 insertions(+), 2304 deletions(-)
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp b/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
index 71d0263fe3760..07e722b9a6591 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.cpp
@@ -114,7 +114,7 @@ void LoongArchDAGToDAGISel::Select(SDNode *Node) {
unsigned SplatBitSize;
bool HasAnyUndefs;
unsigned Op;
- EVT ViaVecTy;
+ EVT ResTy = BVN->getValueType(0);
bool Is128Vec = BVN->getValueType(0).is128BitVector();
bool Is256Vec = BVN->getValueType(0).is256BitVector();
@@ -129,28 +129,25 @@ void LoongArchDAGToDAGISel::Select(SDNode *Node) {
break;
case 8:
Op = Is256Vec ? LoongArch::PseudoXVREPLI_B : LoongArch::PseudoVREPLI_B;
- ViaVecTy = Is256Vec ? MVT::v32i8 : MVT::v16i8;
break;
case 16:
Op = Is256Vec ? LoongArch::PseudoXVREPLI_H : LoongArch::PseudoVREPLI_H;
- ViaVecTy = Is256Vec ? MVT::v16i16 : MVT::v8i16;
break;
case 32:
Op = Is256Vec ? LoongArch::PseudoXVREPLI_W : LoongArch::PseudoVREPLI_W;
- ViaVecTy = Is256Vec ? MVT::v8i32 : MVT::v4i32;
break;
case 64:
Op = Is256Vec ? LoongArch::PseudoXVREPLI_D : LoongArch::PseudoVREPLI_D;
- ViaVecTy = Is256Vec ? MVT::v4i64 : MVT::v2i64;
break;
}
SDNode *Res;
// If we have a signed 10 bit integer, we can splat it directly.
if (SplatValue.isSignedIntN(10)) {
- SDValue Imm = CurDAG->getTargetConstant(SplatValue, DL,
- ViaVecTy.getVectorElementType());
- Res = CurDAG->getMachineNode(Op, DL, ViaVecTy, Imm);
+ EVT EleType = ResTy.getVectorElementType();
+ APInt Val = SplatValue.sextOrTrunc(EleType.getSizeInBits());
+ SDValue Imm = CurDAG->getTargetConstant(Val, DL, EleType);
+ Res = CurDAG->getMachineNode(Op, DL, ResTy, Imm);
ReplaceNode(Node, Res);
return;
}
diff --git a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
index 9854c731cd555..444a8cb841863 100644
--- a/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
+++ b/llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp
@@ -1117,6 +1117,7 @@ static int matchShuffleAsShift(MVT &ShiftVT, unsigned &Opcode,
static SDValue lowerVECTOR_SHUFFLEAsShift(const SDLoc &DL, ArrayRef<int> Mask,
MVT VT, SDValue V1, SDValue V2,
SelectionDAG &DAG,
+ const LoongArchSubtarget &Subtarget,
const APInt &Zeroable) {
int Size = Mask.size();
assert(Size == (int)VT.getVectorNumElements() && "Unexpected mask size");
@@ -1143,7 +1144,7 @@ static SDValue lowerVECTOR_SHUFFLEAsShift(const SDLoc &DL, ArrayRef<int> Mask,
"Illegal integer vector type");
V = DAG.getBitcast(ShiftVT, V);
V = DAG.getNode(Opcode, DL, ShiftVT, V,
- DAG.getConstant(ShiftAmt, DL, MVT::i64));
+ DAG.getConstant(ShiftAmt, DL, Subtarget.getGRLenVT()));
return DAG.getBitcast(VT, V);
}
@@ -1312,10 +1313,10 @@ static int matchShuffleAsByteRotate(MVT VT, SDValue &V1, SDValue &V2,
/// (VBSRL_V $v1, $v1, 8)
/// (VBSLL_V $v0, $v0, 8)
/// (VOR_V $v0, $V0, $v1)
-static SDValue lowerVECTOR_SHUFFLEAsByteRotate(const SDLoc &DL,
- ArrayRef<int> Mask, MVT VT,
- SDValue V1, SDValue V2,
- SelectionDAG &DAG) {
+static SDValue
+lowerVECTOR_SHUFFLEAsByteRotate(const SDLoc &DL, ArrayRef<int> Mask, MVT VT,
+ SDValue V1, SDValue V2, SelectionDAG &DAG,
+ const LoongArchSubtarget &Subtarget) {
SDValue Lo = V1, Hi = V2;
int ByteRotation = matchShuffleAsByteRotate(VT, Lo, Hi, Mask);
@@ -1328,11 +1329,12 @@ static SDValue lowerVECTOR_SHUFFLEAsByteRotate(const SDLoc &DL,
int LoByteShift = 16 - ByteRotation;
int HiByteShift = ByteRotation;
+ MVT GRLenVT = Subtarget.getGRLenVT();
SDValue LoShift = DAG.getNode(LoongArchISD::VBSLL, DL, ByteVT, Lo,
- DAG.getConstant(LoByteShift, DL, MVT::i64));
+ DAG.getConstant(LoByteShift, DL, GRLenVT));
SDValue HiShift = DAG.getNode(LoongArchISD::VBSRL, DL, ByteVT, Hi,
- DAG.getConstant(HiByteShift, DL, MVT::i64));
+ DAG.getConstant(HiByteShift, DL, GRLenVT));
return DAG.getBitcast(VT, DAG.getNode(ISD::OR, DL, ByteVT, LoShift, HiShift));
}
@@ -1437,9 +1439,10 @@ static SDValue lowerVECTOR_SHUFFLEAsZeroOrAnyExtend(const SDLoc &DL,
///
/// When undef's appear in the mask they are treated as if they were whatever
/// value is necessary in order to fit the above form.
-static SDValue lowerVECTOR_SHUFFLE_VREPLVEI(const SDLoc &DL, ArrayRef<int> Mask,
- MVT VT, SDValue V1, SDValue V2,
- SelectionDAG &DAG) {
+static SDValue
+lowerVECTOR_SHUFFLE_VREPLVEI(const SDLoc &DL, ArrayRef<int> Mask, MVT VT,
+ SDValue V1, SDValue V2, SelectionDAG &DAG,
+ const LoongArchSubtarget &Subtarget) {
int SplatIndex = -1;
for (const auto &M : Mask) {
if (M != -1) {
@@ -1455,7 +1458,7 @@ static SDValue lowerVECTOR_SHUFFLE_VREPLVEI(const SDLoc &DL, ArrayRef<int> Mask,
if (fitsRegularPattern<int>(Mask.begin(), 1, Mask.end(), SplatIndex, 0)) {
APInt Imm(64, SplatIndex);
return DAG.getNode(LoongArchISD::VREPLVEI, DL, VT, V1,
- DAG.getConstant(Imm, DL, MVT::i64));
+ DAG.getConstant(Imm, DL, Subtarget.getGRLenVT()));
}
return SDValue();
@@ -1479,9 +1482,10 @@ static SDValue lowerVECTOR_SHUFFLE_VREPLVEI(const SDLoc &DL, ArrayRef<int> Mask,
/// (VSHUF4I_H $v0, $v1, 27)
/// where the 27 comes from:
/// 3 + (2 << 2) + (1 << 4) + (0 << 6)
-static SDValue lowerVECTOR_SHUFFLE_VSHUF4I(const SDLoc &DL, ArrayRef<int> Mask,
- MVT VT, SDValue V1, SDValue V2,
- SelectionDAG &DAG) {
+static SDValue
+lowerVECTOR_SHUFFLE_VSHUF4I(const SDLoc &DL, ArrayRef<int> Mask, MVT VT,
+ SDValue V1, SDValue V2, SelectionDAG &DAG,
+ const LoongArchSubtarget &Subtarget) {
unsigned SubVecSize = 4;
if (VT == MVT::v2f64 || VT == MVT::v2i64)
@@ -1523,13 +1527,15 @@ static SDValue lowerVECTOR_SHUFFLE_VSHUF4I(const SDLoc &DL, ArrayRef<int> Mask,
Imm |= M & 0x3;
}
+ MVT GRLenVT = Subtarget.getGRLenVT();
+
// Return vshuf4i.d
if (VT == MVT::v2f64 || VT == MVT::v2i64)
return DAG.getNode(LoongArchISD::VSHUF4I, DL, VT, V1, V2,
- DAG.getConstant(Imm, DL, MVT::i64));
+ DAG.getConstant(Imm, DL, GRLenVT));
return DAG.getNode(LoongArchISD::VSHUF4I, DL, VT, V1,
- DAG.getConstant(Imm, DL, MVT::i64));
+ DAG.getConstant(Imm, DL, GRLenVT));
}
/// Lower VECTOR_SHUFFLE into VPACKEV (if possible).
@@ -1809,7 +1815,8 @@ static SDValue lowerVECTOR_SHUFFLE_VSHUF(const SDLoc &DL, ArrayRef<int> Mask,
/// This routine breaks down the specific type of 128-bit shuffle and
/// dispatches to the lowering routines accordingly.
static SDValue lower128BitShuffle(const SDLoc &DL, ArrayRef<int> Mask, MVT VT,
- SDValue V1, SDValue V2, SelectionDAG &DAG) {
+ SDValue V1, SDValue V2, SelectionDAG &DAG,
+ const LoongArchSubtarget &Subtarget) {
assert((VT.SimpleTy == MVT::v16i8 || VT.SimpleTy == MVT::v8i16 ||
VT.SimpleTy == MVT::v4i32 || VT.SimpleTy == MVT::v2i64 ||
VT.SimpleTy == MVT::v4f32 || VT.SimpleTy == MVT::v2f64) &&
@@ -1827,9 +1834,11 @@ static SDValue lower128BitShuffle(const SDLoc &DL, ArrayRef<int> Mask, MVT VT,
SDValue Result;
// TODO: Add more comparison patterns.
if (V2.isUndef()) {
- if ((Result = lowerVECTOR_SHUFFLE_VREPLVEI(DL, Mask, VT, V1, V2, DAG)))
+ if ((Result = lowerVECTOR_SHUFFLE_VREPLVEI(DL, Mask, VT, V1, V2, DAG,
+ Subtarget)))
return Result;
- if ((Result = lowerVECTOR_SHUFFLE_VSHUF4I(DL, Mask, VT, V1, V2, DAG)))
+ if ((Result =
+ lowerVECTOR_SHUFFLE_VSHUF4I(DL, Mask, VT, V1, V2, DAG, Subtarget)))
return Result;
// TODO: This comment may be enabled in the future to better match the
@@ -1852,15 +1861,17 @@ static SDValue lower128BitShuffle(const SDLoc &DL, ArrayRef<int> Mask, MVT VT,
if ((Result = lowerVECTOR_SHUFFLE_VPICKOD(DL, Mask, VT, V1, V2, DAG)))
return Result;
if ((VT.SimpleTy == MVT::v2i64 || VT.SimpleTy == MVT::v2f64) &&
- (Result = lowerVECTOR_SHUFFLE_VSHUF4I(DL, Mask, VT, V1, V2, DAG)))
+ (Result =
+ lowerVECTOR_SHUFFLE_VSHUF4I(DL, Mask, VT, V1, V2, DAG, Subtarget)))
return Result;
if ((Result = lowerVECTOR_SHUFFLEAsZeroOrAnyExtend(DL, Mask, VT, V1, V2, DAG,
Zeroable)))
return Result;
- if ((Result =
- lowerVECTOR_SHUFFLEAsShift(DL, Mask, VT, V1, V2, DAG, Zeroable)))
+ if ((Result = lowerVECTOR_SHUFFLEAsShift(DL, Mask, VT, V1, V2, DAG, Subtarget,
+ Zeroable)))
return Result;
- if ((Result = lowerVECTOR_SHUFFLEAsByteRotate(DL, Mask, VT, V1, V2, DAG)))
+ if ((Result = lowerVECTOR_SHUFFLEAsByteRotate(DL, Mask, VT, V1, V2, DAG,
+ Subtarget)))
return Result;
if (SDValue NewShuffle = widenShuffleMask(DL, Mask, VT, V1, V2, DAG))
return NewShuffle;
@@ -1877,10 +1888,10 @@ static SDValue lower128BitShuffle(const SDLoc &DL, ArrayRef<int> Mask, MVT VT,
///
/// When undef's appear in the mask they are treated as if they were whatever
/// value is necessary in order to fit the above form.
-static SDValue lowerVECTOR_SHUFFLE_XVREPLVEI(const SDLoc &DL,
- ArrayRef<int> Mask, MVT VT,
- SDValue V1, SDValue V2,
- SelectionDAG &DAG) {
+static SDValue
+lowerVECTOR_SHUFFLE_XVREPLVEI(const SDLoc &DL, ArrayRef<int> Mask, MVT VT,
+ SDValue V1, SDValue V2, SelectionDAG &DAG,
+ const LoongArchSubtarget &Subtarget) {
int SplatIndex = -1;
for (const auto &M : Mask) {
if (M != -1) {
@@ -1902,21 +1913,22 @@ static SDValue lowerVECTOR_SHUFFLE_XVREPLVEI(const SDLoc &DL,
0)) {
APInt Imm(64, SplatIndex);
return DAG.getNode(LoongArchISD::VREPLVEI, DL, VT, V1,
- DAG.getConstant(Imm, DL, MVT::i64));
+ DAG.getConstant(Imm, DL, Subtarget.getGRLenVT()));
}
return SDValue();
}
/// Lower VECTOR_SHUFFLE into XVSHUF4I (if possible).
-static SDValue lowerVECTOR_SHUFFLE_XVSHUF4I(const SDLoc &DL, ArrayRef<int> Mask,
- MVT VT, SDValue V1, SDValue V2,
- SelectionDAG &DAG) {
+static SDValue
+lowerVECTOR_SHUFFLE_XVSHUF4I(const SDLoc &DL, ArrayRef<int> Mask, MVT VT,
+ SDValue V1, SDValue V2, SelectionDAG &DAG,
+ const LoongArchSubtarget &Subtarget) {
// When the size is less than or equal to 4, lower cost instructions may be
// used.
if (Mask.size() <= 4)
return SDValue();
- return lowerVECTOR_SHUFFLE_VSHUF4I(DL, Mask, VT, V1, V2, DAG);
+ return lowerVECTOR_SHUFFLE_VSHUF4I(DL, Mask, VT, V1, V2, DAG, Subtarget);
}
/// Lower VECTOR_SHUFFLE into XVPACKEV (if possible).
@@ -2146,15 +2158,15 @@ static SDValue lowerVECTOR_SHUFFLE_XVSHUF(const SDLoc &DL, ArrayRef<int> Mask,
/// cases need to be converted to it for processing.
///
/// This function may modify V1, V2 and Mask
-static void canonicalizeShuffleVectorByLane(const SDLoc &DL,
- MutableArrayRef<int> Mask, MVT VT,
- SDValue &V1, SDValue &V2,
- SelectionDAG &DAG) {
+static void canonicalizeShuffleVectorByLane(
+ const SDLoc &DL, MutableArrayRef<int> Mask, MVT VT, SDValue &V1,
+ SDValue &V2, SelectionDAG &DAG, const LoongArchSubtarget &Subtarget) {
enum HalfMaskType { HighLaneTy, LowLaneTy, None };
int MaskSize = Mask.size();
int HalfSize = Mask.size() / 2;
+ MVT GRLenVT = Subtarget.getGRLenVT();
HalfMaskType preMask = None, postMask = None;
@@ -2192,13 +2204,13 @@ static void canonicalizeShuffleVectorByLane(const SDLoc &DL,
if (preMask == LowLaneTy && postMask == HighLaneTy) {
V1 = DAG.getBitcast(MVT::v4i64, V1);
V1 = DAG.getNode(LoongArchISD::XVPERMI, DL, MVT::v4i64, V1,
- DAG.getConstant(0b01001110, DL, MVT::i64));
+ DAG.getConstant(0b01001110, DL, GRLenVT));
V1 = DAG.getBitcast(VT, V1);
if (!V2.isUndef()) {
V2 = DAG.getBitcast(MVT::v4i64, V2);
V2 = DAG.getNode(LoongArchISD::XVPERMI, DL, MVT::v4i64, V2,
- DAG.getConstant(0b01001110, DL, MVT::i64));
+ DAG.getConstant(0b01001110, DL, GRLenVT));
V2 = DAG.getBitcast(VT, V2);
}
@@ -2211,13 +2223,13 @@ static void canonicalizeShuffleVectorByLane(const SDLoc &DL,
} else if (preMask == LowLaneTy && postMask == LowLaneTy) {
V1 = DAG.getBitcast(MVT::v4i64, V1);
V1 = DAG.getNode(LoongArchISD::XVPERMI, DL, MVT::v4i64, V1,
- DAG.getConstant(0b11101110, DL, MVT::i64));
+ DAG.getConstant(0b11101110, DL, GRLenVT));
V1 = DAG.getBitcast(VT, V1);
if (!V2.isUndef()) {
V2 = DAG.getBitcast(MVT::v4i64, V2);
V2 = DAG.getNode(LoongArchISD::XVPERMI, DL, MVT::v4i64, V2,
- DAG.getConstant(0b11101110, DL, MVT::i64));
+ DAG.getConstant(0b11101110, DL, GRLenVT));
V2 = DAG.getBitcast(VT, V2);
}
@@ -2227,13 +2239,13 @@ static void canonicalizeShuffleVectorByLane(const SDLoc &DL,
} else if (preMask == HighLaneTy && postMask == HighLaneTy) {
V1 = DAG.getBitcast(MVT::v4i64, V1);
V1 = DAG.getNode(LoongArchISD::XVPERMI, DL, MVT::v4i64, V1,
- DAG.getConstant(0b01000100, DL, MVT::i64));
+ DAG.getConstant(0b01000100, DL, GRLenVT));
V1 = DAG.getBitcast(VT, V1);
if (!V2.isUndef()) {
V2 = DAG.getBitcast(MVT::v4i64, V2);
V2 = DAG.getNode(LoongArchISD::XVPERMI, DL, MVT::v4i64, V2,
- DAG.getConstant(0b01000100, DL, MVT::i64));
+ DAG.getConstant(0b01000100, DL, GRLenVT));
V2 = DAG.getBitcast(VT, V2);
}
@@ -2295,7 +2307,8 @@ static SDValue lowerVECTOR_SHUFFLEAsLanePermuteAndShuffle(const SDLoc &DL,
/// This routine breaks down the specific type of 256-bit shuffle and
/// dispatches to the lowering routines accordingly.
static SDValue lower256BitShuffle(const SDLoc &DL, ArrayRef<int> Mask, MVT VT,
- SDValue V1, SDValue V2, SelectionDAG &DAG) {
+ SDValue V1, SDValue V2, SelectionDAG &DAG,
+ const LoongArchSubtarget &Subtarget) {
assert((VT.SimpleTy == MVT::v32i8 || VT.SimpleTy == MVT::v16i16 ||
VT.SimpleTy == MVT::v8i32 || VT.SimpleTy == MVT::v4i64 ||
VT.SimpleTy == MVT::v8f32 || VT.SimpleTy == MVT::v4f64) &&
@@ -2309,7 +2322,7 @@ static SDValue lower256BitShuffle(const SDLoc &DL, ArrayRef<int> Mask, MVT VT,
// canonicalize non cross-lane shuffle vector
SmallVector<int> NewMask(Mask);
- canonicalizeShuffleVectorByLane(DL, NewMask, VT, V1, V2, DAG);
+ canonicalizeShuffleVectorByLane(DL, NewMask, VT, V1, V2, DAG, Subtarget);
APInt KnownUndef, KnownZero;
computeZeroableShuffleElements(NewMask, V1, V2, KnownUndef, KnownZero);
@@ -2318,9 +2331,11 @@ static SDValue lower256BitShuffle(const SDLoc &DL, ArrayRef<int> Mask, MVT VT,
SDValue Result;
// TODO: Add more comparison patterns.
if (V2.isUndef()) {
- if ((Result = lowerVECTOR_SHUFFLE_XVREPLVEI(DL, NewMask, VT, V1, V2, DAG)))
+ if ((Result = lowerVECTOR_SHUFFLE_XVREPLVEI(DL, NewMask, VT, V1, V2, DAG,
+ Subtarget)))
return Result;
- if ((Result = lowerVECTOR_SHUFFLE_XVSHUF4I(DL, NewMask, VT, V1, V2, DAG)))
+ if ((Result = lowerVECTOR_SHUFFLE_XVSHUF4I(DL, NewMask, VT, V1, V2, DAG,
+ Subtarget)))
return Result;
if ((Result = lowerVECTOR_SHUFFLEAsLanePermuteAndShuffle(DL, NewMask, VT,
V1, V2, DAG)))
@@ -2345,10 +2360,11 @@ static SDValue lower256BitShuffle(const SDLoc &DL, ArrayRef<int> Mask, MVT VT,
return Result;
if ((Result = lowerVECTOR_SHUFFLE_XVPICKOD(DL, NewMask, VT, V1, V2, DAG)))
return Result;
- if ((Result =
- lowerVECTOR_SHUFFLEAsShift(DL, NewMask, VT, V1, V2, DAG, Zeroable)))
+ if ((Result = lowerVECTOR_SHUFFLEAsShift(DL, NewMask, VT, V1, V2, DAG,
+ Subtarget, Zeroable)))
return Result;
- if ((Result = lowerVECTOR_SHUFFLEAsByteRotate(DL, NewMask, VT, V1, V2, DAG)))
+ if ((Result = lowerVECTOR_SHUFFLEAsByteRotate(DL, NewMask, VT, V1, V2, DAG,
+ Subtarget)))
return Result;
if (SDValue NewShuffle = widenShuffleMask(DL, NewMask, VT, V1, V2, DAG))
return NewShuffle;
@@ -2400,10 +2416,10 @@ SDValue LoongArchTargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
// For each vector width, delegate to a specialized lowering routine.
if (VT.is128BitVector())
- return lower128BitShuffle(DL, OrigMask, VT, V1, V2, DAG);
+ return lower128BitShuffle(DL, OrigMask, VT, V1, V2, DAG, Subtarget);
if (VT.is256BitVector())
- return lower256BitShuffle(DL, OrigMask, VT, V1, V2, DAG);
+ return lower256BitShuffle(DL, OrigMask, VT, V1, V2, DAG, Subtarget);
return SDValue();
}
@@ -2547,6 +2563,16 @@ SDValue LoongArchTargetLowering::lowerBUILD_VECTOR(SDValue Op,
SplatBitSize != 64)
return SDValue();
+ if (SplatBitSize == 64 && !Subtarget.is64Bit()) {
+ // We can only handle 64-bit elements that are within
+ // the signed 32-bit range on 32-bit targets.
+ if (!SplatValue.isSignedIntN(32))
+ return SDValue();
+ if ((Is128Vec && ResTy == MVT::v4i32) ||
+ (Is256Vec && ResTy == MVT::v8i32))
+ return Op;
+ }
+
EVT ViaVecTy;
switch (SplatBitSize) {
diff --git a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
index 168a60004fc0f..eb7120ffb41a6 100644
--- a/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchLSXInstrInfo.td
@@ -22,7 +22,7 @@ def SDT_LoongArchVShuf : SDTypeProfile<1, 3, [SDTCisVec<0>,
def SDT_LoongArchV2R : SDTypeProfile<1, 2, [SDTCisVec<0>,
SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
def SDT_LoongArchV1RUimm: SDTypeProfile<1, 2, [SDTCisVec<0>,
- SDTCisSameAs<0,1>, SDTCisVT<2, i64>]>;
+ SDTCisSameAs<0,1>, SDTCisVT<2, GRLenVT>]>;
def SDT_LoongArchV2RUimm
: SDTypeProfile<1, 3,
[SDTCisVec<0>, SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
diff --git a/llvm/test/CodeGen/LoongArch/lasx/broadcast-load.ll b/llvm/test/CodeGen/LoongArch/lasx/broadcast-load.ll
index 976924bdca686..205e59a18bf9d 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/broadcast-load.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/broadcast-load.ll
@@ -1,16 +1,31 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc --mtriple=loongarch64 -mattr=+lasx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA32
+; RUN: llc --mtriple=loongarch64 -mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA64
-; TODO: Load a element and splat it to a vector could be lowerd to xvldrepl
-; A load has more than one user shouldn't be lowered to xvldrepl
define <4 x i64> @should_not_be_optimized(ptr %ptr, ptr %dst) {
-; CHECK-LABEL: should_not_be_optimized:
-; CHECK: # %bb.0:
-; CHECK-NEXT: ld.d $a0, $a0, 0
-; CHECK-NEXT: xvreplgr2vr.d $xr0, $a0
-; CHECK-NEXT: st.d $a0, $a1, 0
-; CHECK-NEXT: ret
+; LA32-LABEL: should_not_be_optimized:
+; LA32: # %bb.0:
+; LA32-NEXT: ld.w $a2, $a0, 0
+; LA32-NEXT: ld.w $a0, $a0, 4
+; LA32-NEXT: st.w $a2, $a1, 0
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a2, 0
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 1
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a2, 2
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 3
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a2, 4
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 5
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a2, 6
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 7
+; LA32-NEXT: st.w $a0, $a1, 4
+; LA32-NEXT: ret
+;
+; LA64-LABEL: should_not_be_optimized:
+; LA64: # %bb.0:
+; LA64-NEXT: ld.d $a0, $a0, 0
+; LA64-NEXT: xvreplgr2vr.d $xr0, $a0
+; LA64-NEXT: st.d $a0, $a1, 0
+; LA64-NEXT: ret
%tmp = load i64, ptr %ptr
store i64 %tmp, ptr %dst
%tmp1 = insertelement <4 x i64> zeroinitializer, i64 %tmp, i32 0
@@ -19,11 +34,25 @@ define <4 x i64> @should_not_be_optimized(ptr %ptr, ptr %dst) {
}
define <4 x i64> @xvldrepl_d_unaligned_offset(ptr %ptr) {
-; CHECK-LABEL: xvldrepl_d_unaligned_offset:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi.d $a0, $a0, 4
-; CHECK-NEXT: xvldrepl.d $xr0, $a0, 0
-; CHECK-NEXT: ret
+; LA32-LABEL: xvldrepl_d_unaligned_offset:
+; LA32: # %bb.0:
+; LA32-NEXT: ld.w $a1, $a0, 4
+; LA32-NEXT: ld.w $a0, $a0, 8
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 0
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 1
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 2
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 3
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 4
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 5
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 6
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 7
+; LA32-NEXT: ret
+;
+; LA64-LABEL: xvldrepl_d_unaligned_offset:
+; LA64: # %bb.0:
+; LA64-NEXT: addi.d $a0, $a0, 4
+; LA64-NEXT: xvldrepl.d $xr0, $a0, 0
+; LA64-NEXT: ret
%p = getelementptr i32, ptr %ptr, i32 1
%tmp = load i64, ptr %p
%tmp1 = insertelement <4 x i64> zeroinitializer, i64 %tmp, i32 0
@@ -103,10 +132,24 @@ define <8 x i32> @xvldrepl_w_offset(ptr %ptr) {
define <4 x i64> @xvldrepl_d(ptr %ptr) {
-; CHECK-LABEL: xvldrepl_d:
-; CHECK: # %bb.0:
-; CHECK-NEXT: xvldrepl.d $xr0, $a0, 0
-; CHECK-NEXT: ret
+; LA32-LABEL: xvldrepl_d:
+; LA32: # %bb.0:
+; LA32-NEXT: ld.w $a1, $a0, 0
+; LA32-NEXT: ld.w $a0, $a0, 4
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 0
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 1
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 2
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 3
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 4
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 5
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 6
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 7
+; LA32-NEXT: ret
+;
+; LA64-LABEL: xvldrepl_d:
+; LA64: # %bb.0:
+; LA64-NEXT: xvldrepl.d $xr0, $a0, 0
+; LA64-NEXT: ret
%tmp = load i64, ptr %ptr
%tmp1 = insertelement <4 x i64> zeroinitializer, i64 %tmp, i32 0
%tmp2 = shufflevector <4 x i64> %tmp1, <4 x i64> poison, <4 x i32> zeroinitializer
@@ -114,10 +157,24 @@ define <4 x i64> @xvldrepl_d(ptr %ptr) {
}
define <4 x i64> @xvldrepl_d_offset(ptr %ptr) {
-; CHECK-LABEL: xvldrepl_d_offset:
-; CHECK: # %bb.0:
-; CHECK-NEXT: xvldrepl.d $xr0, $a0, 264
-; CHECK-NEXT: ret
+; LA32-LABEL: xvldrepl_d_offset:
+; LA32: # %bb.0:
+; LA32-NEXT: ld.w $a1, $a0, 264
+; LA32-NEXT: ld.w $a0, $a0, 268
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 0
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 1
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 2
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 3
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 4
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 5
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 6
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 7
+; LA32-NEXT: ret
+;
+; LA64-LABEL: xvldrepl_d_offset:
+; LA64: # %bb.0:
+; LA64-NEXT: xvldrepl.d $xr0, $a0, 264
+; LA64-NEXT: ret
%p = getelementptr i64, ptr %ptr, i64 33
%tmp = load i64, ptr %p
%tmp1 = insertelement <4 x i64> zeroinitializer, i64 %tmp, i32 0
diff --git a/llvm/test/CodeGen/LoongArch/lasx/bswap.ll b/llvm/test/CodeGen/LoongArch/lasx/bswap.ll
index 1b0132d25ed59..a4c9abac7dcc6 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/bswap.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/bswap.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
define void @bswap_v16i16(ptr %src, ptr %dst) nounwind {
diff --git a/llvm/test/CodeGen/LoongArch/lasx/build-vector.ll b/llvm/test/CodeGen/LoongArch/lasx/build-vector.ll
index 44803e7078c45..23245726c8968 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/build-vector.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/build-vector.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
-; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA64
define void @buildvector_v32i8_splat(ptr %dst, i8 %a0) nounwind {
; CHECK-LABEL: buildvector_v32i8_splat:
@@ -41,11 +42,24 @@ entry:
}
define void @buildvector_v4i64_splat(ptr %dst, i64 %a0) nounwind {
-; CHECK-LABEL: buildvector_v4i64_splat:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xvreplgr2vr.d $xr0, $a1
-; CHECK-NEXT: xvst $xr0, $a0, 0
-; CHECK-NEXT: ret
+; LA32-LABEL: buildvector_v4i64_splat:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 0
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a2, 1
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 2
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a2, 3
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 4
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a2, 5
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 6
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a2, 7
+; LA32-NEXT: xvst $xr0, $a0, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: buildvector_v4i64_splat:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: xvreplgr2vr.d $xr0, $a1
+; LA64-NEXT: xvst $xr0, $a0, 0
+; LA64-NEXT: ret
entry:
%insert = insertelement <4 x i64> undef, i64 %a0, i8 0
%splat = shufflevector <4 x i64> %insert, <4 x i64> undef, <4 x i32> zeroinitializer
@@ -138,12 +152,19 @@ entry:
}
define void @buildvector_v4f64_const_splat(ptr %dst) nounwind {
-; CHECK-LABEL: buildvector_v4f64_const_splat:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lu52i.d $a1, $zero, 1023
-; CHECK-NEXT: xvreplgr2vr.d $xr0, $a1
-; CHECK-NEXT: xvst $xr0, $a0, 0
-; CHECK-NEXT: ret
+; LA32-LABEL: buildvector_v4f64_const_splat:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI11_0)
+; LA32-NEXT: xvld $xr0, $a1, %pc_lo12(.LCPI11_0)
+; LA32-NEXT: xvst $xr0, $a0, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: buildvector_v4f64_const_splat:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: lu52i.d $a1, $zero, 1023
+; LA64-NEXT: xvreplgr2vr.d $xr0, $a1
+; LA64-NEXT: xvst $xr0, $a0, 0
+; LA64-NEXT: ret
entry:
store <4 x double> <double 1.0, double 1.0, double 1.0, double 1.0>, ptr %dst
ret void
@@ -222,147 +243,289 @@ entry:
}
define void @buildvector_v32i8(ptr %dst, i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4, i8 %a5, i8 %a6, i8 %a7, i8 %a8, i8 %a9, i8 %a10, i8 %a11, i8 %a12, i8 %a13, i8 %a14, i8 %a15, i8 %a16, i8 %a17, i8 %a18, i8 %a19, i8 %a20, i8 %a21, i8 %a22, i8 %a23, i8 %a24, i8 %a25, i8 %a26, i8 %a27, i8 %a28, i8 %a29, i8 %a30, i8 %a31) nounwind {
-; CHECK-LABEL: buildvector_v32i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi.d $sp, $sp, -80
-; CHECK-NEXT: fst.d $fs0, $sp, 72 # 8-byte Folded Spill
-; CHECK-NEXT: fst.d $fs1, $sp, 64 # 8-byte Folded Spill
-; CHECK-NEXT: fst.d $fs2, $sp, 56 # 8-byte Folded Spill
-; CHECK-NEXT: fst.d $fs3, $sp, 48 # 8-byte Folded Spill
-; CHECK-NEXT: fst.d $fs4, $sp, 40 # 8-byte Folded Spill
-; CHECK-NEXT: fst.d $fs5, $sp, 32 # 8-byte Folded Spill
-; CHECK-NEXT: fst.d $fs6, $sp, 24 # 8-byte Folded Spill
-; CHECK-NEXT: fst.d $fs7, $sp, 16 # 8-byte Folded Spill
-; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 0
-; CHECK-NEXT: xvreplgr2vr.b $xr1, $a2
-; CHECK-NEXT: xvreplgr2vr.b $xr2, $a3
-; CHECK-NEXT: xvreplgr2vr.b $xr3, $a4
-; CHECK-NEXT: ld.b $a1, $sp, 264
-; CHECK-NEXT: xvreplgr2vr.b $xr4, $a5
-; CHECK-NEXT: ld.b $a2, $sp, 80
-; CHECK-NEXT: xvreplgr2vr.b $xr5, $a6
-; CHECK-NEXT: ld.b $a3, $sp, 88
-; CHECK-NEXT: xvreplgr2vr.b $xr6, $a7
-; CHECK-NEXT: ld.b $a4, $sp, 96
-; CHECK-NEXT: xvreplgr2vr.b $xr7, $a2
-; CHECK-NEXT: ld.b $a2, $sp, 104
-; CHECK-NEXT: xvreplgr2vr.b $xr8, $a3
-; CHECK-NEXT: ld.b $a3, $sp, 112
-; CHECK-NEXT: xvreplgr2vr.b $xr9, $a4
-; CHECK-NEXT: ld.b $a4, $sp, 120
-; CHECK-NEXT: xvreplgr2vr.b $xr10, $a2
-; CHECK-NEXT: ld.b $a2, $sp, 128
-; CHECK-NEXT: xvreplgr2vr.b $xr11, $a3
-; CHECK-NEXT: ld.b $a3, $sp, 136
-; CHECK-NEXT: xvreplgr2vr.b $xr12, $a4
-; CHECK-NEXT: ld.b $a4, $sp, 144
-; CHECK-NEXT: xvreplgr2vr.b $xr13, $a2
-; CHECK-NEXT: ld.b $a2, $sp, 152
-; CHECK-NEXT: xvreplgr2vr.b $xr14, $a3
-; CHECK-NEXT: ld.b $a3, $sp, 160
-; CHECK-NEXT: xvreplgr2vr.b $xr15, $a4
-; CHECK-NEXT: ld.b $a4, $sp, 168
-; CHECK-NEXT: xvreplgr2vr.b $xr16, $a2
-; CHECK-NEXT: ld.b $a2, $sp, 176
-; CHECK-NEXT: xvreplgr2vr.b $xr17, $a3
-; CHECK-NEXT: ld.b $a3, $sp, 184
-; CHECK-NEXT: xvreplgr2vr.b $xr18, $a4
-; CHECK-NEXT: ld.b $a4, $sp, 192
-; CHECK-NEXT: xvreplgr2vr.b $xr19, $a2
-; CHECK-NEXT: ld.b $a2, $sp, 200
-; CHECK-NEXT: xvreplgr2vr.b $xr20, $a3
-; CHECK-NEXT: ld.b $a3, $sp, 208
-; CHECK-NEXT: xvreplgr2vr.b $xr21, $a4
-; CHECK-NEXT: ld.b $a4, $sp, 216
-; CHECK-NEXT: xvreplgr2vr.b $xr22, $a2
-; CHECK-NEXT: ld.b $a2, $sp, 224
-; CHECK-NEXT: xvreplgr2vr.b $xr23, $a3
-; CHECK-NEXT: ld.b $a3, $sp, 232
-; CHECK-NEXT: xvreplgr2vr.b $xr24, $a4
-; CHECK-NEXT: ld.b $a4, $sp, 240
-; CHECK-NEXT: xvreplgr2vr.b $xr25, $a2
-; CHECK-NEXT: ld.b $a2, $sp, 248
-; CHECK-NEXT: xvreplgr2vr.b $xr26, $a3
-; CHECK-NEXT: ld.b $a3, $sp, 256
-; CHECK-NEXT: xvreplgr2vr.b $xr27, $a4
-; CHECK-NEXT: ld.b $a4, $sp, 272
-; CHECK-NEXT: xvreplgr2vr.b $xr28, $a2
-; CHECK-NEXT: xvreplgr2vr.b $xr29, $a3
-; CHECK-NEXT: xvreplgr2vr.b $xr30, $a1
-; CHECK-NEXT: xvreplgr2vr.b $xr31, $a4
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18
-; CHECK-NEXT: xvextrins.b $xr0, $xr1, 17
-; CHECK-NEXT: xvpermi.q $xr2, $xr0, 18
-; CHECK-NEXT: xvextrins.b $xr0, $xr2, 34
-; CHECK-NEXT: xvpermi.q $xr3, $xr0, 18
-; CHECK-NEXT: xvextrins.b $xr0, $xr3, 51
-; CHECK-NEXT: xvpermi.q $xr4, $xr0, 18
-; CHECK-NEXT: xvextrins.b $xr0, $xr4, 68
-; CHECK-NEXT: xvpermi.q $xr5, $xr0, 18
-; CHECK-NEXT: xvextrins.b $xr0, $xr5, 85
-; CHECK-NEXT: xvpermi.q $xr6, $xr0, 18
-; CHECK-NEXT: xvextrins.b $xr0, $xr6, 102
-; CHECK-NEXT: xvpermi.q $xr7, $xr0, 18
-; CHECK-NEXT: xvextrins.b $xr0, $xr7, 119
-; CHECK-NEXT: xvpermi.q $xr8, $xr0, 18
-; CHECK-NEXT: xvextrins.b $xr0, $xr8, 136
-; CHECK-NEXT: xvpermi.q $xr9, $xr0, 18
-; CHECK-NEXT: xvextrins.b $xr0, $xr9, 153
-; CHECK-NEXT: xvpermi.q $xr10, $xr0, 18
-; CHECK-NEXT: xvextrins.b $xr0, $xr10, 170
-; CHECK-NEXT: xvpermi.q $xr11, $xr0, 18
-; CHECK-NEXT: xvextrins.b $xr0, $xr11, 187
-; CHECK-NEXT: xvpermi.q $xr12, $xr0, 18
-; CHECK-NEXT: xvextrins.b $xr0, $xr12, 204
-; CHECK-NEXT: xvpermi.q $xr13, $xr0, 18
-; CHECK-NEXT: xvextrins.b $xr0, $xr13, 221
-; CHECK-NEXT: xvpermi.q $xr14, $xr0, 18
-; CHECK-NEXT: xvextrins.b $xr0, $xr14, 238
-; CHECK-NEXT: xvpermi.q $xr15, $xr0, 18
-; CHECK-NEXT: xvextrins.b $xr0, $xr15, 255
-; CHECK-NEXT: xvpermi.q $xr16, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr16, 0
-; CHECK-NEXT: xvpermi.q $xr17, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr17, 17
-; CHECK-NEXT: xvpermi.q $xr18, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr18, 34
-; CHECK-NEXT: xvpermi.q $xr19, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr19, 51
-; CHECK-NEXT: xvpermi.q $xr20, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr20, 68
-; CHECK-NEXT: xvpermi.q $xr21, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr21, 85
-; CHECK-NEXT: xvpermi.q $xr22, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr22, 102
-; CHECK-NEXT: xvpermi.q $xr23, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr23, 119
-; CHECK-NEXT: xvpermi.q $xr24, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr24, 136
-; CHECK-NEXT: xvpermi.q $xr25, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr25, 153
-; CHECK-NEXT: xvpermi.q $xr26, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr26, 170
-; CHECK-NEXT: xvpermi.q $xr27, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr27, 187
-; CHECK-NEXT: xvpermi.q $xr28, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr28, 204
-; CHECK-NEXT: xvpermi.q $xr29, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr29, 221
-; CHECK-NEXT: xvpermi.q $xr30, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr30, 238
-; CHECK-NEXT: xvpermi.q $xr31, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr31, 255
-; CHECK-NEXT: xvst $xr0, $a0, 0
-; CHECK-NEXT: fld.d $fs7, $sp, 16 # 8-byte Folded Reload
-; CHECK-NEXT: fld.d $fs6, $sp, 24 # 8-byte Folded Reload
-; CHECK-NEXT: fld.d $fs5, $sp, 32 # 8-byte Folded Reload
-; CHECK-NEXT: fld.d $fs4, $sp, 40 # 8-byte Folded Reload
-; CHECK-NEXT: fld.d $fs3, $sp, 48 # 8-byte Folded Reload
-; CHECK-NEXT: fld.d $fs2, $sp, 56 # 8-byte Folded Reload
-; CHECK-NEXT: fld.d $fs1, $sp, 64 # 8-byte Folded Reload
-; CHECK-NEXT: fld.d $fs0, $sp, 72 # 8-byte Folded Reload
-; CHECK-NEXT: addi.d $sp, $sp, 80
-; CHECK-NEXT: ret
+; LA32-LABEL: buildvector_v32i8:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: addi.w $sp, $sp, -80
+; LA32-NEXT: fst.d $fs0, $sp, 72 # 8-byte Folded Spill
+; LA32-NEXT: fst.d $fs1, $sp, 64 # 8-byte Folded Spill
+; LA32-NEXT: fst.d $fs2, $sp, 56 # 8-byte Folded Spill
+; LA32-NEXT: fst.d $fs3, $sp, 48 # 8-byte Folded Spill
+; LA32-NEXT: fst.d $fs4, $sp, 40 # 8-byte Folded Spill
+; LA32-NEXT: fst.d $fs5, $sp, 32 # 8-byte Folded Spill
+; LA32-NEXT: fst.d $fs6, $sp, 24 # 8-byte Folded Spill
+; LA32-NEXT: fst.d $fs7, $sp, 16 # 8-byte Folded Spill
+; LA32-NEXT: vinsgr2vr.b $vr0, $a1, 0
+; LA32-NEXT: xvreplgr2vr.b $xr1, $a2
+; LA32-NEXT: xvreplgr2vr.b $xr2, $a3
+; LA32-NEXT: xvreplgr2vr.b $xr3, $a4
+; LA32-NEXT: ld.b $a1, $sp, 172
+; LA32-NEXT: xvreplgr2vr.b $xr4, $a5
+; LA32-NEXT: ld.b $a2, $sp, 80
+; LA32-NEXT: xvreplgr2vr.b $xr5, $a6
+; LA32-NEXT: ld.b $a3, $sp, 84
+; LA32-NEXT: xvreplgr2vr.b $xr6, $a7
+; LA32-NEXT: ld.b $a4, $sp, 88
+; LA32-NEXT: xvreplgr2vr.b $xr7, $a2
+; LA32-NEXT: ld.b $a2, $sp, 92
+; LA32-NEXT: xvreplgr2vr.b $xr8, $a3
+; LA32-NEXT: ld.b $a3, $sp, 96
+; LA32-NEXT: xvreplgr2vr.b $xr9, $a4
+; LA32-NEXT: ld.b $a4, $sp, 100
+; LA32-NEXT: xvreplgr2vr.b $xr10, $a2
+; LA32-NEXT: ld.b $a2, $sp, 104
+; LA32-NEXT: xvreplgr2vr.b $xr11, $a3
+; LA32-NEXT: ld.b $a3, $sp, 108
+; LA32-NEXT: xvreplgr2vr.b $xr12, $a4
+; LA32-NEXT: ld.b $a4, $sp, 112
+; LA32-NEXT: xvreplgr2vr.b $xr13, $a2
+; LA32-NEXT: ld.b $a2, $sp, 116
+; LA32-NEXT: xvreplgr2vr.b $xr14, $a3
+; LA32-NEXT: ld.b $a3, $sp, 120
+; LA32-NEXT: xvreplgr2vr.b $xr15, $a4
+; LA32-NEXT: ld.b $a4, $sp, 124
+; LA32-NEXT: xvreplgr2vr.b $xr16, $a2
+; LA32-NEXT: ld.b $a2, $sp, 128
+; LA32-NEXT: xvreplgr2vr.b $xr17, $a3
+; LA32-NEXT: ld.b $a3, $sp, 132
+; LA32-NEXT: xvreplgr2vr.b $xr18, $a4
+; LA32-NEXT: ld.b $a4, $sp, 136
+; LA32-NEXT: xvreplgr2vr.b $xr19, $a2
+; LA32-NEXT: ld.b $a2, $sp, 140
+; LA32-NEXT: xvreplgr2vr.b $xr20, $a3
+; LA32-NEXT: ld.b $a3, $sp, 144
+; LA32-NEXT: xvreplgr2vr.b $xr21, $a4
+; LA32-NEXT: ld.b $a4, $sp, 148
+; LA32-NEXT: xvreplgr2vr.b $xr22, $a2
+; LA32-NEXT: ld.b $a2, $sp, 152
+; LA32-NEXT: xvreplgr2vr.b $xr23, $a3
+; LA32-NEXT: ld.b $a3, $sp, 156
+; LA32-NEXT: xvreplgr2vr.b $xr24, $a4
+; LA32-NEXT: ld.b $a4, $sp, 160
+; LA32-NEXT: xvreplgr2vr.b $xr25, $a2
+; LA32-NEXT: ld.b $a2, $sp, 164
+; LA32-NEXT: xvreplgr2vr.b $xr26, $a3
+; LA32-NEXT: ld.b $a3, $sp, 168
+; LA32-NEXT: xvreplgr2vr.b $xr27, $a4
+; LA32-NEXT: ld.b $a4, $sp, 176
+; LA32-NEXT: xvreplgr2vr.b $xr28, $a2
+; LA32-NEXT: xvreplgr2vr.b $xr29, $a3
+; LA32-NEXT: xvreplgr2vr.b $xr30, $a1
+; LA32-NEXT: xvreplgr2vr.b $xr31, $a4
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 18
+; LA32-NEXT: xvextrins.b $xr0, $xr1, 17
+; LA32-NEXT: xvpermi.q $xr2, $xr0, 18
+; LA32-NEXT: xvextrins.b $xr0, $xr2, 34
+; LA32-NEXT: xvpermi.q $xr3, $xr0, 18
+; LA32-NEXT: xvextrins.b $xr0, $xr3, 51
+; LA32-NEXT: xvpermi.q $xr4, $xr0, 18
+; LA32-NEXT: xvextrins.b $xr0, $xr4, 68
+; LA32-NEXT: xvpermi.q $xr5, $xr0, 18
+; LA32-NEXT: xvextrins.b $xr0, $xr5, 85
+; LA32-NEXT: xvpermi.q $xr6, $xr0, 18
+; LA32-NEXT: xvextrins.b $xr0, $xr6, 102
+; LA32-NEXT: xvpermi.q $xr7, $xr0, 18
+; LA32-NEXT: xvextrins.b $xr0, $xr7, 119
+; LA32-NEXT: xvpermi.q $xr8, $xr0, 18
+; LA32-NEXT: xvextrins.b $xr0, $xr8, 136
+; LA32-NEXT: xvpermi.q $xr9, $xr0, 18
+; LA32-NEXT: xvextrins.b $xr0, $xr9, 153
+; LA32-NEXT: xvpermi.q $xr10, $xr0, 18
+; LA32-NEXT: xvextrins.b $xr0, $xr10, 170
+; LA32-NEXT: xvpermi.q $xr11, $xr0, 18
+; LA32-NEXT: xvextrins.b $xr0, $xr11, 187
+; LA32-NEXT: xvpermi.q $xr12, $xr0, 18
+; LA32-NEXT: xvextrins.b $xr0, $xr12, 204
+; LA32-NEXT: xvpermi.q $xr13, $xr0, 18
+; LA32-NEXT: xvextrins.b $xr0, $xr13, 221
+; LA32-NEXT: xvpermi.q $xr14, $xr0, 18
+; LA32-NEXT: xvextrins.b $xr0, $xr14, 238
+; LA32-NEXT: xvpermi.q $xr15, $xr0, 18
+; LA32-NEXT: xvextrins.b $xr0, $xr15, 255
+; LA32-NEXT: xvpermi.q $xr16, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr16, 0
+; LA32-NEXT: xvpermi.q $xr17, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr17, 17
+; LA32-NEXT: xvpermi.q $xr18, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr18, 34
+; LA32-NEXT: xvpermi.q $xr19, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr19, 51
+; LA32-NEXT: xvpermi.q $xr20, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr20, 68
+; LA32-NEXT: xvpermi.q $xr21, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr21, 85
+; LA32-NEXT: xvpermi.q $xr22, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr22, 102
+; LA32-NEXT: xvpermi.q $xr23, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr23, 119
+; LA32-NEXT: xvpermi.q $xr24, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr24, 136
+; LA32-NEXT: xvpermi.q $xr25, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr25, 153
+; LA32-NEXT: xvpermi.q $xr26, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr26, 170
+; LA32-NEXT: xvpermi.q $xr27, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr27, 187
+; LA32-NEXT: xvpermi.q $xr28, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr28, 204
+; LA32-NEXT: xvpermi.q $xr29, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr29, 221
+; LA32-NEXT: xvpermi.q $xr30, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr30, 238
+; LA32-NEXT: xvpermi.q $xr31, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr31, 255
+; LA32-NEXT: xvst $xr0, $a0, 0
+; LA32-NEXT: fld.d $fs7, $sp, 16 # 8-byte Folded Reload
+; LA32-NEXT: fld.d $fs6, $sp, 24 # 8-byte Folded Reload
+; LA32-NEXT: fld.d $fs5, $sp, 32 # 8-byte Folded Reload
+; LA32-NEXT: fld.d $fs4, $sp, 40 # 8-byte Folded Reload
+; LA32-NEXT: fld.d $fs3, $sp, 48 # 8-byte Folded Reload
+; LA32-NEXT: fld.d $fs2, $sp, 56 # 8-byte Folded Reload
+; LA32-NEXT: fld.d $fs1, $sp, 64 # 8-byte Folded Reload
+; LA32-NEXT: fld.d $fs0, $sp, 72 # 8-byte Folded Reload
+; LA32-NEXT: addi.w $sp, $sp, 80
+; LA32-NEXT: ret
+;
+; LA64-LABEL: buildvector_v32i8:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: addi.d $sp, $sp, -80
+; LA64-NEXT: fst.d $fs0, $sp, 72 # 8-byte Folded Spill
+; LA64-NEXT: fst.d $fs1, $sp, 64 # 8-byte Folded Spill
+; LA64-NEXT: fst.d $fs2, $sp, 56 # 8-byte Folded Spill
+; LA64-NEXT: fst.d $fs3, $sp, 48 # 8-byte Folded Spill
+; LA64-NEXT: fst.d $fs4, $sp, 40 # 8-byte Folded Spill
+; LA64-NEXT: fst.d $fs5, $sp, 32 # 8-byte Folded Spill
+; LA64-NEXT: fst.d $fs6, $sp, 24 # 8-byte Folded Spill
+; LA64-NEXT: fst.d $fs7, $sp, 16 # 8-byte Folded Spill
+; LA64-NEXT: vinsgr2vr.b $vr0, $a1, 0
+; LA64-NEXT: xvreplgr2vr.b $xr1, $a2
+; LA64-NEXT: xvreplgr2vr.b $xr2, $a3
+; LA64-NEXT: xvreplgr2vr.b $xr3, $a4
+; LA64-NEXT: ld.b $a1, $sp, 264
+; LA64-NEXT: xvreplgr2vr.b $xr4, $a5
+; LA64-NEXT: ld.b $a2, $sp, 80
+; LA64-NEXT: xvreplgr2vr.b $xr5, $a6
+; LA64-NEXT: ld.b $a3, $sp, 88
+; LA64-NEXT: xvreplgr2vr.b $xr6, $a7
+; LA64-NEXT: ld.b $a4, $sp, 96
+; LA64-NEXT: xvreplgr2vr.b $xr7, $a2
+; LA64-NEXT: ld.b $a2, $sp, 104
+; LA64-NEXT: xvreplgr2vr.b $xr8, $a3
+; LA64-NEXT: ld.b $a3, $sp, 112
+; LA64-NEXT: xvreplgr2vr.b $xr9, $a4
+; LA64-NEXT: ld.b $a4, $sp, 120
+; LA64-NEXT: xvreplgr2vr.b $xr10, $a2
+; LA64-NEXT: ld.b $a2, $sp, 128
+; LA64-NEXT: xvreplgr2vr.b $xr11, $a3
+; LA64-NEXT: ld.b $a3, $sp, 136
+; LA64-NEXT: xvreplgr2vr.b $xr12, $a4
+; LA64-NEXT: ld.b $a4, $sp, 144
+; LA64-NEXT: xvreplgr2vr.b $xr13, $a2
+; LA64-NEXT: ld.b $a2, $sp, 152
+; LA64-NEXT: xvreplgr2vr.b $xr14, $a3
+; LA64-NEXT: ld.b $a3, $sp, 160
+; LA64-NEXT: xvreplgr2vr.b $xr15, $a4
+; LA64-NEXT: ld.b $a4, $sp, 168
+; LA64-NEXT: xvreplgr2vr.b $xr16, $a2
+; LA64-NEXT: ld.b $a2, $sp, 176
+; LA64-NEXT: xvreplgr2vr.b $xr17, $a3
+; LA64-NEXT: ld.b $a3, $sp, 184
+; LA64-NEXT: xvreplgr2vr.b $xr18, $a4
+; LA64-NEXT: ld.b $a4, $sp, 192
+; LA64-NEXT: xvreplgr2vr.b $xr19, $a2
+; LA64-NEXT: ld.b $a2, $sp, 200
+; LA64-NEXT: xvreplgr2vr.b $xr20, $a3
+; LA64-NEXT: ld.b $a3, $sp, 208
+; LA64-NEXT: xvreplgr2vr.b $xr21, $a4
+; LA64-NEXT: ld.b $a4, $sp, 216
+; LA64-NEXT: xvreplgr2vr.b $xr22, $a2
+; LA64-NEXT: ld.b $a2, $sp, 224
+; LA64-NEXT: xvreplgr2vr.b $xr23, $a3
+; LA64-NEXT: ld.b $a3, $sp, 232
+; LA64-NEXT: xvreplgr2vr.b $xr24, $a4
+; LA64-NEXT: ld.b $a4, $sp, 240
+; LA64-NEXT: xvreplgr2vr.b $xr25, $a2
+; LA64-NEXT: ld.b $a2, $sp, 248
+; LA64-NEXT: xvreplgr2vr.b $xr26, $a3
+; LA64-NEXT: ld.b $a3, $sp, 256
+; LA64-NEXT: xvreplgr2vr.b $xr27, $a4
+; LA64-NEXT: ld.b $a4, $sp, 272
+; LA64-NEXT: xvreplgr2vr.b $xr28, $a2
+; LA64-NEXT: xvreplgr2vr.b $xr29, $a3
+; LA64-NEXT: xvreplgr2vr.b $xr30, $a1
+; LA64-NEXT: xvreplgr2vr.b $xr31, $a4
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 18
+; LA64-NEXT: xvextrins.b $xr0, $xr1, 17
+; LA64-NEXT: xvpermi.q $xr2, $xr0, 18
+; LA64-NEXT: xvextrins.b $xr0, $xr2, 34
+; LA64-NEXT: xvpermi.q $xr3, $xr0, 18
+; LA64-NEXT: xvextrins.b $xr0, $xr3, 51
+; LA64-NEXT: xvpermi.q $xr4, $xr0, 18
+; LA64-NEXT: xvextrins.b $xr0, $xr4, 68
+; LA64-NEXT: xvpermi.q $xr5, $xr0, 18
+; LA64-NEXT: xvextrins.b $xr0, $xr5, 85
+; LA64-NEXT: xvpermi.q $xr6, $xr0, 18
+; LA64-NEXT: xvextrins.b $xr0, $xr6, 102
+; LA64-NEXT: xvpermi.q $xr7, $xr0, 18
+; LA64-NEXT: xvextrins.b $xr0, $xr7, 119
+; LA64-NEXT: xvpermi.q $xr8, $xr0, 18
+; LA64-NEXT: xvextrins.b $xr0, $xr8, 136
+; LA64-NEXT: xvpermi.q $xr9, $xr0, 18
+; LA64-NEXT: xvextrins.b $xr0, $xr9, 153
+; LA64-NEXT: xvpermi.q $xr10, $xr0, 18
+; LA64-NEXT: xvextrins.b $xr0, $xr10, 170
+; LA64-NEXT: xvpermi.q $xr11, $xr0, 18
+; LA64-NEXT: xvextrins.b $xr0, $xr11, 187
+; LA64-NEXT: xvpermi.q $xr12, $xr0, 18
+; LA64-NEXT: xvextrins.b $xr0, $xr12, 204
+; LA64-NEXT: xvpermi.q $xr13, $xr0, 18
+; LA64-NEXT: xvextrins.b $xr0, $xr13, 221
+; LA64-NEXT: xvpermi.q $xr14, $xr0, 18
+; LA64-NEXT: xvextrins.b $xr0, $xr14, 238
+; LA64-NEXT: xvpermi.q $xr15, $xr0, 18
+; LA64-NEXT: xvextrins.b $xr0, $xr15, 255
+; LA64-NEXT: xvpermi.q $xr16, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr16, 0
+; LA64-NEXT: xvpermi.q $xr17, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr17, 17
+; LA64-NEXT: xvpermi.q $xr18, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr18, 34
+; LA64-NEXT: xvpermi.q $xr19, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr19, 51
+; LA64-NEXT: xvpermi.q $xr20, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr20, 68
+; LA64-NEXT: xvpermi.q $xr21, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr21, 85
+; LA64-NEXT: xvpermi.q $xr22, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr22, 102
+; LA64-NEXT: xvpermi.q $xr23, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr23, 119
+; LA64-NEXT: xvpermi.q $xr24, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr24, 136
+; LA64-NEXT: xvpermi.q $xr25, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr25, 153
+; LA64-NEXT: xvpermi.q $xr26, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr26, 170
+; LA64-NEXT: xvpermi.q $xr27, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr27, 187
+; LA64-NEXT: xvpermi.q $xr28, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr28, 204
+; LA64-NEXT: xvpermi.q $xr29, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr29, 221
+; LA64-NEXT: xvpermi.q $xr30, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr30, 238
+; LA64-NEXT: xvpermi.q $xr31, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr31, 255
+; LA64-NEXT: xvst $xr0, $a0, 0
+; LA64-NEXT: fld.d $fs7, $sp, 16 # 8-byte Folded Reload
+; LA64-NEXT: fld.d $fs6, $sp, 24 # 8-byte Folded Reload
+; LA64-NEXT: fld.d $fs5, $sp, 32 # 8-byte Folded Reload
+; LA64-NEXT: fld.d $fs4, $sp, 40 # 8-byte Folded Reload
+; LA64-NEXT: fld.d $fs3, $sp, 48 # 8-byte Folded Reload
+; LA64-NEXT: fld.d $fs2, $sp, 56 # 8-byte Folded Reload
+; LA64-NEXT: fld.d $fs1, $sp, 64 # 8-byte Folded Reload
+; LA64-NEXT: fld.d $fs0, $sp, 72 # 8-byte Folded Reload
+; LA64-NEXT: addi.d $sp, $sp, 80
+; LA64-NEXT: ret
entry:
%ins0 = insertelement <32 x i8> undef, i8 %a0, i32 0
%ins1 = insertelement <32 x i8> %ins0, i8 %a1, i32 1
@@ -401,61 +564,117 @@ entry:
}
define void @buildvector_v32i8_partial(ptr %dst, i8 %a0, i8 %a1, i8 %a2, i8 %a5, i8 %a7, i8 %a8, i8 %a15, i8 %a17, i8 %a18, i8 %a20, i8 %a22, i8 %a23, i8 %a27, i8 %a28, i8 %a31) nounwind {
-; CHECK-LABEL: buildvector_v32i8_partial:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: ld.b $t0, $sp, 56
-; CHECK-NEXT: ld.b $t1, $sp, 48
-; CHECK-NEXT: ld.b $t2, $sp, 40
-; CHECK-NEXT: ld.b $t3, $sp, 32
-; CHECK-NEXT: ld.b $t4, $sp, 24
-; CHECK-NEXT: ld.b $t5, $sp, 16
-; CHECK-NEXT: ld.b $t6, $sp, 8
-; CHECK-NEXT: ld.b $t7, $sp, 0
-; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 0
-; CHECK-NEXT: xvreplgr2vr.b $xr1, $a2
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18
-; CHECK-NEXT: xvextrins.b $xr0, $xr1, 17
-; CHECK-NEXT: xvreplgr2vr.b $xr1, $a3
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18
-; CHECK-NEXT: xvextrins.b $xr0, $xr1, 34
-; CHECK-NEXT: xvreplgr2vr.b $xr1, $a4
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18
-; CHECK-NEXT: xvextrins.b $xr0, $xr1, 85
-; CHECK-NEXT: xvreplgr2vr.b $xr1, $a5
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18
-; CHECK-NEXT: xvextrins.b $xr0, $xr1, 119
-; CHECK-NEXT: xvreplgr2vr.b $xr1, $a6
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18
-; CHECK-NEXT: xvextrins.b $xr0, $xr1, 136
-; CHECK-NEXT: xvreplgr2vr.b $xr1, $a7
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18
-; CHECK-NEXT: xvextrins.b $xr0, $xr1, 255
-; CHECK-NEXT: xvreplgr2vr.b $xr1, $t7
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr1, 17
-; CHECK-NEXT: xvreplgr2vr.b $xr1, $t6
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr1, 34
-; CHECK-NEXT: xvreplgr2vr.b $xr1, $t5
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr1, 68
-; CHECK-NEXT: xvreplgr2vr.b $xr1, $t4
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr1, 102
-; CHECK-NEXT: xvreplgr2vr.b $xr1, $t3
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr1, 119
-; CHECK-NEXT: xvreplgr2vr.b $xr1, $t2
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr1, 187
-; CHECK-NEXT: xvreplgr2vr.b $xr1, $t1
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr1, 204
-; CHECK-NEXT: xvreplgr2vr.b $xr1, $t0
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr1, 255
-; CHECK-NEXT: xvst $xr0, $a0, 0
-; CHECK-NEXT: ret
+; LA32-LABEL: buildvector_v32i8_partial:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: ld.b $t0, $sp, 28
+; LA32-NEXT: ld.b $t1, $sp, 24
+; LA32-NEXT: ld.b $t2, $sp, 20
+; LA32-NEXT: ld.b $t3, $sp, 16
+; LA32-NEXT: ld.b $t4, $sp, 12
+; LA32-NEXT: ld.b $t5, $sp, 8
+; LA32-NEXT: ld.b $t6, $sp, 4
+; LA32-NEXT: ld.b $t7, $sp, 0
+; LA32-NEXT: vinsgr2vr.b $vr0, $a1, 0
+; LA32-NEXT: xvreplgr2vr.b $xr1, $a2
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 18
+; LA32-NEXT: xvextrins.b $xr0, $xr1, 17
+; LA32-NEXT: xvreplgr2vr.b $xr1, $a3
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 18
+; LA32-NEXT: xvextrins.b $xr0, $xr1, 34
+; LA32-NEXT: xvreplgr2vr.b $xr1, $a4
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 18
+; LA32-NEXT: xvextrins.b $xr0, $xr1, 85
+; LA32-NEXT: xvreplgr2vr.b $xr1, $a5
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 18
+; LA32-NEXT: xvextrins.b $xr0, $xr1, 119
+; LA32-NEXT: xvreplgr2vr.b $xr1, $a6
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 18
+; LA32-NEXT: xvextrins.b $xr0, $xr1, 136
+; LA32-NEXT: xvreplgr2vr.b $xr1, $a7
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 18
+; LA32-NEXT: xvextrins.b $xr0, $xr1, 255
+; LA32-NEXT: xvreplgr2vr.b $xr1, $t7
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr1, 17
+; LA32-NEXT: xvreplgr2vr.b $xr1, $t6
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr1, 34
+; LA32-NEXT: xvreplgr2vr.b $xr1, $t5
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr1, 68
+; LA32-NEXT: xvreplgr2vr.b $xr1, $t4
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr1, 102
+; LA32-NEXT: xvreplgr2vr.b $xr1, $t3
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr1, 119
+; LA32-NEXT: xvreplgr2vr.b $xr1, $t2
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr1, 187
+; LA32-NEXT: xvreplgr2vr.b $xr1, $t1
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr1, 204
+; LA32-NEXT: xvreplgr2vr.b $xr1, $t0
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr1, 255
+; LA32-NEXT: xvst $xr0, $a0, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: buildvector_v32i8_partial:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: ld.b $t0, $sp, 56
+; LA64-NEXT: ld.b $t1, $sp, 48
+; LA64-NEXT: ld.b $t2, $sp, 40
+; LA64-NEXT: ld.b $t3, $sp, 32
+; LA64-NEXT: ld.b $t4, $sp, 24
+; LA64-NEXT: ld.b $t5, $sp, 16
+; LA64-NEXT: ld.b $t6, $sp, 8
+; LA64-NEXT: ld.b $t7, $sp, 0
+; LA64-NEXT: vinsgr2vr.b $vr0, $a1, 0
+; LA64-NEXT: xvreplgr2vr.b $xr1, $a2
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 18
+; LA64-NEXT: xvextrins.b $xr0, $xr1, 17
+; LA64-NEXT: xvreplgr2vr.b $xr1, $a3
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 18
+; LA64-NEXT: xvextrins.b $xr0, $xr1, 34
+; LA64-NEXT: xvreplgr2vr.b $xr1, $a4
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 18
+; LA64-NEXT: xvextrins.b $xr0, $xr1, 85
+; LA64-NEXT: xvreplgr2vr.b $xr1, $a5
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 18
+; LA64-NEXT: xvextrins.b $xr0, $xr1, 119
+; LA64-NEXT: xvreplgr2vr.b $xr1, $a6
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 18
+; LA64-NEXT: xvextrins.b $xr0, $xr1, 136
+; LA64-NEXT: xvreplgr2vr.b $xr1, $a7
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 18
+; LA64-NEXT: xvextrins.b $xr0, $xr1, 255
+; LA64-NEXT: xvreplgr2vr.b $xr1, $t7
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr1, 17
+; LA64-NEXT: xvreplgr2vr.b $xr1, $t6
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr1, 34
+; LA64-NEXT: xvreplgr2vr.b $xr1, $t5
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr1, 68
+; LA64-NEXT: xvreplgr2vr.b $xr1, $t4
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr1, 102
+; LA64-NEXT: xvreplgr2vr.b $xr1, $t3
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr1, 119
+; LA64-NEXT: xvreplgr2vr.b $xr1, $t2
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr1, 187
+; LA64-NEXT: xvreplgr2vr.b $xr1, $t1
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr1, 204
+; LA64-NEXT: xvreplgr2vr.b $xr1, $t0
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr1, 255
+; LA64-NEXT: xvst $xr0, $a0, 0
+; LA64-NEXT: ret
entry:
%ins0 = insertelement <32 x i8> undef, i8 %a0, i32 0
%ins1 = insertelement <32 x i8> %ins0, i8 %a1, i32 1
@@ -494,64 +713,123 @@ entry:
}
define void @buildvector_v32i8_with_constant(ptr %dst, i8 %a0, i8 %a1, i8 %a2, i8 %a5, i8 %a8, i8 %a9, i8 %a15, i8 %a17, i8 %a18, i8 %a20, i8 %a22, i8 %a23, i8 %a27, i8 %a28, i8 %a31) nounwind {
-; CHECK-LABEL: buildvector_v32i8_with_constant:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: ld.b $t0, $sp, 56
-; CHECK-NEXT: ld.b $t1, $sp, 48
-; CHECK-NEXT: ld.b $t2, $sp, 40
-; CHECK-NEXT: ld.b $t3, $sp, 32
-; CHECK-NEXT: ld.b $t4, $sp, 24
-; CHECK-NEXT: ld.b $t5, $sp, 16
-; CHECK-NEXT: ld.b $t6, $sp, 8
-; CHECK-NEXT: ld.b $t7, $sp, 0
-; CHECK-NEXT: xvrepli.b $xr0, 0
-; CHECK-NEXT: xvreplgr2vr.b $xr1, $a1
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18
-; CHECK-NEXT: xvextrins.b $xr0, $xr1, 0
-; CHECK-NEXT: xvreplgr2vr.b $xr1, $a2
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18
-; CHECK-NEXT: xvextrins.b $xr0, $xr1, 17
-; CHECK-NEXT: xvreplgr2vr.b $xr1, $a3
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18
-; CHECK-NEXT: xvextrins.b $xr0, $xr1, 34
-; CHECK-NEXT: xvreplgr2vr.b $xr1, $a4
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18
-; CHECK-NEXT: xvextrins.b $xr0, $xr1, 85
-; CHECK-NEXT: xvreplgr2vr.b $xr1, $a5
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18
-; CHECK-NEXT: xvextrins.b $xr0, $xr1, 136
-; CHECK-NEXT: xvreplgr2vr.b $xr1, $a6
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18
-; CHECK-NEXT: xvextrins.b $xr0, $xr1, 153
-; CHECK-NEXT: xvreplgr2vr.b $xr1, $a7
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18
-; CHECK-NEXT: xvextrins.b $xr0, $xr1, 255
-; CHECK-NEXT: xvreplgr2vr.b $xr1, $t7
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr1, 17
-; CHECK-NEXT: xvreplgr2vr.b $xr1, $t6
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr1, 34
-; CHECK-NEXT: xvreplgr2vr.b $xr1, $t5
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr1, 68
-; CHECK-NEXT: xvreplgr2vr.b $xr1, $t4
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr1, 102
-; CHECK-NEXT: xvreplgr2vr.b $xr1, $t3
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr1, 119
-; CHECK-NEXT: xvreplgr2vr.b $xr1, $t2
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr1, 187
-; CHECK-NEXT: xvreplgr2vr.b $xr1, $t1
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr1, 204
-; CHECK-NEXT: xvreplgr2vr.b $xr1, $t0
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr1, 255
-; CHECK-NEXT: xvst $xr0, $a0, 0
-; CHECK-NEXT: ret
+; LA32-LABEL: buildvector_v32i8_with_constant:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: ld.b $t0, $sp, 28
+; LA32-NEXT: ld.b $t1, $sp, 24
+; LA32-NEXT: ld.b $t2, $sp, 20
+; LA32-NEXT: ld.b $t3, $sp, 16
+; LA32-NEXT: ld.b $t4, $sp, 12
+; LA32-NEXT: ld.b $t5, $sp, 8
+; LA32-NEXT: ld.b $t6, $sp, 4
+; LA32-NEXT: ld.b $t7, $sp, 0
+; LA32-NEXT: xvrepli.b $xr0, 0
+; LA32-NEXT: xvreplgr2vr.b $xr1, $a1
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 18
+; LA32-NEXT: xvextrins.b $xr0, $xr1, 0
+; LA32-NEXT: xvreplgr2vr.b $xr1, $a2
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 18
+; LA32-NEXT: xvextrins.b $xr0, $xr1, 17
+; LA32-NEXT: xvreplgr2vr.b $xr1, $a3
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 18
+; LA32-NEXT: xvextrins.b $xr0, $xr1, 34
+; LA32-NEXT: xvreplgr2vr.b $xr1, $a4
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 18
+; LA32-NEXT: xvextrins.b $xr0, $xr1, 85
+; LA32-NEXT: xvreplgr2vr.b $xr1, $a5
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 18
+; LA32-NEXT: xvextrins.b $xr0, $xr1, 136
+; LA32-NEXT: xvreplgr2vr.b $xr1, $a6
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 18
+; LA32-NEXT: xvextrins.b $xr0, $xr1, 153
+; LA32-NEXT: xvreplgr2vr.b $xr1, $a7
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 18
+; LA32-NEXT: xvextrins.b $xr0, $xr1, 255
+; LA32-NEXT: xvreplgr2vr.b $xr1, $t7
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr1, 17
+; LA32-NEXT: xvreplgr2vr.b $xr1, $t6
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr1, 34
+; LA32-NEXT: xvreplgr2vr.b $xr1, $t5
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr1, 68
+; LA32-NEXT: xvreplgr2vr.b $xr1, $t4
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr1, 102
+; LA32-NEXT: xvreplgr2vr.b $xr1, $t3
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr1, 119
+; LA32-NEXT: xvreplgr2vr.b $xr1, $t2
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr1, 187
+; LA32-NEXT: xvreplgr2vr.b $xr1, $t1
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr1, 204
+; LA32-NEXT: xvreplgr2vr.b $xr1, $t0
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr1, 255
+; LA32-NEXT: xvst $xr0, $a0, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: buildvector_v32i8_with_constant:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: ld.b $t0, $sp, 56
+; LA64-NEXT: ld.b $t1, $sp, 48
+; LA64-NEXT: ld.b $t2, $sp, 40
+; LA64-NEXT: ld.b $t3, $sp, 32
+; LA64-NEXT: ld.b $t4, $sp, 24
+; LA64-NEXT: ld.b $t5, $sp, 16
+; LA64-NEXT: ld.b $t6, $sp, 8
+; LA64-NEXT: ld.b $t7, $sp, 0
+; LA64-NEXT: xvrepli.b $xr0, 0
+; LA64-NEXT: xvreplgr2vr.b $xr1, $a1
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 18
+; LA64-NEXT: xvextrins.b $xr0, $xr1, 0
+; LA64-NEXT: xvreplgr2vr.b $xr1, $a2
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 18
+; LA64-NEXT: xvextrins.b $xr0, $xr1, 17
+; LA64-NEXT: xvreplgr2vr.b $xr1, $a3
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 18
+; LA64-NEXT: xvextrins.b $xr0, $xr1, 34
+; LA64-NEXT: xvreplgr2vr.b $xr1, $a4
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 18
+; LA64-NEXT: xvextrins.b $xr0, $xr1, 85
+; LA64-NEXT: xvreplgr2vr.b $xr1, $a5
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 18
+; LA64-NEXT: xvextrins.b $xr0, $xr1, 136
+; LA64-NEXT: xvreplgr2vr.b $xr1, $a6
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 18
+; LA64-NEXT: xvextrins.b $xr0, $xr1, 153
+; LA64-NEXT: xvreplgr2vr.b $xr1, $a7
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 18
+; LA64-NEXT: xvextrins.b $xr0, $xr1, 255
+; LA64-NEXT: xvreplgr2vr.b $xr1, $t7
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr1, 17
+; LA64-NEXT: xvreplgr2vr.b $xr1, $t6
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr1, 34
+; LA64-NEXT: xvreplgr2vr.b $xr1, $t5
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr1, 68
+; LA64-NEXT: xvreplgr2vr.b $xr1, $t4
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr1, 102
+; LA64-NEXT: xvreplgr2vr.b $xr1, $t3
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr1, 119
+; LA64-NEXT: xvreplgr2vr.b $xr1, $t2
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr1, 187
+; LA64-NEXT: xvreplgr2vr.b $xr1, $t1
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr1, 204
+; LA64-NEXT: xvreplgr2vr.b $xr1, $t0
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr1, 255
+; LA64-NEXT: xvst $xr0, $a0, 0
+; LA64-NEXT: ret
entry:
%ins0 = insertelement <32 x i8> undef, i8 %a0, i32 0
%ins1 = insertelement <32 x i8> %ins0, i8 %a1, i32 1
@@ -590,113 +868,221 @@ entry:
}
define void @buildvector_v32i8_subseq_2(ptr %dst, i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4, i8 %a5, i8 %a6, i8 %a7, i8 %a8, i8 %a9, i8 %a10, i8 %a11, i8 %a12, i8 %a13, i8 %a14, i8 %a15) nounwind {
-; CHECK-LABEL: buildvector_v32i8_subseq_2:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: ld.b $t0, $sp, 64
-; CHECK-NEXT: ld.b $t1, $sp, 56
-; CHECK-NEXT: ld.b $t2, $sp, 48
-; CHECK-NEXT: ld.b $t3, $sp, 40
-; CHECK-NEXT: ld.b $t4, $sp, 32
-; CHECK-NEXT: ld.b $t5, $sp, 24
-; CHECK-NEXT: ld.b $t6, $sp, 16
-; CHECK-NEXT: ld.b $t7, $sp, 8
-; CHECK-NEXT: ld.b $t8, $sp, 0
-; CHECK-NEXT: xvreplgr2vr.b $xr1, $a2
-; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 0
-; CHECK-NEXT: xvori.b $xr3, $xr1, 0
-; CHECK-NEXT: xvpermi.q $xr3, $xr0, 18
-; CHECK-NEXT: xvreplgr2vr.b $xr2, $a3
-; CHECK-NEXT: xvextrins.b $xr0, $xr3, 17
-; CHECK-NEXT: xvori.b $xr4, $xr2, 0
-; CHECK-NEXT: xvpermi.q $xr4, $xr0, 18
-; CHECK-NEXT: xvreplgr2vr.b $xr3, $a4
-; CHECK-NEXT: xvextrins.b $xr0, $xr4, 34
-; CHECK-NEXT: xvori.b $xr5, $xr3, 0
-; CHECK-NEXT: xvpermi.q $xr5, $xr0, 18
-; CHECK-NEXT: xvreplgr2vr.b $xr4, $a5
-; CHECK-NEXT: xvextrins.b $xr0, $xr5, 51
-; CHECK-NEXT: xvori.b $xr6, $xr4, 0
-; CHECK-NEXT: xvpermi.q $xr6, $xr0, 18
-; CHECK-NEXT: xvreplgr2vr.b $xr5, $a6
-; CHECK-NEXT: xvextrins.b $xr0, $xr6, 68
-; CHECK-NEXT: xvori.b $xr7, $xr5, 0
-; CHECK-NEXT: xvpermi.q $xr7, $xr0, 18
-; CHECK-NEXT: xvreplgr2vr.b $xr6, $a7
-; CHECK-NEXT: xvextrins.b $xr0, $xr7, 85
-; CHECK-NEXT: xvori.b $xr8, $xr6, 0
-; CHECK-NEXT: xvpermi.q $xr8, $xr0, 18
-; CHECK-NEXT: xvreplgr2vr.b $xr7, $t8
-; CHECK-NEXT: xvextrins.b $xr0, $xr8, 102
-; CHECK-NEXT: xvori.b $xr9, $xr7, 0
-; CHECK-NEXT: xvpermi.q $xr9, $xr0, 18
-; CHECK-NEXT: xvreplgr2vr.b $xr8, $t7
-; CHECK-NEXT: xvextrins.b $xr0, $xr9, 119
-; CHECK-NEXT: xvori.b $xr10, $xr8, 0
-; CHECK-NEXT: xvpermi.q $xr10, $xr0, 18
-; CHECK-NEXT: xvreplgr2vr.b $xr9, $t6
-; CHECK-NEXT: xvextrins.b $xr0, $xr10, 136
-; CHECK-NEXT: xvori.b $xr11, $xr9, 0
-; CHECK-NEXT: xvpermi.q $xr11, $xr0, 18
-; CHECK-NEXT: xvreplgr2vr.b $xr10, $t5
-; CHECK-NEXT: xvextrins.b $xr0, $xr11, 153
-; CHECK-NEXT: xvori.b $xr12, $xr10, 0
-; CHECK-NEXT: xvpermi.q $xr12, $xr0, 18
-; CHECK-NEXT: xvreplgr2vr.b $xr11, $t4
-; CHECK-NEXT: xvextrins.b $xr0, $xr12, 170
-; CHECK-NEXT: xvori.b $xr13, $xr11, 0
-; CHECK-NEXT: xvpermi.q $xr13, $xr0, 18
-; CHECK-NEXT: xvreplgr2vr.b $xr12, $t3
-; CHECK-NEXT: xvextrins.b $xr0, $xr13, 187
-; CHECK-NEXT: xvori.b $xr14, $xr12, 0
-; CHECK-NEXT: xvpermi.q $xr14, $xr0, 18
-; CHECK-NEXT: xvreplgr2vr.b $xr13, $t2
-; CHECK-NEXT: xvextrins.b $xr0, $xr14, 204
-; CHECK-NEXT: xvori.b $xr15, $xr13, 0
-; CHECK-NEXT: xvpermi.q $xr15, $xr0, 18
-; CHECK-NEXT: xvreplgr2vr.b $xr14, $t1
-; CHECK-NEXT: xvextrins.b $xr0, $xr15, 221
-; CHECK-NEXT: xvori.b $xr16, $xr14, 0
-; CHECK-NEXT: xvpermi.q $xr16, $xr0, 18
-; CHECK-NEXT: xvreplgr2vr.b $xr15, $t0
-; CHECK-NEXT: xvextrins.b $xr0, $xr16, 238
-; CHECK-NEXT: xvori.b $xr16, $xr15, 0
-; CHECK-NEXT: xvpermi.q $xr16, $xr0, 18
-; CHECK-NEXT: xvextrins.b $xr0, $xr16, 255
-; CHECK-NEXT: xvreplgr2vr.b $xr16, $a1
-; CHECK-NEXT: xvpermi.q $xr16, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr16, 0
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr1, 17
-; CHECK-NEXT: xvpermi.q $xr2, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr2, 34
-; CHECK-NEXT: xvpermi.q $xr3, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr3, 51
-; CHECK-NEXT: xvpermi.q $xr4, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr4, 68
-; CHECK-NEXT: xvpermi.q $xr5, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr5, 85
-; CHECK-NEXT: xvpermi.q $xr6, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr6, 102
-; CHECK-NEXT: xvpermi.q $xr7, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr7, 119
-; CHECK-NEXT: xvpermi.q $xr8, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr8, 136
-; CHECK-NEXT: xvpermi.q $xr9, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr9, 153
-; CHECK-NEXT: xvpermi.q $xr10, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr10, 170
-; CHECK-NEXT: xvpermi.q $xr11, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr11, 187
-; CHECK-NEXT: xvpermi.q $xr12, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr12, 204
-; CHECK-NEXT: xvpermi.q $xr13, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr13, 221
-; CHECK-NEXT: xvpermi.q $xr14, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr14, 238
-; CHECK-NEXT: xvpermi.q $xr15, $xr0, 48
-; CHECK-NEXT: xvextrins.b $xr0, $xr15, 255
-; CHECK-NEXT: xvst $xr0, $a0, 0
-; CHECK-NEXT: ret
+; LA32-LABEL: buildvector_v32i8_subseq_2:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: ld.b $t0, $sp, 32
+; LA32-NEXT: ld.b $t1, $sp, 28
+; LA32-NEXT: ld.b $t2, $sp, 24
+; LA32-NEXT: ld.b $t3, $sp, 20
+; LA32-NEXT: ld.b $t4, $sp, 16
+; LA32-NEXT: ld.b $t5, $sp, 12
+; LA32-NEXT: ld.b $t6, $sp, 8
+; LA32-NEXT: ld.b $t7, $sp, 4
+; LA32-NEXT: ld.b $t8, $sp, 0
+; LA32-NEXT: xvreplgr2vr.b $xr1, $a2
+; LA32-NEXT: vinsgr2vr.b $vr0, $a1, 0
+; LA32-NEXT: xvori.b $xr3, $xr1, 0
+; LA32-NEXT: xvpermi.q $xr3, $xr0, 18
+; LA32-NEXT: xvreplgr2vr.b $xr2, $a3
+; LA32-NEXT: xvextrins.b $xr0, $xr3, 17
+; LA32-NEXT: xvori.b $xr4, $xr2, 0
+; LA32-NEXT: xvpermi.q $xr4, $xr0, 18
+; LA32-NEXT: xvreplgr2vr.b $xr3, $a4
+; LA32-NEXT: xvextrins.b $xr0, $xr4, 34
+; LA32-NEXT: xvori.b $xr5, $xr3, 0
+; LA32-NEXT: xvpermi.q $xr5, $xr0, 18
+; LA32-NEXT: xvreplgr2vr.b $xr4, $a5
+; LA32-NEXT: xvextrins.b $xr0, $xr5, 51
+; LA32-NEXT: xvori.b $xr6, $xr4, 0
+; LA32-NEXT: xvpermi.q $xr6, $xr0, 18
+; LA32-NEXT: xvreplgr2vr.b $xr5, $a6
+; LA32-NEXT: xvextrins.b $xr0, $xr6, 68
+; LA32-NEXT: xvori.b $xr7, $xr5, 0
+; LA32-NEXT: xvpermi.q $xr7, $xr0, 18
+; LA32-NEXT: xvreplgr2vr.b $xr6, $a7
+; LA32-NEXT: xvextrins.b $xr0, $xr7, 85
+; LA32-NEXT: xvori.b $xr8, $xr6, 0
+; LA32-NEXT: xvpermi.q $xr8, $xr0, 18
+; LA32-NEXT: xvreplgr2vr.b $xr7, $t8
+; LA32-NEXT: xvextrins.b $xr0, $xr8, 102
+; LA32-NEXT: xvori.b $xr9, $xr7, 0
+; LA32-NEXT: xvpermi.q $xr9, $xr0, 18
+; LA32-NEXT: xvreplgr2vr.b $xr8, $t7
+; LA32-NEXT: xvextrins.b $xr0, $xr9, 119
+; LA32-NEXT: xvori.b $xr10, $xr8, 0
+; LA32-NEXT: xvpermi.q $xr10, $xr0, 18
+; LA32-NEXT: xvreplgr2vr.b $xr9, $t6
+; LA32-NEXT: xvextrins.b $xr0, $xr10, 136
+; LA32-NEXT: xvori.b $xr11, $xr9, 0
+; LA32-NEXT: xvpermi.q $xr11, $xr0, 18
+; LA32-NEXT: xvreplgr2vr.b $xr10, $t5
+; LA32-NEXT: xvextrins.b $xr0, $xr11, 153
+; LA32-NEXT: xvori.b $xr12, $xr10, 0
+; LA32-NEXT: xvpermi.q $xr12, $xr0, 18
+; LA32-NEXT: xvreplgr2vr.b $xr11, $t4
+; LA32-NEXT: xvextrins.b $xr0, $xr12, 170
+; LA32-NEXT: xvori.b $xr13, $xr11, 0
+; LA32-NEXT: xvpermi.q $xr13, $xr0, 18
+; LA32-NEXT: xvreplgr2vr.b $xr12, $t3
+; LA32-NEXT: xvextrins.b $xr0, $xr13, 187
+; LA32-NEXT: xvori.b $xr14, $xr12, 0
+; LA32-NEXT: xvpermi.q $xr14, $xr0, 18
+; LA32-NEXT: xvreplgr2vr.b $xr13, $t2
+; LA32-NEXT: xvextrins.b $xr0, $xr14, 204
+; LA32-NEXT: xvori.b $xr15, $xr13, 0
+; LA32-NEXT: xvpermi.q $xr15, $xr0, 18
+; LA32-NEXT: xvreplgr2vr.b $xr14, $t1
+; LA32-NEXT: xvextrins.b $xr0, $xr15, 221
+; LA32-NEXT: xvori.b $xr16, $xr14, 0
+; LA32-NEXT: xvpermi.q $xr16, $xr0, 18
+; LA32-NEXT: xvreplgr2vr.b $xr15, $t0
+; LA32-NEXT: xvextrins.b $xr0, $xr16, 238
+; LA32-NEXT: xvori.b $xr16, $xr15, 0
+; LA32-NEXT: xvpermi.q $xr16, $xr0, 18
+; LA32-NEXT: xvextrins.b $xr0, $xr16, 255
+; LA32-NEXT: xvreplgr2vr.b $xr16, $a1
+; LA32-NEXT: xvpermi.q $xr16, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr16, 0
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr1, 17
+; LA32-NEXT: xvpermi.q $xr2, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr2, 34
+; LA32-NEXT: xvpermi.q $xr3, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr3, 51
+; LA32-NEXT: xvpermi.q $xr4, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr4, 68
+; LA32-NEXT: xvpermi.q $xr5, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr5, 85
+; LA32-NEXT: xvpermi.q $xr6, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr6, 102
+; LA32-NEXT: xvpermi.q $xr7, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr7, 119
+; LA32-NEXT: xvpermi.q $xr8, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr8, 136
+; LA32-NEXT: xvpermi.q $xr9, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr9, 153
+; LA32-NEXT: xvpermi.q $xr10, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr10, 170
+; LA32-NEXT: xvpermi.q $xr11, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr11, 187
+; LA32-NEXT: xvpermi.q $xr12, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr12, 204
+; LA32-NEXT: xvpermi.q $xr13, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr13, 221
+; LA32-NEXT: xvpermi.q $xr14, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr14, 238
+; LA32-NEXT: xvpermi.q $xr15, $xr0, 48
+; LA32-NEXT: xvextrins.b $xr0, $xr15, 255
+; LA32-NEXT: xvst $xr0, $a0, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: buildvector_v32i8_subseq_2:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: ld.b $t0, $sp, 64
+; LA64-NEXT: ld.b $t1, $sp, 56
+; LA64-NEXT: ld.b $t2, $sp, 48
+; LA64-NEXT: ld.b $t3, $sp, 40
+; LA64-NEXT: ld.b $t4, $sp, 32
+; LA64-NEXT: ld.b $t5, $sp, 24
+; LA64-NEXT: ld.b $t6, $sp, 16
+; LA64-NEXT: ld.b $t7, $sp, 8
+; LA64-NEXT: ld.b $t8, $sp, 0
+; LA64-NEXT: xvreplgr2vr.b $xr1, $a2
+; LA64-NEXT: vinsgr2vr.b $vr0, $a1, 0
+; LA64-NEXT: xvori.b $xr3, $xr1, 0
+; LA64-NEXT: xvpermi.q $xr3, $xr0, 18
+; LA64-NEXT: xvreplgr2vr.b $xr2, $a3
+; LA64-NEXT: xvextrins.b $xr0, $xr3, 17
+; LA64-NEXT: xvori.b $xr4, $xr2, 0
+; LA64-NEXT: xvpermi.q $xr4, $xr0, 18
+; LA64-NEXT: xvreplgr2vr.b $xr3, $a4
+; LA64-NEXT: xvextrins.b $xr0, $xr4, 34
+; LA64-NEXT: xvori.b $xr5, $xr3, 0
+; LA64-NEXT: xvpermi.q $xr5, $xr0, 18
+; LA64-NEXT: xvreplgr2vr.b $xr4, $a5
+; LA64-NEXT: xvextrins.b $xr0, $xr5, 51
+; LA64-NEXT: xvori.b $xr6, $xr4, 0
+; LA64-NEXT: xvpermi.q $xr6, $xr0, 18
+; LA64-NEXT: xvreplgr2vr.b $xr5, $a6
+; LA64-NEXT: xvextrins.b $xr0, $xr6, 68
+; LA64-NEXT: xvori.b $xr7, $xr5, 0
+; LA64-NEXT: xvpermi.q $xr7, $xr0, 18
+; LA64-NEXT: xvreplgr2vr.b $xr6, $a7
+; LA64-NEXT: xvextrins.b $xr0, $xr7, 85
+; LA64-NEXT: xvori.b $xr8, $xr6, 0
+; LA64-NEXT: xvpermi.q $xr8, $xr0, 18
+; LA64-NEXT: xvreplgr2vr.b $xr7, $t8
+; LA64-NEXT: xvextrins.b $xr0, $xr8, 102
+; LA64-NEXT: xvori.b $xr9, $xr7, 0
+; LA64-NEXT: xvpermi.q $xr9, $xr0, 18
+; LA64-NEXT: xvreplgr2vr.b $xr8, $t7
+; LA64-NEXT: xvextrins.b $xr0, $xr9, 119
+; LA64-NEXT: xvori.b $xr10, $xr8, 0
+; LA64-NEXT: xvpermi.q $xr10, $xr0, 18
+; LA64-NEXT: xvreplgr2vr.b $xr9, $t6
+; LA64-NEXT: xvextrins.b $xr0, $xr10, 136
+; LA64-NEXT: xvori.b $xr11, $xr9, 0
+; LA64-NEXT: xvpermi.q $xr11, $xr0, 18
+; LA64-NEXT: xvreplgr2vr.b $xr10, $t5
+; LA64-NEXT: xvextrins.b $xr0, $xr11, 153
+; LA64-NEXT: xvori.b $xr12, $xr10, 0
+; LA64-NEXT: xvpermi.q $xr12, $xr0, 18
+; LA64-NEXT: xvreplgr2vr.b $xr11, $t4
+; LA64-NEXT: xvextrins.b $xr0, $xr12, 170
+; LA64-NEXT: xvori.b $xr13, $xr11, 0
+; LA64-NEXT: xvpermi.q $xr13, $xr0, 18
+; LA64-NEXT: xvreplgr2vr.b $xr12, $t3
+; LA64-NEXT: xvextrins.b $xr0, $xr13, 187
+; LA64-NEXT: xvori.b $xr14, $xr12, 0
+; LA64-NEXT: xvpermi.q $xr14, $xr0, 18
+; LA64-NEXT: xvreplgr2vr.b $xr13, $t2
+; LA64-NEXT: xvextrins.b $xr0, $xr14, 204
+; LA64-NEXT: xvori.b $xr15, $xr13, 0
+; LA64-NEXT: xvpermi.q $xr15, $xr0, 18
+; LA64-NEXT: xvreplgr2vr.b $xr14, $t1
+; LA64-NEXT: xvextrins.b $xr0, $xr15, 221
+; LA64-NEXT: xvori.b $xr16, $xr14, 0
+; LA64-NEXT: xvpermi.q $xr16, $xr0, 18
+; LA64-NEXT: xvreplgr2vr.b $xr15, $t0
+; LA64-NEXT: xvextrins.b $xr0, $xr16, 238
+; LA64-NEXT: xvori.b $xr16, $xr15, 0
+; LA64-NEXT: xvpermi.q $xr16, $xr0, 18
+; LA64-NEXT: xvextrins.b $xr0, $xr16, 255
+; LA64-NEXT: xvreplgr2vr.b $xr16, $a1
+; LA64-NEXT: xvpermi.q $xr16, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr16, 0
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr1, 17
+; LA64-NEXT: xvpermi.q $xr2, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr2, 34
+; LA64-NEXT: xvpermi.q $xr3, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr3, 51
+; LA64-NEXT: xvpermi.q $xr4, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr4, 68
+; LA64-NEXT: xvpermi.q $xr5, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr5, 85
+; LA64-NEXT: xvpermi.q $xr6, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr6, 102
+; LA64-NEXT: xvpermi.q $xr7, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr7, 119
+; LA64-NEXT: xvpermi.q $xr8, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr8, 136
+; LA64-NEXT: xvpermi.q $xr9, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr9, 153
+; LA64-NEXT: xvpermi.q $xr10, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr10, 170
+; LA64-NEXT: xvpermi.q $xr11, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr11, 187
+; LA64-NEXT: xvpermi.q $xr12, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr12, 204
+; LA64-NEXT: xvpermi.q $xr13, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr13, 221
+; LA64-NEXT: xvpermi.q $xr14, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr14, 238
+; LA64-NEXT: xvpermi.q $xr15, $xr0, 48
+; LA64-NEXT: xvextrins.b $xr0, $xr15, 255
+; LA64-NEXT: xvst $xr0, $a0, 0
+; LA64-NEXT: ret
entry:
%ins0 = insertelement <32 x i8> undef, i8 %a0, i32 0
%ins1 = insertelement <32 x i8> %ins0, i8 %a1, i32 1
@@ -1144,65 +1530,125 @@ entry:
}
define void @buildvector_v16i16(ptr %dst, i16 %a0, i16 %a1, i16 %a2, i16 %a3, i16 %a4, i16 %a5, i16 %a6, i16 %a7, i16 %a8, i16 %a9, i16 %a10, i16 %a11, i16 %a12, i16 %a13, i16 %a14, i16 %a15) nounwind {
-; CHECK-LABEL: buildvector_v16i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: ld.h $t0, $sp, 64
-; CHECK-NEXT: ld.h $t1, $sp, 56
-; CHECK-NEXT: ld.h $t2, $sp, 48
-; CHECK-NEXT: ld.h $t3, $sp, 40
-; CHECK-NEXT: ld.h $t4, $sp, 32
-; CHECK-NEXT: ld.h $t5, $sp, 24
-; CHECK-NEXT: ld.h $t6, $sp, 16
-; CHECK-NEXT: ld.h $t7, $sp, 8
-; CHECK-NEXT: ld.h $t8, $sp, 0
-; CHECK-NEXT: vinsgr2vr.h $vr0, $a1, 0
-; CHECK-NEXT: xvreplgr2vr.h $xr1, $a2
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18
-; CHECK-NEXT: xvextrins.h $xr0, $xr1, 17
-; CHECK-NEXT: xvreplgr2vr.h $xr1, $a3
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18
-; CHECK-NEXT: xvextrins.h $xr0, $xr1, 34
-; CHECK-NEXT: xvreplgr2vr.h $xr1, $a4
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18
-; CHECK-NEXT: xvextrins.h $xr0, $xr1, 51
-; CHECK-NEXT: xvreplgr2vr.h $xr1, $a5
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18
-; CHECK-NEXT: xvextrins.h $xr0, $xr1, 68
-; CHECK-NEXT: xvreplgr2vr.h $xr1, $a6
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18
-; CHECK-NEXT: xvextrins.h $xr0, $xr1, 85
-; CHECK-NEXT: xvreplgr2vr.h $xr1, $a7
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18
-; CHECK-NEXT: xvextrins.h $xr0, $xr1, 102
-; CHECK-NEXT: xvreplgr2vr.h $xr1, $t8
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 18
-; CHECK-NEXT: xvextrins.h $xr0, $xr1, 119
-; CHECK-NEXT: xvreplgr2vr.h $xr1, $t7
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48
-; CHECK-NEXT: xvextrins.h $xr0, $xr1, 0
-; CHECK-NEXT: xvreplgr2vr.h $xr1, $t6
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48
-; CHECK-NEXT: xvextrins.h $xr0, $xr1, 17
-; CHECK-NEXT: xvreplgr2vr.h $xr1, $t5
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48
-; CHECK-NEXT: xvextrins.h $xr0, $xr1, 34
-; CHECK-NEXT: xvreplgr2vr.h $xr1, $t4
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48
-; CHECK-NEXT: xvextrins.h $xr0, $xr1, 51
-; CHECK-NEXT: xvreplgr2vr.h $xr1, $t3
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48
-; CHECK-NEXT: xvextrins.h $xr0, $xr1, 68
-; CHECK-NEXT: xvreplgr2vr.h $xr1, $t2
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48
-; CHECK-NEXT: xvextrins.h $xr0, $xr1, 85
-; CHECK-NEXT: xvreplgr2vr.h $xr1, $t1
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48
-; CHECK-NEXT: xvextrins.h $xr0, $xr1, 102
-; CHECK-NEXT: xvreplgr2vr.h $xr1, $t0
-; CHECK-NEXT: xvpermi.q $xr1, $xr0, 48
-; CHECK-NEXT: xvextrins.h $xr0, $xr1, 119
-; CHECK-NEXT: xvst $xr0, $a0, 0
-; CHECK-NEXT: ret
+; LA32-LABEL: buildvector_v16i16:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: ld.h $t0, $sp, 32
+; LA32-NEXT: ld.h $t1, $sp, 28
+; LA32-NEXT: ld.h $t2, $sp, 24
+; LA32-NEXT: ld.h $t3, $sp, 20
+; LA32-NEXT: ld.h $t4, $sp, 16
+; LA32-NEXT: ld.h $t5, $sp, 12
+; LA32-NEXT: ld.h $t6, $sp, 8
+; LA32-NEXT: ld.h $t7, $sp, 4
+; LA32-NEXT: ld.h $t8, $sp, 0
+; LA32-NEXT: vinsgr2vr.h $vr0, $a1, 0
+; LA32-NEXT: xvreplgr2vr.h $xr1, $a2
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 18
+; LA32-NEXT: xvextrins.h $xr0, $xr1, 17
+; LA32-NEXT: xvreplgr2vr.h $xr1, $a3
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 18
+; LA32-NEXT: xvextrins.h $xr0, $xr1, 34
+; LA32-NEXT: xvreplgr2vr.h $xr1, $a4
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 18
+; LA32-NEXT: xvextrins.h $xr0, $xr1, 51
+; LA32-NEXT: xvreplgr2vr.h $xr1, $a5
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 18
+; LA32-NEXT: xvextrins.h $xr0, $xr1, 68
+; LA32-NEXT: xvreplgr2vr.h $xr1, $a6
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 18
+; LA32-NEXT: xvextrins.h $xr0, $xr1, 85
+; LA32-NEXT: xvreplgr2vr.h $xr1, $a7
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 18
+; LA32-NEXT: xvextrins.h $xr0, $xr1, 102
+; LA32-NEXT: xvreplgr2vr.h $xr1, $t8
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 18
+; LA32-NEXT: xvextrins.h $xr0, $xr1, 119
+; LA32-NEXT: xvreplgr2vr.h $xr1, $t7
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA32-NEXT: xvextrins.h $xr0, $xr1, 0
+; LA32-NEXT: xvreplgr2vr.h $xr1, $t6
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA32-NEXT: xvextrins.h $xr0, $xr1, 17
+; LA32-NEXT: xvreplgr2vr.h $xr1, $t5
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA32-NEXT: xvextrins.h $xr0, $xr1, 34
+; LA32-NEXT: xvreplgr2vr.h $xr1, $t4
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA32-NEXT: xvextrins.h $xr0, $xr1, 51
+; LA32-NEXT: xvreplgr2vr.h $xr1, $t3
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA32-NEXT: xvextrins.h $xr0, $xr1, 68
+; LA32-NEXT: xvreplgr2vr.h $xr1, $t2
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA32-NEXT: xvextrins.h $xr0, $xr1, 85
+; LA32-NEXT: xvreplgr2vr.h $xr1, $t1
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA32-NEXT: xvextrins.h $xr0, $xr1, 102
+; LA32-NEXT: xvreplgr2vr.h $xr1, $t0
+; LA32-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA32-NEXT: xvextrins.h $xr0, $xr1, 119
+; LA32-NEXT: xvst $xr0, $a0, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: buildvector_v16i16:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: ld.h $t0, $sp, 64
+; LA64-NEXT: ld.h $t1, $sp, 56
+; LA64-NEXT: ld.h $t2, $sp, 48
+; LA64-NEXT: ld.h $t3, $sp, 40
+; LA64-NEXT: ld.h $t4, $sp, 32
+; LA64-NEXT: ld.h $t5, $sp, 24
+; LA64-NEXT: ld.h $t6, $sp, 16
+; LA64-NEXT: ld.h $t7, $sp, 8
+; LA64-NEXT: ld.h $t8, $sp, 0
+; LA64-NEXT: vinsgr2vr.h $vr0, $a1, 0
+; LA64-NEXT: xvreplgr2vr.h $xr1, $a2
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 18
+; LA64-NEXT: xvextrins.h $xr0, $xr1, 17
+; LA64-NEXT: xvreplgr2vr.h $xr1, $a3
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 18
+; LA64-NEXT: xvextrins.h $xr0, $xr1, 34
+; LA64-NEXT: xvreplgr2vr.h $xr1, $a4
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 18
+; LA64-NEXT: xvextrins.h $xr0, $xr1, 51
+; LA64-NEXT: xvreplgr2vr.h $xr1, $a5
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 18
+; LA64-NEXT: xvextrins.h $xr0, $xr1, 68
+; LA64-NEXT: xvreplgr2vr.h $xr1, $a6
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 18
+; LA64-NEXT: xvextrins.h $xr0, $xr1, 85
+; LA64-NEXT: xvreplgr2vr.h $xr1, $a7
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 18
+; LA64-NEXT: xvextrins.h $xr0, $xr1, 102
+; LA64-NEXT: xvreplgr2vr.h $xr1, $t8
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 18
+; LA64-NEXT: xvextrins.h $xr0, $xr1, 119
+; LA64-NEXT: xvreplgr2vr.h $xr1, $t7
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA64-NEXT: xvextrins.h $xr0, $xr1, 0
+; LA64-NEXT: xvreplgr2vr.h $xr1, $t6
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA64-NEXT: xvextrins.h $xr0, $xr1, 17
+; LA64-NEXT: xvreplgr2vr.h $xr1, $t5
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA64-NEXT: xvextrins.h $xr0, $xr1, 34
+; LA64-NEXT: xvreplgr2vr.h $xr1, $t4
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA64-NEXT: xvextrins.h $xr0, $xr1, 51
+; LA64-NEXT: xvreplgr2vr.h $xr1, $t3
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA64-NEXT: xvextrins.h $xr0, $xr1, 68
+; LA64-NEXT: xvreplgr2vr.h $xr1, $t2
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA64-NEXT: xvextrins.h $xr0, $xr1, 85
+; LA64-NEXT: xvreplgr2vr.h $xr1, $t1
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA64-NEXT: xvextrins.h $xr0, $xr1, 102
+; LA64-NEXT: xvreplgr2vr.h $xr1, $t0
+; LA64-NEXT: xvpermi.q $xr1, $xr0, 48
+; LA64-NEXT: xvextrins.h $xr0, $xr1, 119
+; LA64-NEXT: xvst $xr0, $a0, 0
+; LA64-NEXT: ret
entry:
%ins0 = insertelement <16 x i16> undef, i16 %a0, i32 0
%ins1 = insertelement <16 x i16> %ins0, i16 %a1, i32 1
@@ -1659,14 +2105,28 @@ entry:
}
define void @buildvector_v4i64(ptr %dst, i64 %a0, i64 %a1, i64 %a2, i64 %a3) nounwind {
-; CHECK-LABEL: buildvector_v4i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xvinsgr2vr.d $xr0, $a1, 0
-; CHECK-NEXT: xvinsgr2vr.d $xr0, $a2, 1
-; CHECK-NEXT: xvinsgr2vr.d $xr0, $a3, 2
-; CHECK-NEXT: xvinsgr2vr.d $xr0, $a4, 3
-; CHECK-NEXT: xvst $xr0, $a0, 0
-; CHECK-NEXT: ret
+; LA32-LABEL: buildvector_v4i64:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: ld.w $t0, $sp, 0
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 0
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a2, 1
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a3, 2
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a4, 3
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a5, 4
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a6, 5
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a7, 6
+; LA32-NEXT: xvinsgr2vr.w $xr0, $t0, 7
+; LA32-NEXT: xvst $xr0, $a0, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: buildvector_v4i64:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: xvinsgr2vr.d $xr0, $a1, 0
+; LA64-NEXT: xvinsgr2vr.d $xr0, $a2, 1
+; LA64-NEXT: xvinsgr2vr.d $xr0, $a3, 2
+; LA64-NEXT: xvinsgr2vr.d $xr0, $a4, 3
+; LA64-NEXT: xvst $xr0, $a0, 0
+; LA64-NEXT: ret
entry:
%ins0 = insertelement <4 x i64> undef, i64 %a0, i32 0
%ins1 = insertelement <4 x i64> %ins0, i64 %a1, i32 1
@@ -1677,12 +2137,21 @@ entry:
}
define void @buildvector_v4i64_partial(ptr %dst, i64 %a1, i64 %a2) nounwind {
-; CHECK-LABEL: buildvector_v4i64_partial:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xvinsgr2vr.d $xr0, $a1, 1
-; CHECK-NEXT: xvinsgr2vr.d $xr0, $a2, 2
-; CHECK-NEXT: xvst $xr0, $a0, 0
-; CHECK-NEXT: ret
+; LA32-LABEL: buildvector_v4i64_partial:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 2
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a2, 3
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a3, 4
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a4, 5
+; LA32-NEXT: xvst $xr0, $a0, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: buildvector_v4i64_partial:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: xvinsgr2vr.d $xr0, $a1, 1
+; LA64-NEXT: xvinsgr2vr.d $xr0, $a2, 2
+; LA64-NEXT: xvst $xr0, $a0, 0
+; LA64-NEXT: ret
entry:
%ins0 = insertelement <4 x i64> undef, i64 undef, i32 0
%ins1 = insertelement <4 x i64> %ins0, i64 %a1, i32 1
@@ -1693,13 +2162,23 @@ entry:
}
define void @buildvector_v4i64_with_constant(ptr %dst, i64 %a0, i64 %a2) nounwind {
-; CHECK-LABEL: buildvector_v4i64_with_constant:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xvrepli.b $xr0, 0
-; CHECK-NEXT: xvinsgr2vr.d $xr0, $a1, 0
-; CHECK-NEXT: xvinsgr2vr.d $xr0, $a2, 2
-; CHECK-NEXT: xvst $xr0, $a0, 0
-; CHECK-NEXT: ret
+; LA32-LABEL: buildvector_v4i64_with_constant:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: xvrepli.b $xr0, 0
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 0
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a2, 1
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a3, 4
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a4, 5
+; LA32-NEXT: xvst $xr0, $a0, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: buildvector_v4i64_with_constant:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: xvrepli.b $xr0, 0
+; LA64-NEXT: xvinsgr2vr.d $xr0, $a1, 0
+; LA64-NEXT: xvinsgr2vr.d $xr0, $a2, 2
+; LA64-NEXT: xvst $xr0, $a0, 0
+; LA64-NEXT: ret
entry:
%ins0 = insertelement <4 x i64> undef, i64 %a0, i32 0
%ins1 = insertelement <4 x i64> %ins0, i64 0, i32 1
@@ -1710,14 +2189,27 @@ entry:
}
define void @buildvector_v4i64_subseq_2(ptr %dst, i64 %a0, i64 %a1) nounwind {
-; CHECK-LABEL: buildvector_v4i64_subseq_2:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xvinsgr2vr.d $xr0, $a1, 0
-; CHECK-NEXT: xvinsgr2vr.d $xr0, $a2, 1
-; CHECK-NEXT: xvinsgr2vr.d $xr0, $a1, 2
-; CHECK-NEXT: xvinsgr2vr.d $xr0, $a2, 3
-; CHECK-NEXT: xvst $xr0, $a0, 0
-; CHECK-NEXT: ret
+; LA32-LABEL: buildvector_v4i64_subseq_2:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 0
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a2, 1
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a3, 2
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a4, 3
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 4
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a2, 5
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a3, 6
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a4, 7
+; LA32-NEXT: xvst $xr0, $a0, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: buildvector_v4i64_subseq_2:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: xvinsgr2vr.d $xr0, $a1, 0
+; LA64-NEXT: xvinsgr2vr.d $xr0, $a2, 1
+; LA64-NEXT: xvinsgr2vr.d $xr0, $a1, 2
+; LA64-NEXT: xvinsgr2vr.d $xr0, $a2, 3
+; LA64-NEXT: xvst $xr0, $a0, 0
+; LA64-NEXT: ret
entry:
%ins0 = insertelement <4 x i64> undef, i64 %a0, i32 0
%ins1 = insertelement <4 x i64> %ins0, i64 %a1, i32 1
diff --git a/llvm/test/CodeGen/LoongArch/lasx/concat-vectors.ll b/llvm/test/CodeGen/LoongArch/lasx/concat-vectors.ll
index 231e82a6d53ac..d1868a949a076 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/concat-vectors.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/concat-vectors.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
define <32 x i8> @concat_poison_v32i8_1(<16 x i8> %a) {
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ctpop-ctlz.ll b/llvm/test/CodeGen/LoongArch/lasx/ctpop-ctlz.ll
index 7786e399c95f4..ba2118fb94f63 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/ctpop-ctlz.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/ctpop-ctlz.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
define void @ctpop_v32i8(ptr %src, ptr %dst) nounwind {
diff --git a/llvm/test/CodeGen/LoongArch/lasx/fdiv-reciprocal-estimate.ll b/llvm/test/CodeGen/LoongArch/lasx/fdiv-reciprocal-estimate.ll
index 769d9ef81faf3..7514dafa8000b 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/fdiv-reciprocal-estimate.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/fdiv-reciprocal-estimate.ll
@@ -1,25 +1,27 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; RUN: llc --mtriple=loongarch64 --mattr=+lasx,-frecipe < %s | FileCheck %s --check-prefix=FAULT
-; RUN: llc --mtriple=loongarch64 --mattr=+lasx,+frecipe < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx,-frecipe < %s | FileCheck %s --check-prefixes=FAULT,FAULT-LA32
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx,+frecipe < %s | FileCheck %s --check-prefixes=CHECK,LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx,-frecipe < %s | FileCheck %s --check-prefixes=FAULT,FAULT-LA64
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx,+frecipe < %s | FileCheck %s --check-prefixes=CHECK,LA64
define void @fdiv_v8f32(ptr %res, ptr %a0, ptr %a1) nounwind {
; FAULT-LABEL: fdiv_v8f32:
-; FAULT: # %bb.0:
-; FAULT-NEXT: xvld $xr0, $a1, 0
-; FAULT-NEXT: xvld $xr1, $a2, 0
-; FAULT-NEXT: xvfdiv.s $xr0, $xr0, $xr1
-; FAULT-NEXT: xvst $xr0, $a0, 0
+; FAULT: # %bb.0: # %entry
+; FAULT-NEXT: xvld $xr0, $a1, 0
+; FAULT-NEXT: xvld $xr1, $a2, 0
+; FAULT-NEXT: xvfdiv.s $xr0, $xr0, $xr1
+; FAULT-NEXT: xvst $xr0, $a0, 0
; FAULT-NEXT: ret
;
; CHECK-LABEL: fdiv_v8f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xvld $xr0, $a2, 0
-; CHECK-NEXT: xvld $xr1, $a1, 0
-; CHECK-NEXT: xvfrecipe.s $xr2, $xr0
-; CHECK-NEXT: xvfmul.s $xr3, $xr1, $xr2
-; CHECK-NEXT: xvfnmsub.s $xr0, $xr0, $xr3, $xr1
-; CHECK-NEXT: xvfmadd.s $xr0, $xr2, $xr0, $xr3
-; CHECK-NEXT: xvst $xr0, $a0, 0
+; CHECK-NEXT: xvld $xr0, $a2, 0
+; CHECK-NEXT: xvld $xr1, $a1, 0
+; CHECK-NEXT: xvfrecipe.s $xr2, $xr0
+; CHECK-NEXT: xvfmul.s $xr3, $xr1, $xr2
+; CHECK-NEXT: xvfnmsub.s $xr0, $xr0, $xr3, $xr1
+; CHECK-NEXT: xvfmadd.s $xr0, $xr2, $xr0, $xr3
+; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
entry:
%v0 = load <8 x float>, ptr %a0
@@ -31,27 +33,42 @@ entry:
define void @fdiv_v4f64(ptr %res, ptr %a0, ptr %a1) nounwind {
; FAULT-LABEL: fdiv_v4f64:
-; FAULT: # %bb.0:
-; FAULT-NEXT: xvld $xr0, $a1, 0
-; FAULT-NEXT: xvld $xr1, $a2, 0
-; FAULT-NEXT: xvfdiv.d $xr0, $xr0, $xr1
-; FAULT-NEXT: xvst $xr0, $a0, 0
+; FAULT: # %bb.0: # %entry
+; FAULT-NEXT: xvld $xr0, $a1, 0
+; FAULT-NEXT: xvld $xr1, $a2, 0
+; FAULT-NEXT: xvfdiv.d $xr0, $xr0, $xr1
+; FAULT-NEXT: xvst $xr0, $a0, 0
; FAULT-NEXT: ret
;
-; CHECK-LABEL: fdiv_v4f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xvld $xr0, $a2, 0
-; CHECK-NEXT: xvld $xr1, $a1, 0
-; CHECK-NEXT: lu52i.d $a1, $zero, -1025
-; CHECK-NEXT: xvreplgr2vr.d $xr2, $a1
-; CHECK-NEXT: xvfrecipe.d $xr3, $xr0
-; CHECK-NEXT: xvfmadd.d $xr2, $xr0, $xr3, $xr2
-; CHECK-NEXT: xvfnmsub.d $xr2, $xr2, $xr3, $xr3
-; CHECK-NEXT: xvfmul.d $xr3, $xr1, $xr2
-; CHECK-NEXT: xvfnmsub.d $xr0, $xr0, $xr3, $xr1
-; CHECK-NEXT: xvfmadd.d $xr0, $xr2, $xr0, $xr3
-; CHECK-NEXT: xvst $xr0, $a0, 0
-; CHECK-NEXT: ret
+; LA32-LABEL: fdiv_v4f64:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: pcalau12i $a3, %pc_hi20(.LCPI1_0)
+; LA32-NEXT: xvld $xr0, $a2, 0
+; LA32-NEXT: xvld $xr1, $a3, %pc_lo12(.LCPI1_0)
+; LA32-NEXT: xvld $xr2, $a1, 0
+; LA32-NEXT: xvfrecipe.d $xr3, $xr0
+; LA32-NEXT: xvfmadd.d $xr1, $xr0, $xr3, $xr1
+; LA32-NEXT: xvfnmsub.d $xr1, $xr1, $xr3, $xr3
+; LA32-NEXT: xvfmul.d $xr3, $xr2, $xr1
+; LA32-NEXT: xvfnmsub.d $xr0, $xr0, $xr3, $xr2
+; LA32-NEXT: xvfmadd.d $xr0, $xr1, $xr0, $xr3
+; LA32-NEXT: xvst $xr0, $a0, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: fdiv_v4f64:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: xvld $xr0, $a2, 0
+; LA64-NEXT: xvld $xr1, $a1, 0
+; LA64-NEXT: lu52i.d $a1, $zero, -1025
+; LA64-NEXT: xvreplgr2vr.d $xr2, $a1
+; LA64-NEXT: xvfrecipe.d $xr3, $xr0
+; LA64-NEXT: xvfmadd.d $xr2, $xr0, $xr3, $xr2
+; LA64-NEXT: xvfnmsub.d $xr2, $xr2, $xr3, $xr3
+; LA64-NEXT: xvfmul.d $xr3, $xr1, $xr2
+; LA64-NEXT: xvfnmsub.d $xr0, $xr0, $xr3, $xr1
+; LA64-NEXT: xvfmadd.d $xr0, $xr2, $xr0, $xr3
+; LA64-NEXT: xvst $xr0, $a0, 0
+; LA64-NEXT: ret
entry:
%v0 = load <4 x double>, ptr %a0
%v1 = load <4 x double>, ptr %a1
@@ -63,21 +80,21 @@ entry:
;; 1.0 / vec
define void @one_fdiv_v8f32(ptr %res, ptr %a0) nounwind {
; FAULT-LABEL: one_fdiv_v8f32:
-; FAULT: # %bb.0:
-; FAULT-NEXT: xvld $xr0, $a1, 0
-; FAULT-NEXT: xvfrecip.s $xr0, $xr0
-; FAULT-NEXT: xvst $xr0, $a0, 0
+; FAULT: # %bb.0: # %entry
+; FAULT-NEXT: xvld $xr0, $a1, 0
+; FAULT-NEXT: xvfrecip.s $xr0, $xr0
+; FAULT-NEXT: xvst $xr0, $a0, 0
; FAULT-NEXT: ret
;
; CHECK-LABEL: one_fdiv_v8f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xvld $xr0, $a1, 0
-; CHECK-NEXT: xvfrecipe.s $xr1, $xr0
-; CHECK-NEXT: lu12i.w $a1, -264192
-; CHECK-NEXT: xvreplgr2vr.w $xr2, $a1
-; CHECK-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2
-; CHECK-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr1
-; CHECK-NEXT: xvst $xr0, $a0, 0
+; CHECK-NEXT: xvld $xr0, $a1, 0
+; CHECK-NEXT: xvfrecipe.s $xr1, $xr0
+; CHECK-NEXT: lu12i.w $a1, -264192
+; CHECK-NEXT: xvreplgr2vr.w $xr2, $a1
+; CHECK-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2
+; CHECK-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr1
+; CHECK-NEXT: xvst $xr0, $a0, 0
; CHECK-NEXT: ret
entry:
%v0 = load <8 x float>, ptr %a0
@@ -87,25 +104,47 @@ entry:
}
define void @one_fdiv_v4f64(ptr %res, ptr %a0) nounwind {
-; FAULT-LABEL: one_fdiv_v4f64:
-; FAULT: # %bb.0:
-; FAULT-NEXT: xvld $xr0, $a1, 0
-; FAULT-NEXT: xvfrecip.d $xr0, $xr0
-; FAULT-NEXT: xvst $xr0, $a0, 0
-; FAULT-NEXT: ret
+; FAULT-LA32-LABEL: one_fdiv_v4f64:
+; FAULT-LA32: # %bb.0: # %entry
+; FAULT-LA32-NEXT: xvld $xr0, $a1, 0
+; FAULT-LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI3_0)
+; FAULT-LA32-NEXT: xvld $xr1, $a1, %pc_lo12(.LCPI3_0)
+; FAULT-LA32-NEXT: xvfdiv.d $xr0, $xr1, $xr0
+; FAULT-LA32-NEXT: xvst $xr0, $a0, 0
+; FAULT-LA32-NEXT: ret
;
-; CHECK-LABEL: one_fdiv_v4f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xvld $xr0, $a1, 0
-; CHECK-NEXT: xvfrecipe.d $xr1, $xr0
-; CHECK-NEXT: lu52i.d $a1, $zero, 1023
-; CHECK-NEXT: xvreplgr2vr.d $xr2, $a1
-; CHECK-NEXT: xvfnmsub.d $xr3, $xr0, $xr1, $xr2
-; CHECK-NEXT: xvfmadd.d $xr1, $xr1, $xr3, $xr1
-; CHECK-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2
-; CHECK-NEXT: xvfmadd.d $xr0, $xr1, $xr0, $xr1
-; CHECK-NEXT: xvst $xr0, $a0, 0
-; CHECK-NEXT: ret
+; LA32-LABEL: one_fdiv_v4f64:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: xvld $xr0, $a1, 0
+; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI3_0)
+; LA32-NEXT: xvld $xr1, $a1, %pc_lo12(.LCPI3_0)
+; LA32-NEXT: xvfrecipe.d $xr2, $xr0
+; LA32-NEXT: xvfnmsub.d $xr3, $xr0, $xr2, $xr1
+; LA32-NEXT: xvfmadd.d $xr2, $xr2, $xr3, $xr2
+; LA32-NEXT: xvfnmsub.d $xr0, $xr0, $xr2, $xr1
+; LA32-NEXT: xvfmadd.d $xr0, $xr2, $xr0, $xr2
+; LA32-NEXT: xvst $xr0, $a0, 0
+; LA32-NEXT: ret
+;
+; FAULT-LA64-LABEL: one_fdiv_v4f64:
+; FAULT-LA64: # %bb.0: # %entry
+; FAULT-LA64-NEXT: xvld $xr0, $a1, 0
+; FAULT-LA64-NEXT: xvfrecip.d $xr0, $xr0
+; FAULT-LA64-NEXT: xvst $xr0, $a0, 0
+; FAULT-LA64-NEXT: ret
+;
+; LA64-LABEL: one_fdiv_v4f64:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: xvld $xr0, $a1, 0
+; LA64-NEXT: xvfrecipe.d $xr1, $xr0
+; LA64-NEXT: lu52i.d $a1, $zero, 1023
+; LA64-NEXT: xvreplgr2vr.d $xr2, $a1
+; LA64-NEXT: xvfnmsub.d $xr3, $xr0, $xr1, $xr2
+; LA64-NEXT: xvfmadd.d $xr1, $xr1, $xr3, $xr1
+; LA64-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2
+; LA64-NEXT: xvfmadd.d $xr0, $xr1, $xr0, $xr1
+; LA64-NEXT: xvst $xr0, $a0, 0
+; LA64-NEXT: ret
entry:
%v0 = load <4 x double>, ptr %a0
%div = fdiv fast <4 x double> <double 1.0, double 1.0, double 1.0, double 1.0>, %v0
diff --git a/llvm/test/CodeGen/LoongArch/lasx/fma-v4f64.ll b/llvm/test/CodeGen/LoongArch/lasx/fma-v4f64.ll
index 0f3df3d573b65..8e1ba7ea16016 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/fma-v4f64.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/fma-v4f64.ll
@@ -1,40 +1,75 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx --fp-contract=fast < %s \
+; RUN: | FileCheck %s --check-prefix=LA32-CONTRACT-FAST
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx --fp-contract=on < %s \
+; RUN: | FileCheck %s --check-prefix=LA32-CONTRACT-ON
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx --fp-contract=off < %s \
+; RUN: | FileCheck %s --check-prefix=LA32-CONTRACT-OFF
; RUN: llc --mtriple=loongarch64 --mattr=+lasx --fp-contract=fast < %s \
-; RUN: | FileCheck %s --check-prefix=CONTRACT-FAST
+; RUN: | FileCheck %s --check-prefix=LA64-CONTRACT-FAST
; RUN: llc --mtriple=loongarch64 --mattr=+lasx --fp-contract=on < %s \
-; RUN: | FileCheck %s --check-prefix=CONTRACT-ON
+; RUN: | FileCheck %s --check-prefix=LA64-CONTRACT-ON
; RUN: llc --mtriple=loongarch64 --mattr=+lasx --fp-contract=off < %s \
-; RUN: | FileCheck %s --check-prefix=CONTRACT-OFF
+; RUN: | FileCheck %s --check-prefix=LA64-CONTRACT-OFF
define void @xvfmadd_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
-; CONTRACT-FAST-LABEL: xvfmadd_d:
-; CONTRACT-FAST: # %bb.0: # %entry
-; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-FAST-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2
-; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-FAST-NEXT: ret
-;
-; CONTRACT-ON-LABEL: xvfmadd_d:
-; CONTRACT-ON: # %bb.0: # %entry
-; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1
-; CONTRACT-ON-NEXT: xvfadd.d $xr0, $xr0, $xr2
-; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-ON-NEXT: ret
-;
-; CONTRACT-OFF-LABEL: xvfmadd_d:
-; CONTRACT-OFF: # %bb.0: # %entry
-; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1
-; CONTRACT-OFF-NEXT: xvfadd.d $xr0, $xr0, $xr2
-; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-OFF-NEXT: ret
+; LA32-CONTRACT-FAST-LABEL: xvfmadd_d:
+; LA32-CONTRACT-FAST: # %bb.0: # %entry
+; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-FAST-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-FAST-NEXT: ret
+;
+; LA32-CONTRACT-ON-LABEL: xvfmadd_d:
+; LA32-CONTRACT-ON: # %bb.0: # %entry
+; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1
+; LA32-CONTRACT-ON-NEXT: xvfadd.d $xr0, $xr0, $xr2
+; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-ON-NEXT: ret
+;
+; LA32-CONTRACT-OFF-LABEL: xvfmadd_d:
+; LA32-CONTRACT-OFF: # %bb.0: # %entry
+; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1
+; LA32-CONTRACT-OFF-NEXT: xvfadd.d $xr0, $xr0, $xr2
+; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-OFF-NEXT: ret
+;
+; LA64-CONTRACT-FAST-LABEL: xvfmadd_d:
+; LA64-CONTRACT-FAST: # %bb.0: # %entry
+; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-FAST-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-FAST-NEXT: ret
+;
+; LA64-CONTRACT-ON-LABEL: xvfmadd_d:
+; LA64-CONTRACT-ON: # %bb.0: # %entry
+; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1
+; LA64-CONTRACT-ON-NEXT: xvfadd.d $xr0, $xr0, $xr2
+; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-ON-NEXT: ret
+;
+; LA64-CONTRACT-OFF-LABEL: xvfmadd_d:
+; LA64-CONTRACT-OFF: # %bb.0: # %entry
+; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1
+; LA64-CONTRACT-OFF-NEXT: xvfadd.d $xr0, $xr0, $xr2
+; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-OFF-NEXT: ret
entry:
%v0 = load <4 x double>, ptr %a0
%v1 = load <4 x double>, ptr %a1
@@ -46,34 +81,63 @@ entry:
}
define void @xvfmsub_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
-; CONTRACT-FAST-LABEL: xvfmsub_d:
-; CONTRACT-FAST: # %bb.0: # %entry
-; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-FAST-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2
-; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-FAST-NEXT: ret
-;
-; CONTRACT-ON-LABEL: xvfmsub_d:
-; CONTRACT-ON: # %bb.0: # %entry
-; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1
-; CONTRACT-ON-NEXT: xvfsub.d $xr0, $xr0, $xr2
-; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-ON-NEXT: ret
-;
-; CONTRACT-OFF-LABEL: xvfmsub_d:
-; CONTRACT-OFF: # %bb.0: # %entry
-; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1
-; CONTRACT-OFF-NEXT: xvfsub.d $xr0, $xr0, $xr2
-; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-OFF-NEXT: ret
+; LA32-CONTRACT-FAST-LABEL: xvfmsub_d:
+; LA32-CONTRACT-FAST: # %bb.0: # %entry
+; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-FAST-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-FAST-NEXT: ret
+;
+; LA32-CONTRACT-ON-LABEL: xvfmsub_d:
+; LA32-CONTRACT-ON: # %bb.0: # %entry
+; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1
+; LA32-CONTRACT-ON-NEXT: xvfsub.d $xr0, $xr0, $xr2
+; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-ON-NEXT: ret
+;
+; LA32-CONTRACT-OFF-LABEL: xvfmsub_d:
+; LA32-CONTRACT-OFF: # %bb.0: # %entry
+; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1
+; LA32-CONTRACT-OFF-NEXT: xvfsub.d $xr0, $xr0, $xr2
+; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-OFF-NEXT: ret
+;
+; LA64-CONTRACT-FAST-LABEL: xvfmsub_d:
+; LA64-CONTRACT-FAST: # %bb.0: # %entry
+; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-FAST-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-FAST-NEXT: ret
+;
+; LA64-CONTRACT-ON-LABEL: xvfmsub_d:
+; LA64-CONTRACT-ON: # %bb.0: # %entry
+; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1
+; LA64-CONTRACT-ON-NEXT: xvfsub.d $xr0, $xr0, $xr2
+; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-ON-NEXT: ret
+;
+; LA64-CONTRACT-OFF-LABEL: xvfmsub_d:
+; LA64-CONTRACT-OFF: # %bb.0: # %entry
+; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1
+; LA64-CONTRACT-OFF-NEXT: xvfsub.d $xr0, $xr0, $xr2
+; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-OFF-NEXT: ret
entry:
%v0 = load <4 x double>, ptr %a0
%v1 = load <4 x double>, ptr %a1
@@ -85,36 +149,67 @@ entry:
}
define void @xvfnmadd_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
-; CONTRACT-FAST-LABEL: xvfnmadd_d:
-; CONTRACT-FAST: # %bb.0: # %entry
-; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-FAST-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2
-; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-FAST-NEXT: ret
-;
-; CONTRACT-ON-LABEL: xvfnmadd_d:
-; CONTRACT-ON: # %bb.0: # %entry
-; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1
-; CONTRACT-ON-NEXT: xvfadd.d $xr0, $xr0, $xr2
-; CONTRACT-ON-NEXT: xvbitrevi.d $xr0, $xr0, 63
-; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-ON-NEXT: ret
-;
-; CONTRACT-OFF-LABEL: xvfnmadd_d:
-; CONTRACT-OFF: # %bb.0: # %entry
-; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1
-; CONTRACT-OFF-NEXT: xvfadd.d $xr0, $xr0, $xr2
-; CONTRACT-OFF-NEXT: xvbitrevi.d $xr0, $xr0, 63
-; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-OFF-NEXT: ret
+; LA32-CONTRACT-FAST-LABEL: xvfnmadd_d:
+; LA32-CONTRACT-FAST: # %bb.0: # %entry
+; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-FAST-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-FAST-NEXT: ret
+;
+; LA32-CONTRACT-ON-LABEL: xvfnmadd_d:
+; LA32-CONTRACT-ON: # %bb.0: # %entry
+; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1
+; LA32-CONTRACT-ON-NEXT: xvfadd.d $xr0, $xr0, $xr2
+; LA32-CONTRACT-ON-NEXT: xvbitrevi.d $xr0, $xr0, 63
+; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-ON-NEXT: ret
+;
+; LA32-CONTRACT-OFF-LABEL: xvfnmadd_d:
+; LA32-CONTRACT-OFF: # %bb.0: # %entry
+; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1
+; LA32-CONTRACT-OFF-NEXT: xvfadd.d $xr0, $xr0, $xr2
+; LA32-CONTRACT-OFF-NEXT: xvbitrevi.d $xr0, $xr0, 63
+; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-OFF-NEXT: ret
+;
+; LA64-CONTRACT-FAST-LABEL: xvfnmadd_d:
+; LA64-CONTRACT-FAST: # %bb.0: # %entry
+; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-FAST-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-FAST-NEXT: ret
+;
+; LA64-CONTRACT-ON-LABEL: xvfnmadd_d:
+; LA64-CONTRACT-ON: # %bb.0: # %entry
+; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1
+; LA64-CONTRACT-ON-NEXT: xvfadd.d $xr0, $xr0, $xr2
+; LA64-CONTRACT-ON-NEXT: xvbitrevi.d $xr0, $xr0, 63
+; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-ON-NEXT: ret
+;
+; LA64-CONTRACT-OFF-LABEL: xvfnmadd_d:
+; LA64-CONTRACT-OFF: # %bb.0: # %entry
+; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1
+; LA64-CONTRACT-OFF-NEXT: xvfadd.d $xr0, $xr0, $xr2
+; LA64-CONTRACT-OFF-NEXT: xvbitrevi.d $xr0, $xr0, 63
+; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-OFF-NEXT: ret
entry:
%v0 = load <4 x double>, ptr %a0
%v1 = load <4 x double>, ptr %a1
@@ -127,36 +222,67 @@ entry:
}
define void @xvfnmadd_d_nsz(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
-; CONTRACT-FAST-LABEL: xvfnmadd_d_nsz:
-; CONTRACT-FAST: # %bb.0: # %entry
-; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-FAST-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2
-; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-FAST-NEXT: ret
-;
-; CONTRACT-ON-LABEL: xvfnmadd_d_nsz:
-; CONTRACT-ON: # %bb.0: # %entry
-; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-ON-NEXT: xvbitrevi.d $xr0, $xr0, 63
-; CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1
-; CONTRACT-ON-NEXT: xvfsub.d $xr0, $xr0, $xr2
-; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-ON-NEXT: ret
-;
-; CONTRACT-OFF-LABEL: xvfnmadd_d_nsz:
-; CONTRACT-OFF: # %bb.0: # %entry
-; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-OFF-NEXT: xvbitrevi.d $xr0, $xr0, 63
-; CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1
-; CONTRACT-OFF-NEXT: xvfsub.d $xr0, $xr0, $xr2
-; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-OFF-NEXT: ret
+; LA32-CONTRACT-FAST-LABEL: xvfnmadd_d_nsz:
+; LA32-CONTRACT-FAST: # %bb.0: # %entry
+; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-FAST-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-FAST-NEXT: ret
+;
+; LA32-CONTRACT-ON-LABEL: xvfnmadd_d_nsz:
+; LA32-CONTRACT-ON: # %bb.0: # %entry
+; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-ON-NEXT: xvbitrevi.d $xr0, $xr0, 63
+; LA32-CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1
+; LA32-CONTRACT-ON-NEXT: xvfsub.d $xr0, $xr0, $xr2
+; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-ON-NEXT: ret
+;
+; LA32-CONTRACT-OFF-LABEL: xvfnmadd_d_nsz:
+; LA32-CONTRACT-OFF: # %bb.0: # %entry
+; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-OFF-NEXT: xvbitrevi.d $xr0, $xr0, 63
+; LA32-CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1
+; LA32-CONTRACT-OFF-NEXT: xvfsub.d $xr0, $xr0, $xr2
+; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-OFF-NEXT: ret
+;
+; LA64-CONTRACT-FAST-LABEL: xvfnmadd_d_nsz:
+; LA64-CONTRACT-FAST: # %bb.0: # %entry
+; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-FAST-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-FAST-NEXT: ret
+;
+; LA64-CONTRACT-ON-LABEL: xvfnmadd_d_nsz:
+; LA64-CONTRACT-ON: # %bb.0: # %entry
+; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-ON-NEXT: xvbitrevi.d $xr0, $xr0, 63
+; LA64-CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1
+; LA64-CONTRACT-ON-NEXT: xvfsub.d $xr0, $xr0, $xr2
+; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-ON-NEXT: ret
+;
+; LA64-CONTRACT-OFF-LABEL: xvfnmadd_d_nsz:
+; LA64-CONTRACT-OFF: # %bb.0: # %entry
+; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-OFF-NEXT: xvbitrevi.d $xr0, $xr0, 63
+; LA64-CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1
+; LA64-CONTRACT-OFF-NEXT: xvfsub.d $xr0, $xr0, $xr2
+; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-OFF-NEXT: ret
entry:
%v0 = load <4 x double>, ptr %a0
%v1 = load <4 x double>, ptr %a1
@@ -171,37 +297,69 @@ entry:
;; Check that xvfnmadd.d is not emitted.
define void @not_xvfnmadd_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
-; CONTRACT-FAST-LABEL: not_xvfnmadd_d:
-; CONTRACT-FAST: # %bb.0: # %entry
-; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-FAST-NEXT: xvbitrevi.d $xr0, $xr0, 63
-; CONTRACT-FAST-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2
-; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-FAST-NEXT: ret
-;
-; CONTRACT-ON-LABEL: not_xvfnmadd_d:
-; CONTRACT-ON: # %bb.0: # %entry
-; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-ON-NEXT: xvbitrevi.d $xr0, $xr0, 63
-; CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1
-; CONTRACT-ON-NEXT: xvfsub.d $xr0, $xr0, $xr2
-; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-ON-NEXT: ret
-;
-; CONTRACT-OFF-LABEL: not_xvfnmadd_d:
-; CONTRACT-OFF: # %bb.0: # %entry
-; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-OFF-NEXT: xvbitrevi.d $xr0, $xr0, 63
-; CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1
-; CONTRACT-OFF-NEXT: xvfsub.d $xr0, $xr0, $xr2
-; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-OFF-NEXT: ret
+; LA32-CONTRACT-FAST-LABEL: not_xvfnmadd_d:
+; LA32-CONTRACT-FAST: # %bb.0: # %entry
+; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-FAST-NEXT: xvbitrevi.d $xr0, $xr0, 63
+; LA32-CONTRACT-FAST-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-FAST-NEXT: ret
+;
+; LA32-CONTRACT-ON-LABEL: not_xvfnmadd_d:
+; LA32-CONTRACT-ON: # %bb.0: # %entry
+; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-ON-NEXT: xvbitrevi.d $xr0, $xr0, 63
+; LA32-CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1
+; LA32-CONTRACT-ON-NEXT: xvfsub.d $xr0, $xr0, $xr2
+; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-ON-NEXT: ret
+;
+; LA32-CONTRACT-OFF-LABEL: not_xvfnmadd_d:
+; LA32-CONTRACT-OFF: # %bb.0: # %entry
+; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-OFF-NEXT: xvbitrevi.d $xr0, $xr0, 63
+; LA32-CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1
+; LA32-CONTRACT-OFF-NEXT: xvfsub.d $xr0, $xr0, $xr2
+; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-OFF-NEXT: ret
+;
+; LA64-CONTRACT-FAST-LABEL: not_xvfnmadd_d:
+; LA64-CONTRACT-FAST: # %bb.0: # %entry
+; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-FAST-NEXT: xvbitrevi.d $xr0, $xr0, 63
+; LA64-CONTRACT-FAST-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-FAST-NEXT: ret
+;
+; LA64-CONTRACT-ON-LABEL: not_xvfnmadd_d:
+; LA64-CONTRACT-ON: # %bb.0: # %entry
+; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-ON-NEXT: xvbitrevi.d $xr0, $xr0, 63
+; LA64-CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1
+; LA64-CONTRACT-ON-NEXT: xvfsub.d $xr0, $xr0, $xr2
+; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-ON-NEXT: ret
+;
+; LA64-CONTRACT-OFF-LABEL: not_xvfnmadd_d:
+; LA64-CONTRACT-OFF: # %bb.0: # %entry
+; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-OFF-NEXT: xvbitrevi.d $xr0, $xr0, 63
+; LA64-CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1
+; LA64-CONTRACT-OFF-NEXT: xvfsub.d $xr0, $xr0, $xr2
+; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-OFF-NEXT: ret
entry:
%v0 = load <4 x double>, ptr %a0
%v1 = load <4 x double>, ptr %a1
@@ -215,36 +373,67 @@ entry:
}
define void @xvfnmsub_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
-; CONTRACT-FAST-LABEL: xvfnmsub_d:
-; CONTRACT-FAST: # %bb.0: # %entry
-; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-FAST-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2
-; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-FAST-NEXT: ret
-;
-; CONTRACT-ON-LABEL: xvfnmsub_d:
-; CONTRACT-ON: # %bb.0: # %entry
-; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1
-; CONTRACT-ON-NEXT: xvfsub.d $xr0, $xr0, $xr2
-; CONTRACT-ON-NEXT: xvbitrevi.d $xr0, $xr0, 63
-; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-ON-NEXT: ret
-;
-; CONTRACT-OFF-LABEL: xvfnmsub_d:
-; CONTRACT-OFF: # %bb.0: # %entry
-; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1
-; CONTRACT-OFF-NEXT: xvfsub.d $xr0, $xr0, $xr2
-; CONTRACT-OFF-NEXT: xvbitrevi.d $xr0, $xr0, 63
-; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-OFF-NEXT: ret
+; LA32-CONTRACT-FAST-LABEL: xvfnmsub_d:
+; LA32-CONTRACT-FAST: # %bb.0: # %entry
+; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-FAST-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-FAST-NEXT: ret
+;
+; LA32-CONTRACT-ON-LABEL: xvfnmsub_d:
+; LA32-CONTRACT-ON: # %bb.0: # %entry
+; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1
+; LA32-CONTRACT-ON-NEXT: xvfsub.d $xr0, $xr0, $xr2
+; LA32-CONTRACT-ON-NEXT: xvbitrevi.d $xr0, $xr0, 63
+; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-ON-NEXT: ret
+;
+; LA32-CONTRACT-OFF-LABEL: xvfnmsub_d:
+; LA32-CONTRACT-OFF: # %bb.0: # %entry
+; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1
+; LA32-CONTRACT-OFF-NEXT: xvfsub.d $xr0, $xr0, $xr2
+; LA32-CONTRACT-OFF-NEXT: xvbitrevi.d $xr0, $xr0, 63
+; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-OFF-NEXT: ret
+;
+; LA64-CONTRACT-FAST-LABEL: xvfnmsub_d:
+; LA64-CONTRACT-FAST: # %bb.0: # %entry
+; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-FAST-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-FAST-NEXT: ret
+;
+; LA64-CONTRACT-ON-LABEL: xvfnmsub_d:
+; LA64-CONTRACT-ON: # %bb.0: # %entry
+; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1
+; LA64-CONTRACT-ON-NEXT: xvfsub.d $xr0, $xr0, $xr2
+; LA64-CONTRACT-ON-NEXT: xvbitrevi.d $xr0, $xr0, 63
+; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-ON-NEXT: ret
+;
+; LA64-CONTRACT-OFF-LABEL: xvfnmsub_d:
+; LA64-CONTRACT-OFF: # %bb.0: # %entry
+; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1
+; LA64-CONTRACT-OFF-NEXT: xvfsub.d $xr0, $xr0, $xr2
+; LA64-CONTRACT-OFF-NEXT: xvbitrevi.d $xr0, $xr0, 63
+; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-OFF-NEXT: ret
entry:
%v0 = load <4 x double>, ptr %a0
%v1 = load <4 x double>, ptr %a1
@@ -258,34 +447,63 @@ entry:
}
define void @xvfnmsub_d_nsz(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
-; CONTRACT-FAST-LABEL: xvfnmsub_d_nsz:
-; CONTRACT-FAST: # %bb.0: # %entry
-; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-FAST-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2
-; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-FAST-NEXT: ret
-;
-; CONTRACT-ON-LABEL: xvfnmsub_d_nsz:
-; CONTRACT-ON: # %bb.0: # %entry
-; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1
-; CONTRACT-ON-NEXT: xvfsub.d $xr0, $xr2, $xr0
-; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-ON-NEXT: ret
-;
-; CONTRACT-OFF-LABEL: xvfnmsub_d_nsz:
-; CONTRACT-OFF: # %bb.0: # %entry
-; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1
-; CONTRACT-OFF-NEXT: xvfsub.d $xr0, $xr2, $xr0
-; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-OFF-NEXT: ret
+; LA32-CONTRACT-FAST-LABEL: xvfnmsub_d_nsz:
+; LA32-CONTRACT-FAST: # %bb.0: # %entry
+; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-FAST-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-FAST-NEXT: ret
+;
+; LA32-CONTRACT-ON-LABEL: xvfnmsub_d_nsz:
+; LA32-CONTRACT-ON: # %bb.0: # %entry
+; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1
+; LA32-CONTRACT-ON-NEXT: xvfsub.d $xr0, $xr2, $xr0
+; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-ON-NEXT: ret
+;
+; LA32-CONTRACT-OFF-LABEL: xvfnmsub_d_nsz:
+; LA32-CONTRACT-OFF: # %bb.0: # %entry
+; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1
+; LA32-CONTRACT-OFF-NEXT: xvfsub.d $xr0, $xr2, $xr0
+; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-OFF-NEXT: ret
+;
+; LA64-CONTRACT-FAST-LABEL: xvfnmsub_d_nsz:
+; LA64-CONTRACT-FAST: # %bb.0: # %entry
+; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-FAST-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-FAST-NEXT: ret
+;
+; LA64-CONTRACT-ON-LABEL: xvfnmsub_d_nsz:
+; LA64-CONTRACT-ON: # %bb.0: # %entry
+; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1
+; LA64-CONTRACT-ON-NEXT: xvfsub.d $xr0, $xr2, $xr0
+; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-ON-NEXT: ret
+;
+; LA64-CONTRACT-OFF-LABEL: xvfnmsub_d_nsz:
+; LA64-CONTRACT-OFF: # %bb.0: # %entry
+; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1
+; LA64-CONTRACT-OFF-NEXT: xvfsub.d $xr0, $xr2, $xr0
+; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-OFF-NEXT: ret
entry:
%v0 = load <4 x double>, ptr %a0
%v1 = load <4 x double>, ptr %a1
@@ -299,35 +517,65 @@ entry:
;; Check that xvfnmsub.d is not emitted.
define void @not_xvfnmsub_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
-; CONTRACT-FAST-LABEL: not_xvfnmsub_d:
-; CONTRACT-FAST: # %bb.0: # %entry
-; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-FAST-NEXT: xvbitrevi.d $xr0, $xr0, 63
-; CONTRACT-FAST-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2
-; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-FAST-NEXT: ret
-;
-; CONTRACT-ON-LABEL: not_xvfnmsub_d:
-; CONTRACT-ON: # %bb.0: # %entry
-; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1
-; CONTRACT-ON-NEXT: xvfsub.d $xr0, $xr2, $xr0
-; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-ON-NEXT: ret
-;
-; CONTRACT-OFF-LABEL: not_xvfnmsub_d:
-; CONTRACT-OFF: # %bb.0: # %entry
-; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1
-; CONTRACT-OFF-NEXT: xvfsub.d $xr0, $xr2, $xr0
-; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-OFF-NEXT: ret
+; LA32-CONTRACT-FAST-LABEL: not_xvfnmsub_d:
+; LA32-CONTRACT-FAST: # %bb.0: # %entry
+; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-FAST-NEXT: xvbitrevi.d $xr0, $xr0, 63
+; LA32-CONTRACT-FAST-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-FAST-NEXT: ret
+;
+; LA32-CONTRACT-ON-LABEL: not_xvfnmsub_d:
+; LA32-CONTRACT-ON: # %bb.0: # %entry
+; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1
+; LA32-CONTRACT-ON-NEXT: xvfsub.d $xr0, $xr2, $xr0
+; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-ON-NEXT: ret
+;
+; LA32-CONTRACT-OFF-LABEL: not_xvfnmsub_d:
+; LA32-CONTRACT-OFF: # %bb.0: # %entry
+; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1
+; LA32-CONTRACT-OFF-NEXT: xvfsub.d $xr0, $xr2, $xr0
+; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-OFF-NEXT: ret
+;
+; LA64-CONTRACT-FAST-LABEL: not_xvfnmsub_d:
+; LA64-CONTRACT-FAST: # %bb.0: # %entry
+; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-FAST-NEXT: xvbitrevi.d $xr0, $xr0, 63
+; LA64-CONTRACT-FAST-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-FAST-NEXT: ret
+;
+; LA64-CONTRACT-ON-LABEL: not_xvfnmsub_d:
+; LA64-CONTRACT-ON: # %bb.0: # %entry
+; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-ON-NEXT: xvfmul.d $xr0, $xr0, $xr1
+; LA64-CONTRACT-ON-NEXT: xvfsub.d $xr0, $xr2, $xr0
+; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-ON-NEXT: ret
+;
+; LA64-CONTRACT-OFF-LABEL: not_xvfnmsub_d:
+; LA64-CONTRACT-OFF: # %bb.0: # %entry
+; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-OFF-NEXT: xvfmul.d $xr0, $xr0, $xr1
+; LA64-CONTRACT-OFF-NEXT: xvfsub.d $xr0, $xr2, $xr0
+; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-OFF-NEXT: ret
entry:
%v0 = load <4 x double>, ptr %a0
%v1 = load <4 x double>, ptr %a1
@@ -340,32 +588,59 @@ entry:
}
define void @contract_xvfmadd_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
-; CONTRACT-FAST-LABEL: contract_xvfmadd_d:
-; CONTRACT-FAST: # %bb.0: # %entry
-; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-FAST-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2
-; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-FAST-NEXT: ret
-;
-; CONTRACT-ON-LABEL: contract_xvfmadd_d:
-; CONTRACT-ON: # %bb.0: # %entry
-; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-ON-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2
-; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-ON-NEXT: ret
-;
-; CONTRACT-OFF-LABEL: contract_xvfmadd_d:
-; CONTRACT-OFF: # %bb.0: # %entry
-; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-OFF-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2
-; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-OFF-NEXT: ret
+; LA32-CONTRACT-FAST-LABEL: contract_xvfmadd_d:
+; LA32-CONTRACT-FAST: # %bb.0: # %entry
+; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-FAST-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-FAST-NEXT: ret
+;
+; LA32-CONTRACT-ON-LABEL: contract_xvfmadd_d:
+; LA32-CONTRACT-ON: # %bb.0: # %entry
+; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-ON-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-ON-NEXT: ret
+;
+; LA32-CONTRACT-OFF-LABEL: contract_xvfmadd_d:
+; LA32-CONTRACT-OFF: # %bb.0: # %entry
+; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-OFF-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-OFF-NEXT: ret
+;
+; LA64-CONTRACT-FAST-LABEL: contract_xvfmadd_d:
+; LA64-CONTRACT-FAST: # %bb.0: # %entry
+; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-FAST-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-FAST-NEXT: ret
+;
+; LA64-CONTRACT-ON-LABEL: contract_xvfmadd_d:
+; LA64-CONTRACT-ON: # %bb.0: # %entry
+; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-ON-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-ON-NEXT: ret
+;
+; LA64-CONTRACT-OFF-LABEL: contract_xvfmadd_d:
+; LA64-CONTRACT-OFF: # %bb.0: # %entry
+; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-OFF-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-OFF-NEXT: ret
entry:
%v0 = load <4 x double>, ptr %a0
%v1 = load <4 x double>, ptr %a1
@@ -377,32 +652,59 @@ entry:
}
define void @contract_xvfmsub_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
-; CONTRACT-FAST-LABEL: contract_xvfmsub_d:
-; CONTRACT-FAST: # %bb.0: # %entry
-; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-FAST-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2
-; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-FAST-NEXT: ret
-;
-; CONTRACT-ON-LABEL: contract_xvfmsub_d:
-; CONTRACT-ON: # %bb.0: # %entry
-; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-ON-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2
-; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-ON-NEXT: ret
-;
-; CONTRACT-OFF-LABEL: contract_xvfmsub_d:
-; CONTRACT-OFF: # %bb.0: # %entry
-; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-OFF-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2
-; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-OFF-NEXT: ret
+; LA32-CONTRACT-FAST-LABEL: contract_xvfmsub_d:
+; LA32-CONTRACT-FAST: # %bb.0: # %entry
+; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-FAST-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-FAST-NEXT: ret
+;
+; LA32-CONTRACT-ON-LABEL: contract_xvfmsub_d:
+; LA32-CONTRACT-ON: # %bb.0: # %entry
+; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-ON-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-ON-NEXT: ret
+;
+; LA32-CONTRACT-OFF-LABEL: contract_xvfmsub_d:
+; LA32-CONTRACT-OFF: # %bb.0: # %entry
+; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-OFF-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-OFF-NEXT: ret
+;
+; LA64-CONTRACT-FAST-LABEL: contract_xvfmsub_d:
+; LA64-CONTRACT-FAST: # %bb.0: # %entry
+; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-FAST-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-FAST-NEXT: ret
+;
+; LA64-CONTRACT-ON-LABEL: contract_xvfmsub_d:
+; LA64-CONTRACT-ON: # %bb.0: # %entry
+; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-ON-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-ON-NEXT: ret
+;
+; LA64-CONTRACT-OFF-LABEL: contract_xvfmsub_d:
+; LA64-CONTRACT-OFF: # %bb.0: # %entry
+; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-OFF-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-OFF-NEXT: ret
entry:
%v0 = load <4 x double>, ptr %a0
%v1 = load <4 x double>, ptr %a1
@@ -414,32 +716,59 @@ entry:
}
define void @contract_xvfnmadd_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
-; CONTRACT-FAST-LABEL: contract_xvfnmadd_d:
-; CONTRACT-FAST: # %bb.0: # %entry
-; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-FAST-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2
-; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-FAST-NEXT: ret
-;
-; CONTRACT-ON-LABEL: contract_xvfnmadd_d:
-; CONTRACT-ON: # %bb.0: # %entry
-; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-ON-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2
-; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-ON-NEXT: ret
-;
-; CONTRACT-OFF-LABEL: contract_xvfnmadd_d:
-; CONTRACT-OFF: # %bb.0: # %entry
-; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-OFF-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2
-; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-OFF-NEXT: ret
+; LA32-CONTRACT-FAST-LABEL: contract_xvfnmadd_d:
+; LA32-CONTRACT-FAST: # %bb.0: # %entry
+; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-FAST-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-FAST-NEXT: ret
+;
+; LA32-CONTRACT-ON-LABEL: contract_xvfnmadd_d:
+; LA32-CONTRACT-ON: # %bb.0: # %entry
+; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-ON-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-ON-NEXT: ret
+;
+; LA32-CONTRACT-OFF-LABEL: contract_xvfnmadd_d:
+; LA32-CONTRACT-OFF: # %bb.0: # %entry
+; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-OFF-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-OFF-NEXT: ret
+;
+; LA64-CONTRACT-FAST-LABEL: contract_xvfnmadd_d:
+; LA64-CONTRACT-FAST: # %bb.0: # %entry
+; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-FAST-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-FAST-NEXT: ret
+;
+; LA64-CONTRACT-ON-LABEL: contract_xvfnmadd_d:
+; LA64-CONTRACT-ON: # %bb.0: # %entry
+; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-ON-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-ON-NEXT: ret
+;
+; LA64-CONTRACT-OFF-LABEL: contract_xvfnmadd_d:
+; LA64-CONTRACT-OFF: # %bb.0: # %entry
+; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-OFF-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-OFF-NEXT: ret
entry:
%v0 = load <4 x double>, ptr %a0
%v1 = load <4 x double>, ptr %a1
@@ -452,32 +781,59 @@ entry:
}
define void @contract_xvfnmadd_d_nsz(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
-; CONTRACT-FAST-LABEL: contract_xvfnmadd_d_nsz:
-; CONTRACT-FAST: # %bb.0: # %entry
-; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-FAST-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2
-; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-FAST-NEXT: ret
-;
-; CONTRACT-ON-LABEL: contract_xvfnmadd_d_nsz:
-; CONTRACT-ON: # %bb.0: # %entry
-; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-ON-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2
-; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-ON-NEXT: ret
-;
-; CONTRACT-OFF-LABEL: contract_xvfnmadd_d_nsz:
-; CONTRACT-OFF: # %bb.0: # %entry
-; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-OFF-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2
-; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-OFF-NEXT: ret
+; LA32-CONTRACT-FAST-LABEL: contract_xvfnmadd_d_nsz:
+; LA32-CONTRACT-FAST: # %bb.0: # %entry
+; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-FAST-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-FAST-NEXT: ret
+;
+; LA32-CONTRACT-ON-LABEL: contract_xvfnmadd_d_nsz:
+; LA32-CONTRACT-ON: # %bb.0: # %entry
+; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-ON-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-ON-NEXT: ret
+;
+; LA32-CONTRACT-OFF-LABEL: contract_xvfnmadd_d_nsz:
+; LA32-CONTRACT-OFF: # %bb.0: # %entry
+; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-OFF-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-OFF-NEXT: ret
+;
+; LA64-CONTRACT-FAST-LABEL: contract_xvfnmadd_d_nsz:
+; LA64-CONTRACT-FAST: # %bb.0: # %entry
+; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-FAST-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-FAST-NEXT: ret
+;
+; LA64-CONTRACT-ON-LABEL: contract_xvfnmadd_d_nsz:
+; LA64-CONTRACT-ON: # %bb.0: # %entry
+; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-ON-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-ON-NEXT: ret
+;
+; LA64-CONTRACT-OFF-LABEL: contract_xvfnmadd_d_nsz:
+; LA64-CONTRACT-OFF: # %bb.0: # %entry
+; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-OFF-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-OFF-NEXT: ret
entry:
%v0 = load <4 x double>, ptr %a0
%v1 = load <4 x double>, ptr %a1
@@ -492,35 +848,65 @@ entry:
;; Check that xvfnmadd.d is not emitted.
define void @not_contract_xvfnmadd_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
-; CONTRACT-FAST-LABEL: not_contract_xvfnmadd_d:
-; CONTRACT-FAST: # %bb.0: # %entry
-; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-FAST-NEXT: xvbitrevi.d $xr0, $xr0, 63
-; CONTRACT-FAST-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2
-; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-FAST-NEXT: ret
-;
-; CONTRACT-ON-LABEL: not_contract_xvfnmadd_d:
-; CONTRACT-ON: # %bb.0: # %entry
-; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-ON-NEXT: xvbitrevi.d $xr0, $xr0, 63
-; CONTRACT-ON-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2
-; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-ON-NEXT: ret
-;
-; CONTRACT-OFF-LABEL: not_contract_xvfnmadd_d:
-; CONTRACT-OFF: # %bb.0: # %entry
-; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-OFF-NEXT: xvbitrevi.d $xr0, $xr0, 63
-; CONTRACT-OFF-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2
-; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-OFF-NEXT: ret
+; LA32-CONTRACT-FAST-LABEL: not_contract_xvfnmadd_d:
+; LA32-CONTRACT-FAST: # %bb.0: # %entry
+; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-FAST-NEXT: xvbitrevi.d $xr0, $xr0, 63
+; LA32-CONTRACT-FAST-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-FAST-NEXT: ret
+;
+; LA32-CONTRACT-ON-LABEL: not_contract_xvfnmadd_d:
+; LA32-CONTRACT-ON: # %bb.0: # %entry
+; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-ON-NEXT: xvbitrevi.d $xr0, $xr0, 63
+; LA32-CONTRACT-ON-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-ON-NEXT: ret
+;
+; LA32-CONTRACT-OFF-LABEL: not_contract_xvfnmadd_d:
+; LA32-CONTRACT-OFF: # %bb.0: # %entry
+; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-OFF-NEXT: xvbitrevi.d $xr0, $xr0, 63
+; LA32-CONTRACT-OFF-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-OFF-NEXT: ret
+;
+; LA64-CONTRACT-FAST-LABEL: not_contract_xvfnmadd_d:
+; LA64-CONTRACT-FAST: # %bb.0: # %entry
+; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-FAST-NEXT: xvbitrevi.d $xr0, $xr0, 63
+; LA64-CONTRACT-FAST-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-FAST-NEXT: ret
+;
+; LA64-CONTRACT-ON-LABEL: not_contract_xvfnmadd_d:
+; LA64-CONTRACT-ON: # %bb.0: # %entry
+; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-ON-NEXT: xvbitrevi.d $xr0, $xr0, 63
+; LA64-CONTRACT-ON-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-ON-NEXT: ret
+;
+; LA64-CONTRACT-OFF-LABEL: not_contract_xvfnmadd_d:
+; LA64-CONTRACT-OFF: # %bb.0: # %entry
+; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-OFF-NEXT: xvbitrevi.d $xr0, $xr0, 63
+; LA64-CONTRACT-OFF-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-OFF-NEXT: ret
entry:
%v0 = load <4 x double>, ptr %a0
%v1 = load <4 x double>, ptr %a1
@@ -534,32 +920,59 @@ entry:
}
define void @contract_xvfnmsub_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
-; CONTRACT-FAST-LABEL: contract_xvfnmsub_d:
-; CONTRACT-FAST: # %bb.0: # %entry
-; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-FAST-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2
-; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-FAST-NEXT: ret
-;
-; CONTRACT-ON-LABEL: contract_xvfnmsub_d:
-; CONTRACT-ON: # %bb.0: # %entry
-; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-ON-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2
-; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-ON-NEXT: ret
-;
-; CONTRACT-OFF-LABEL: contract_xvfnmsub_d:
-; CONTRACT-OFF: # %bb.0: # %entry
-; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-OFF-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2
-; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-OFF-NEXT: ret
+; LA32-CONTRACT-FAST-LABEL: contract_xvfnmsub_d:
+; LA32-CONTRACT-FAST: # %bb.0: # %entry
+; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-FAST-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-FAST-NEXT: ret
+;
+; LA32-CONTRACT-ON-LABEL: contract_xvfnmsub_d:
+; LA32-CONTRACT-ON: # %bb.0: # %entry
+; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-ON-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-ON-NEXT: ret
+;
+; LA32-CONTRACT-OFF-LABEL: contract_xvfnmsub_d:
+; LA32-CONTRACT-OFF: # %bb.0: # %entry
+; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-OFF-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-OFF-NEXT: ret
+;
+; LA64-CONTRACT-FAST-LABEL: contract_xvfnmsub_d:
+; LA64-CONTRACT-FAST: # %bb.0: # %entry
+; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-FAST-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-FAST-NEXT: ret
+;
+; LA64-CONTRACT-ON-LABEL: contract_xvfnmsub_d:
+; LA64-CONTRACT-ON: # %bb.0: # %entry
+; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-ON-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-ON-NEXT: ret
+;
+; LA64-CONTRACT-OFF-LABEL: contract_xvfnmsub_d:
+; LA64-CONTRACT-OFF: # %bb.0: # %entry
+; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-OFF-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-OFF-NEXT: ret
entry:
%v0 = load <4 x double>, ptr %a0
%v1 = load <4 x double>, ptr %a1
@@ -573,32 +986,59 @@ entry:
}
define void @contract_xvfnmsub_d_nsz(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
-; CONTRACT-FAST-LABEL: contract_xvfnmsub_d_nsz:
-; CONTRACT-FAST: # %bb.0: # %entry
-; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-FAST-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2
-; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-FAST-NEXT: ret
-;
-; CONTRACT-ON-LABEL: contract_xvfnmsub_d_nsz:
-; CONTRACT-ON: # %bb.0: # %entry
-; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-ON-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2
-; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-ON-NEXT: ret
-;
-; CONTRACT-OFF-LABEL: contract_xvfnmsub_d_nsz:
-; CONTRACT-OFF: # %bb.0: # %entry
-; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-OFF-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2
-; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-OFF-NEXT: ret
+; LA32-CONTRACT-FAST-LABEL: contract_xvfnmsub_d_nsz:
+; LA32-CONTRACT-FAST: # %bb.0: # %entry
+; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-FAST-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-FAST-NEXT: ret
+;
+; LA32-CONTRACT-ON-LABEL: contract_xvfnmsub_d_nsz:
+; LA32-CONTRACT-ON: # %bb.0: # %entry
+; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-ON-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-ON-NEXT: ret
+;
+; LA32-CONTRACT-OFF-LABEL: contract_xvfnmsub_d_nsz:
+; LA32-CONTRACT-OFF: # %bb.0: # %entry
+; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-OFF-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-OFF-NEXT: ret
+;
+; LA64-CONTRACT-FAST-LABEL: contract_xvfnmsub_d_nsz:
+; LA64-CONTRACT-FAST: # %bb.0: # %entry
+; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-FAST-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-FAST-NEXT: ret
+;
+; LA64-CONTRACT-ON-LABEL: contract_xvfnmsub_d_nsz:
+; LA64-CONTRACT-ON: # %bb.0: # %entry
+; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-ON-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-ON-NEXT: ret
+;
+; LA64-CONTRACT-OFF-LABEL: contract_xvfnmsub_d_nsz:
+; LA64-CONTRACT-OFF: # %bb.0: # %entry
+; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-OFF-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-OFF-NEXT: ret
entry:
%v0 = load <4 x double>, ptr %a0
%v1 = load <4 x double>, ptr %a1
@@ -612,35 +1052,65 @@ entry:
;; Check that xvfnmsub.d is not emitted.
define void @not_contract_xvfnmsub_d(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
-; CONTRACT-FAST-LABEL: not_contract_xvfnmsub_d:
-; CONTRACT-FAST: # %bb.0: # %entry
-; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-FAST-NEXT: xvbitrevi.d $xr0, $xr0, 63
-; CONTRACT-FAST-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2
-; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-FAST-NEXT: ret
-;
-; CONTRACT-ON-LABEL: not_contract_xvfnmsub_d:
-; CONTRACT-ON: # %bb.0: # %entry
-; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-ON-NEXT: xvbitrevi.d $xr0, $xr0, 63
-; CONTRACT-ON-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2
-; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-ON-NEXT: ret
-;
-; CONTRACT-OFF-LABEL: not_contract_xvfnmsub_d:
-; CONTRACT-OFF: # %bb.0: # %entry
-; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-OFF-NEXT: xvbitrevi.d $xr0, $xr0, 63
-; CONTRACT-OFF-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2
-; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-OFF-NEXT: ret
+; LA32-CONTRACT-FAST-LABEL: not_contract_xvfnmsub_d:
+; LA32-CONTRACT-FAST: # %bb.0: # %entry
+; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-FAST-NEXT: xvbitrevi.d $xr0, $xr0, 63
+; LA32-CONTRACT-FAST-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-FAST-NEXT: ret
+;
+; LA32-CONTRACT-ON-LABEL: not_contract_xvfnmsub_d:
+; LA32-CONTRACT-ON: # %bb.0: # %entry
+; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-ON-NEXT: xvbitrevi.d $xr0, $xr0, 63
+; LA32-CONTRACT-ON-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-ON-NEXT: ret
+;
+; LA32-CONTRACT-OFF-LABEL: not_contract_xvfnmsub_d:
+; LA32-CONTRACT-OFF: # %bb.0: # %entry
+; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-OFF-NEXT: xvbitrevi.d $xr0, $xr0, 63
+; LA32-CONTRACT-OFF-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-OFF-NEXT: ret
+;
+; LA64-CONTRACT-FAST-LABEL: not_contract_xvfnmsub_d:
+; LA64-CONTRACT-FAST: # %bb.0: # %entry
+; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-FAST-NEXT: xvbitrevi.d $xr0, $xr0, 63
+; LA64-CONTRACT-FAST-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-FAST-NEXT: ret
+;
+; LA64-CONTRACT-ON-LABEL: not_contract_xvfnmsub_d:
+; LA64-CONTRACT-ON: # %bb.0: # %entry
+; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-ON-NEXT: xvbitrevi.d $xr0, $xr0, 63
+; LA64-CONTRACT-ON-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-ON-NEXT: ret
+;
+; LA64-CONTRACT-OFF-LABEL: not_contract_xvfnmsub_d:
+; LA64-CONTRACT-OFF: # %bb.0: # %entry
+; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-OFF-NEXT: xvbitrevi.d $xr0, $xr0, 63
+; LA64-CONTRACT-OFF-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-OFF-NEXT: ret
entry:
%v0 = load <4 x double>, ptr %a0
%v1 = load <4 x double>, ptr %a1
@@ -653,32 +1123,59 @@ entry:
}
define void @xvfmadd_d_contract(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
-; CONTRACT-FAST-LABEL: xvfmadd_d_contract:
-; CONTRACT-FAST: # %bb.0: # %entry
-; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-FAST-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2
-; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-FAST-NEXT: ret
-;
-; CONTRACT-ON-LABEL: xvfmadd_d_contract:
-; CONTRACT-ON: # %bb.0: # %entry
-; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-ON-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2
-; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-ON-NEXT: ret
-;
-; CONTRACT-OFF-LABEL: xvfmadd_d_contract:
-; CONTRACT-OFF: # %bb.0: # %entry
-; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-OFF-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2
-; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-OFF-NEXT: ret
+; LA32-CONTRACT-FAST-LABEL: xvfmadd_d_contract:
+; LA32-CONTRACT-FAST: # %bb.0: # %entry
+; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-FAST-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-FAST-NEXT: ret
+;
+; LA32-CONTRACT-ON-LABEL: xvfmadd_d_contract:
+; LA32-CONTRACT-ON: # %bb.0: # %entry
+; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-ON-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-ON-NEXT: ret
+;
+; LA32-CONTRACT-OFF-LABEL: xvfmadd_d_contract:
+; LA32-CONTRACT-OFF: # %bb.0: # %entry
+; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-OFF-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-OFF-NEXT: ret
+;
+; LA64-CONTRACT-FAST-LABEL: xvfmadd_d_contract:
+; LA64-CONTRACT-FAST: # %bb.0: # %entry
+; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-FAST-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-FAST-NEXT: ret
+;
+; LA64-CONTRACT-ON-LABEL: xvfmadd_d_contract:
+; LA64-CONTRACT-ON: # %bb.0: # %entry
+; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-ON-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-ON-NEXT: ret
+;
+; LA64-CONTRACT-OFF-LABEL: xvfmadd_d_contract:
+; LA64-CONTRACT-OFF: # %bb.0: # %entry
+; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-OFF-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-OFF-NEXT: ret
entry:
%v0 = load <4 x double>, ptr %a0
%v1 = load <4 x double>, ptr %a1
@@ -690,32 +1187,59 @@ entry:
}
define void @xvfmsub_d_contract(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
-; CONTRACT-FAST-LABEL: xvfmsub_d_contract:
-; CONTRACT-FAST: # %bb.0: # %entry
-; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-FAST-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2
-; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-FAST-NEXT: ret
-;
-; CONTRACT-ON-LABEL: xvfmsub_d_contract:
-; CONTRACT-ON: # %bb.0: # %entry
-; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-ON-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2
-; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-ON-NEXT: ret
-;
-; CONTRACT-OFF-LABEL: xvfmsub_d_contract:
-; CONTRACT-OFF: # %bb.0: # %entry
-; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-OFF-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2
-; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-OFF-NEXT: ret
+; LA32-CONTRACT-FAST-LABEL: xvfmsub_d_contract:
+; LA32-CONTRACT-FAST: # %bb.0: # %entry
+; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-FAST-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-FAST-NEXT: ret
+;
+; LA32-CONTRACT-ON-LABEL: xvfmsub_d_contract:
+; LA32-CONTRACT-ON: # %bb.0: # %entry
+; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-ON-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-ON-NEXT: ret
+;
+; LA32-CONTRACT-OFF-LABEL: xvfmsub_d_contract:
+; LA32-CONTRACT-OFF: # %bb.0: # %entry
+; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-OFF-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-OFF-NEXT: ret
+;
+; LA64-CONTRACT-FAST-LABEL: xvfmsub_d_contract:
+; LA64-CONTRACT-FAST: # %bb.0: # %entry
+; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-FAST-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-FAST-NEXT: ret
+;
+; LA64-CONTRACT-ON-LABEL: xvfmsub_d_contract:
+; LA64-CONTRACT-ON: # %bb.0: # %entry
+; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-ON-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-ON-NEXT: ret
+;
+; LA64-CONTRACT-OFF-LABEL: xvfmsub_d_contract:
+; LA64-CONTRACT-OFF: # %bb.0: # %entry
+; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-OFF-NEXT: xvfmsub.d $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-OFF-NEXT: ret
entry:
%v0 = load <4 x double>, ptr %a0
%v1 = load <4 x double>, ptr %a1
@@ -727,32 +1251,59 @@ entry:
}
define void @xvfnmadd_d_contract(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
-; CONTRACT-FAST-LABEL: xvfnmadd_d_contract:
-; CONTRACT-FAST: # %bb.0: # %entry
-; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-FAST-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2
-; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-FAST-NEXT: ret
-;
-; CONTRACT-ON-LABEL: xvfnmadd_d_contract:
-; CONTRACT-ON: # %bb.0: # %entry
-; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-ON-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2
-; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-ON-NEXT: ret
-;
-; CONTRACT-OFF-LABEL: xvfnmadd_d_contract:
-; CONTRACT-OFF: # %bb.0: # %entry
-; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-OFF-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2
-; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-OFF-NEXT: ret
+; LA32-CONTRACT-FAST-LABEL: xvfnmadd_d_contract:
+; LA32-CONTRACT-FAST: # %bb.0: # %entry
+; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-FAST-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-FAST-NEXT: ret
+;
+; LA32-CONTRACT-ON-LABEL: xvfnmadd_d_contract:
+; LA32-CONTRACT-ON: # %bb.0: # %entry
+; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-ON-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-ON-NEXT: ret
+;
+; LA32-CONTRACT-OFF-LABEL: xvfnmadd_d_contract:
+; LA32-CONTRACT-OFF: # %bb.0: # %entry
+; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-OFF-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-OFF-NEXT: ret
+;
+; LA64-CONTRACT-FAST-LABEL: xvfnmadd_d_contract:
+; LA64-CONTRACT-FAST: # %bb.0: # %entry
+; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-FAST-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-FAST-NEXT: ret
+;
+; LA64-CONTRACT-ON-LABEL: xvfnmadd_d_contract:
+; LA64-CONTRACT-ON: # %bb.0: # %entry
+; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-ON-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-ON-NEXT: ret
+;
+; LA64-CONTRACT-OFF-LABEL: xvfnmadd_d_contract:
+; LA64-CONTRACT-OFF: # %bb.0: # %entry
+; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-OFF-NEXT: xvfnmadd.d $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-OFF-NEXT: ret
entry:
%v0 = load <4 x double>, ptr %a0
%v1 = load <4 x double>, ptr %a1
@@ -765,32 +1316,59 @@ entry:
}
define void @xvfnmsub_d_contract(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
-; CONTRACT-FAST-LABEL: xvfnmsub_d_contract:
-; CONTRACT-FAST: # %bb.0: # %entry
-; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-FAST-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2
-; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-FAST-NEXT: ret
-;
-; CONTRACT-ON-LABEL: xvfnmsub_d_contract:
-; CONTRACT-ON: # %bb.0: # %entry
-; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-ON-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2
-; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-ON-NEXT: ret
-;
-; CONTRACT-OFF-LABEL: xvfnmsub_d_contract:
-; CONTRACT-OFF: # %bb.0: # %entry
-; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-OFF-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2
-; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-OFF-NEXT: ret
+; LA32-CONTRACT-FAST-LABEL: xvfnmsub_d_contract:
+; LA32-CONTRACT-FAST: # %bb.0: # %entry
+; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-FAST-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-FAST-NEXT: ret
+;
+; LA32-CONTRACT-ON-LABEL: xvfnmsub_d_contract:
+; LA32-CONTRACT-ON: # %bb.0: # %entry
+; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-ON-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-ON-NEXT: ret
+;
+; LA32-CONTRACT-OFF-LABEL: xvfnmsub_d_contract:
+; LA32-CONTRACT-OFF: # %bb.0: # %entry
+; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-OFF-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-OFF-NEXT: ret
+;
+; LA64-CONTRACT-FAST-LABEL: xvfnmsub_d_contract:
+; LA64-CONTRACT-FAST: # %bb.0: # %entry
+; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-FAST-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-FAST-NEXT: ret
+;
+; LA64-CONTRACT-ON-LABEL: xvfnmsub_d_contract:
+; LA64-CONTRACT-ON: # %bb.0: # %entry
+; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-ON-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-ON-NEXT: ret
+;
+; LA64-CONTRACT-OFF-LABEL: xvfnmsub_d_contract:
+; LA64-CONTRACT-OFF: # %bb.0: # %entry
+; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-OFF-NEXT: xvfnmsub.d $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-OFF-NEXT: ret
entry:
%v0 = load <4 x double>, ptr %a0
%v1 = load <4 x double>, ptr %a1
diff --git a/llvm/test/CodeGen/LoongArch/lasx/fma-v8f32.ll b/llvm/test/CodeGen/LoongArch/lasx/fma-v8f32.ll
index 6fd14d93a751e..57b283801675b 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/fma-v8f32.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/fma-v8f32.ll
@@ -1,40 +1,75 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx --fp-contract=fast < %s \
+; RUN: | FileCheck %s --check-prefix=LA32-CONTRACT-FAST
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx --fp-contract=on < %s \
+; RUN: | FileCheck %s --check-prefix=LA32-CONTRACT-ON
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx --fp-contract=off < %s \
+; RUN: | FileCheck %s --check-prefix=LA32-CONTRACT-OFF
; RUN: llc --mtriple=loongarch64 --mattr=+lasx --fp-contract=fast < %s \
-; RUN: | FileCheck %s --check-prefix=CONTRACT-FAST
+; RUN: | FileCheck %s --check-prefix=LA64-CONTRACT-FAST
; RUN: llc --mtriple=loongarch64 --mattr=+lasx --fp-contract=on < %s \
-; RUN: | FileCheck %s --check-prefix=CONTRACT-ON
+; RUN: | FileCheck %s --check-prefix=LA64-CONTRACT-ON
; RUN: llc --mtriple=loongarch64 --mattr=+lasx --fp-contract=off < %s \
-; RUN: | FileCheck %s --check-prefix=CONTRACT-OFF
+; RUN: | FileCheck %s --check-prefix=LA64-CONTRACT-OFF
define void @xvfmadd_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
-; CONTRACT-FAST-LABEL: xvfmadd_s:
-; CONTRACT-FAST: # %bb.0: # %entry
-; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-FAST-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2
-; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-FAST-NEXT: ret
-;
-; CONTRACT-ON-LABEL: xvfmadd_s:
-; CONTRACT-ON: # %bb.0: # %entry
-; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1
-; CONTRACT-ON-NEXT: xvfadd.s $xr0, $xr0, $xr2
-; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-ON-NEXT: ret
-;
-; CONTRACT-OFF-LABEL: xvfmadd_s:
-; CONTRACT-OFF: # %bb.0: # %entry
-; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1
-; CONTRACT-OFF-NEXT: xvfadd.s $xr0, $xr0, $xr2
-; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-OFF-NEXT: ret
+; LA32-CONTRACT-FAST-LABEL: xvfmadd_s:
+; LA32-CONTRACT-FAST: # %bb.0: # %entry
+; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-FAST-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-FAST-NEXT: ret
+;
+; LA32-CONTRACT-ON-LABEL: xvfmadd_s:
+; LA32-CONTRACT-ON: # %bb.0: # %entry
+; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1
+; LA32-CONTRACT-ON-NEXT: xvfadd.s $xr0, $xr0, $xr2
+; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-ON-NEXT: ret
+;
+; LA32-CONTRACT-OFF-LABEL: xvfmadd_s:
+; LA32-CONTRACT-OFF: # %bb.0: # %entry
+; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1
+; LA32-CONTRACT-OFF-NEXT: xvfadd.s $xr0, $xr0, $xr2
+; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-OFF-NEXT: ret
+;
+; LA64-CONTRACT-FAST-LABEL: xvfmadd_s:
+; LA64-CONTRACT-FAST: # %bb.0: # %entry
+; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-FAST-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-FAST-NEXT: ret
+;
+; LA64-CONTRACT-ON-LABEL: xvfmadd_s:
+; LA64-CONTRACT-ON: # %bb.0: # %entry
+; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1
+; LA64-CONTRACT-ON-NEXT: xvfadd.s $xr0, $xr0, $xr2
+; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-ON-NEXT: ret
+;
+; LA64-CONTRACT-OFF-LABEL: xvfmadd_s:
+; LA64-CONTRACT-OFF: # %bb.0: # %entry
+; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1
+; LA64-CONTRACT-OFF-NEXT: xvfadd.s $xr0, $xr0, $xr2
+; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-OFF-NEXT: ret
entry:
%v0 = load <8 x float>, ptr %a0
%v1 = load <8 x float>, ptr %a1
@@ -46,34 +81,63 @@ entry:
}
define void @xvfmsub_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
-; CONTRACT-FAST-LABEL: xvfmsub_s:
-; CONTRACT-FAST: # %bb.0: # %entry
-; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-FAST-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2
-; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-FAST-NEXT: ret
-;
-; CONTRACT-ON-LABEL: xvfmsub_s:
-; CONTRACT-ON: # %bb.0: # %entry
-; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1
-; CONTRACT-ON-NEXT: xvfsub.s $xr0, $xr0, $xr2
-; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-ON-NEXT: ret
-;
-; CONTRACT-OFF-LABEL: xvfmsub_s:
-; CONTRACT-OFF: # %bb.0: # %entry
-; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1
-; CONTRACT-OFF-NEXT: xvfsub.s $xr0, $xr0, $xr2
-; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-OFF-NEXT: ret
+; LA32-CONTRACT-FAST-LABEL: xvfmsub_s:
+; LA32-CONTRACT-FAST: # %bb.0: # %entry
+; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-FAST-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-FAST-NEXT: ret
+;
+; LA32-CONTRACT-ON-LABEL: xvfmsub_s:
+; LA32-CONTRACT-ON: # %bb.0: # %entry
+; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1
+; LA32-CONTRACT-ON-NEXT: xvfsub.s $xr0, $xr0, $xr2
+; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-ON-NEXT: ret
+;
+; LA32-CONTRACT-OFF-LABEL: xvfmsub_s:
+; LA32-CONTRACT-OFF: # %bb.0: # %entry
+; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1
+; LA32-CONTRACT-OFF-NEXT: xvfsub.s $xr0, $xr0, $xr2
+; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-OFF-NEXT: ret
+;
+; LA64-CONTRACT-FAST-LABEL: xvfmsub_s:
+; LA64-CONTRACT-FAST: # %bb.0: # %entry
+; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-FAST-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-FAST-NEXT: ret
+;
+; LA64-CONTRACT-ON-LABEL: xvfmsub_s:
+; LA64-CONTRACT-ON: # %bb.0: # %entry
+; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1
+; LA64-CONTRACT-ON-NEXT: xvfsub.s $xr0, $xr0, $xr2
+; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-ON-NEXT: ret
+;
+; LA64-CONTRACT-OFF-LABEL: xvfmsub_s:
+; LA64-CONTRACT-OFF: # %bb.0: # %entry
+; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1
+; LA64-CONTRACT-OFF-NEXT: xvfsub.s $xr0, $xr0, $xr2
+; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-OFF-NEXT: ret
entry:
%v0 = load <8 x float>, ptr %a0
%v1 = load <8 x float>, ptr %a1
@@ -85,36 +149,67 @@ entry:
}
define void @xvfnmadd_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
-; CONTRACT-FAST-LABEL: xvfnmadd_s:
-; CONTRACT-FAST: # %bb.0: # %entry
-; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-FAST-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2
-; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-FAST-NEXT: ret
-;
-; CONTRACT-ON-LABEL: xvfnmadd_s:
-; CONTRACT-ON: # %bb.0: # %entry
-; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1
-; CONTRACT-ON-NEXT: xvfadd.s $xr0, $xr0, $xr2
-; CONTRACT-ON-NEXT: xvbitrevi.w $xr0, $xr0, 31
-; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-ON-NEXT: ret
-;
-; CONTRACT-OFF-LABEL: xvfnmadd_s:
-; CONTRACT-OFF: # %bb.0: # %entry
-; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1
-; CONTRACT-OFF-NEXT: xvfadd.s $xr0, $xr0, $xr2
-; CONTRACT-OFF-NEXT: xvbitrevi.w $xr0, $xr0, 31
-; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-OFF-NEXT: ret
+; LA32-CONTRACT-FAST-LABEL: xvfnmadd_s:
+; LA32-CONTRACT-FAST: # %bb.0: # %entry
+; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-FAST-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-FAST-NEXT: ret
+;
+; LA32-CONTRACT-ON-LABEL: xvfnmadd_s:
+; LA32-CONTRACT-ON: # %bb.0: # %entry
+; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1
+; LA32-CONTRACT-ON-NEXT: xvfadd.s $xr0, $xr0, $xr2
+; LA32-CONTRACT-ON-NEXT: xvbitrevi.w $xr0, $xr0, 31
+; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-ON-NEXT: ret
+;
+; LA32-CONTRACT-OFF-LABEL: xvfnmadd_s:
+; LA32-CONTRACT-OFF: # %bb.0: # %entry
+; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1
+; LA32-CONTRACT-OFF-NEXT: xvfadd.s $xr0, $xr0, $xr2
+; LA32-CONTRACT-OFF-NEXT: xvbitrevi.w $xr0, $xr0, 31
+; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-OFF-NEXT: ret
+;
+; LA64-CONTRACT-FAST-LABEL: xvfnmadd_s:
+; LA64-CONTRACT-FAST: # %bb.0: # %entry
+; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-FAST-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-FAST-NEXT: ret
+;
+; LA64-CONTRACT-ON-LABEL: xvfnmadd_s:
+; LA64-CONTRACT-ON: # %bb.0: # %entry
+; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1
+; LA64-CONTRACT-ON-NEXT: xvfadd.s $xr0, $xr0, $xr2
+; LA64-CONTRACT-ON-NEXT: xvbitrevi.w $xr0, $xr0, 31
+; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-ON-NEXT: ret
+;
+; LA64-CONTRACT-OFF-LABEL: xvfnmadd_s:
+; LA64-CONTRACT-OFF: # %bb.0: # %entry
+; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1
+; LA64-CONTRACT-OFF-NEXT: xvfadd.s $xr0, $xr0, $xr2
+; LA64-CONTRACT-OFF-NEXT: xvbitrevi.w $xr0, $xr0, 31
+; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-OFF-NEXT: ret
entry:
%v0 = load <8 x float>, ptr %a0
%v1 = load <8 x float>, ptr %a1
@@ -127,36 +222,67 @@ entry:
}
define void @xvfnmadd_s_nsz(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
-; CONTRACT-FAST-LABEL: xvfnmadd_s_nsz:
-; CONTRACT-FAST: # %bb.0: # %entry
-; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-FAST-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2
-; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-FAST-NEXT: ret
-;
-; CONTRACT-ON-LABEL: xvfnmadd_s_nsz:
-; CONTRACT-ON: # %bb.0: # %entry
-; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-ON-NEXT: xvbitrevi.w $xr0, $xr0, 31
-; CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1
-; CONTRACT-ON-NEXT: xvfsub.s $xr0, $xr0, $xr2
-; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-ON-NEXT: ret
-;
-; CONTRACT-OFF-LABEL: xvfnmadd_s_nsz:
-; CONTRACT-OFF: # %bb.0: # %entry
-; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-OFF-NEXT: xvbitrevi.w $xr0, $xr0, 31
-; CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1
-; CONTRACT-OFF-NEXT: xvfsub.s $xr0, $xr0, $xr2
-; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-OFF-NEXT: ret
+; LA32-CONTRACT-FAST-LABEL: xvfnmadd_s_nsz:
+; LA32-CONTRACT-FAST: # %bb.0: # %entry
+; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-FAST-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-FAST-NEXT: ret
+;
+; LA32-CONTRACT-ON-LABEL: xvfnmadd_s_nsz:
+; LA32-CONTRACT-ON: # %bb.0: # %entry
+; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-ON-NEXT: xvbitrevi.w $xr0, $xr0, 31
+; LA32-CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1
+; LA32-CONTRACT-ON-NEXT: xvfsub.s $xr0, $xr0, $xr2
+; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-ON-NEXT: ret
+;
+; LA32-CONTRACT-OFF-LABEL: xvfnmadd_s_nsz:
+; LA32-CONTRACT-OFF: # %bb.0: # %entry
+; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-OFF-NEXT: xvbitrevi.w $xr0, $xr0, 31
+; LA32-CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1
+; LA32-CONTRACT-OFF-NEXT: xvfsub.s $xr0, $xr0, $xr2
+; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-OFF-NEXT: ret
+;
+; LA64-CONTRACT-FAST-LABEL: xvfnmadd_s_nsz:
+; LA64-CONTRACT-FAST: # %bb.0: # %entry
+; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-FAST-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-FAST-NEXT: ret
+;
+; LA64-CONTRACT-ON-LABEL: xvfnmadd_s_nsz:
+; LA64-CONTRACT-ON: # %bb.0: # %entry
+; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-ON-NEXT: xvbitrevi.w $xr0, $xr0, 31
+; LA64-CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1
+; LA64-CONTRACT-ON-NEXT: xvfsub.s $xr0, $xr0, $xr2
+; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-ON-NEXT: ret
+;
+; LA64-CONTRACT-OFF-LABEL: xvfnmadd_s_nsz:
+; LA64-CONTRACT-OFF: # %bb.0: # %entry
+; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-OFF-NEXT: xvbitrevi.w $xr0, $xr0, 31
+; LA64-CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1
+; LA64-CONTRACT-OFF-NEXT: xvfsub.s $xr0, $xr0, $xr2
+; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-OFF-NEXT: ret
entry:
%v0 = load <8 x float>, ptr %a0
%v1 = load <8 x float>, ptr %a1
@@ -171,37 +297,69 @@ entry:
;; Check that fnmadd.s is not emitted.
define void @not_xvfnmadd_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
-; CONTRACT-FAST-LABEL: not_xvfnmadd_s:
-; CONTRACT-FAST: # %bb.0: # %entry
-; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-FAST-NEXT: xvbitrevi.w $xr0, $xr0, 31
-; CONTRACT-FAST-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2
-; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-FAST-NEXT: ret
-;
-; CONTRACT-ON-LABEL: not_xvfnmadd_s:
-; CONTRACT-ON: # %bb.0: # %entry
-; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-ON-NEXT: xvbitrevi.w $xr0, $xr0, 31
-; CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1
-; CONTRACT-ON-NEXT: xvfsub.s $xr0, $xr0, $xr2
-; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-ON-NEXT: ret
-;
-; CONTRACT-OFF-LABEL: not_xvfnmadd_s:
-; CONTRACT-OFF: # %bb.0: # %entry
-; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-OFF-NEXT: xvbitrevi.w $xr0, $xr0, 31
-; CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1
-; CONTRACT-OFF-NEXT: xvfsub.s $xr0, $xr0, $xr2
-; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-OFF-NEXT: ret
+; LA32-CONTRACT-FAST-LABEL: not_xvfnmadd_s:
+; LA32-CONTRACT-FAST: # %bb.0: # %entry
+; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-FAST-NEXT: xvbitrevi.w $xr0, $xr0, 31
+; LA32-CONTRACT-FAST-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-FAST-NEXT: ret
+;
+; LA32-CONTRACT-ON-LABEL: not_xvfnmadd_s:
+; LA32-CONTRACT-ON: # %bb.0: # %entry
+; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-ON-NEXT: xvbitrevi.w $xr0, $xr0, 31
+; LA32-CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1
+; LA32-CONTRACT-ON-NEXT: xvfsub.s $xr0, $xr0, $xr2
+; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-ON-NEXT: ret
+;
+; LA32-CONTRACT-OFF-LABEL: not_xvfnmadd_s:
+; LA32-CONTRACT-OFF: # %bb.0: # %entry
+; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-OFF-NEXT: xvbitrevi.w $xr0, $xr0, 31
+; LA32-CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1
+; LA32-CONTRACT-OFF-NEXT: xvfsub.s $xr0, $xr0, $xr2
+; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-OFF-NEXT: ret
+;
+; LA64-CONTRACT-FAST-LABEL: not_xvfnmadd_s:
+; LA64-CONTRACT-FAST: # %bb.0: # %entry
+; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-FAST-NEXT: xvbitrevi.w $xr0, $xr0, 31
+; LA64-CONTRACT-FAST-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-FAST-NEXT: ret
+;
+; LA64-CONTRACT-ON-LABEL: not_xvfnmadd_s:
+; LA64-CONTRACT-ON: # %bb.0: # %entry
+; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-ON-NEXT: xvbitrevi.w $xr0, $xr0, 31
+; LA64-CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1
+; LA64-CONTRACT-ON-NEXT: xvfsub.s $xr0, $xr0, $xr2
+; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-ON-NEXT: ret
+;
+; LA64-CONTRACT-OFF-LABEL: not_xvfnmadd_s:
+; LA64-CONTRACT-OFF: # %bb.0: # %entry
+; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-OFF-NEXT: xvbitrevi.w $xr0, $xr0, 31
+; LA64-CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1
+; LA64-CONTRACT-OFF-NEXT: xvfsub.s $xr0, $xr0, $xr2
+; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-OFF-NEXT: ret
entry:
%v0 = load <8 x float>, ptr %a0
%v1 = load <8 x float>, ptr %a1
@@ -215,36 +373,67 @@ entry:
}
define void @xvfnmsub_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
-; CONTRACT-FAST-LABEL: xvfnmsub_s:
-; CONTRACT-FAST: # %bb.0: # %entry
-; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-FAST-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2
-; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-FAST-NEXT: ret
-;
-; CONTRACT-ON-LABEL: xvfnmsub_s:
-; CONTRACT-ON: # %bb.0: # %entry
-; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1
-; CONTRACT-ON-NEXT: xvfsub.s $xr0, $xr0, $xr2
-; CONTRACT-ON-NEXT: xvbitrevi.w $xr0, $xr0, 31
-; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-ON-NEXT: ret
-;
-; CONTRACT-OFF-LABEL: xvfnmsub_s:
-; CONTRACT-OFF: # %bb.0: # %entry
-; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1
-; CONTRACT-OFF-NEXT: xvfsub.s $xr0, $xr0, $xr2
-; CONTRACT-OFF-NEXT: xvbitrevi.w $xr0, $xr0, 31
-; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-OFF-NEXT: ret
+; LA32-CONTRACT-FAST-LABEL: xvfnmsub_s:
+; LA32-CONTRACT-FAST: # %bb.0: # %entry
+; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-FAST-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-FAST-NEXT: ret
+;
+; LA32-CONTRACT-ON-LABEL: xvfnmsub_s:
+; LA32-CONTRACT-ON: # %bb.0: # %entry
+; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1
+; LA32-CONTRACT-ON-NEXT: xvfsub.s $xr0, $xr0, $xr2
+; LA32-CONTRACT-ON-NEXT: xvbitrevi.w $xr0, $xr0, 31
+; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-ON-NEXT: ret
+;
+; LA32-CONTRACT-OFF-LABEL: xvfnmsub_s:
+; LA32-CONTRACT-OFF: # %bb.0: # %entry
+; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1
+; LA32-CONTRACT-OFF-NEXT: xvfsub.s $xr0, $xr0, $xr2
+; LA32-CONTRACT-OFF-NEXT: xvbitrevi.w $xr0, $xr0, 31
+; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-OFF-NEXT: ret
+;
+; LA64-CONTRACT-FAST-LABEL: xvfnmsub_s:
+; LA64-CONTRACT-FAST: # %bb.0: # %entry
+; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-FAST-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-FAST-NEXT: ret
+;
+; LA64-CONTRACT-ON-LABEL: xvfnmsub_s:
+; LA64-CONTRACT-ON: # %bb.0: # %entry
+; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1
+; LA64-CONTRACT-ON-NEXT: xvfsub.s $xr0, $xr0, $xr2
+; LA64-CONTRACT-ON-NEXT: xvbitrevi.w $xr0, $xr0, 31
+; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-ON-NEXT: ret
+;
+; LA64-CONTRACT-OFF-LABEL: xvfnmsub_s:
+; LA64-CONTRACT-OFF: # %bb.0: # %entry
+; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1
+; LA64-CONTRACT-OFF-NEXT: xvfsub.s $xr0, $xr0, $xr2
+; LA64-CONTRACT-OFF-NEXT: xvbitrevi.w $xr0, $xr0, 31
+; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-OFF-NEXT: ret
entry:
%v0 = load <8 x float>, ptr %a0
%v1 = load <8 x float>, ptr %a1
@@ -258,34 +447,63 @@ entry:
}
define void @xvfnmsub_s_nsz(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
-; CONTRACT-FAST-LABEL: xvfnmsub_s_nsz:
-; CONTRACT-FAST: # %bb.0: # %entry
-; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-FAST-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2
-; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-FAST-NEXT: ret
-;
-; CONTRACT-ON-LABEL: xvfnmsub_s_nsz:
-; CONTRACT-ON: # %bb.0: # %entry
-; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1
-; CONTRACT-ON-NEXT: xvfsub.s $xr0, $xr2, $xr0
-; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-ON-NEXT: ret
-;
-; CONTRACT-OFF-LABEL: xvfnmsub_s_nsz:
-; CONTRACT-OFF: # %bb.0: # %entry
-; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1
-; CONTRACT-OFF-NEXT: xvfsub.s $xr0, $xr2, $xr0
-; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-OFF-NEXT: ret
+; LA32-CONTRACT-FAST-LABEL: xvfnmsub_s_nsz:
+; LA32-CONTRACT-FAST: # %bb.0: # %entry
+; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-FAST-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-FAST-NEXT: ret
+;
+; LA32-CONTRACT-ON-LABEL: xvfnmsub_s_nsz:
+; LA32-CONTRACT-ON: # %bb.0: # %entry
+; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1
+; LA32-CONTRACT-ON-NEXT: xvfsub.s $xr0, $xr2, $xr0
+; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-ON-NEXT: ret
+;
+; LA32-CONTRACT-OFF-LABEL: xvfnmsub_s_nsz:
+; LA32-CONTRACT-OFF: # %bb.0: # %entry
+; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1
+; LA32-CONTRACT-OFF-NEXT: xvfsub.s $xr0, $xr2, $xr0
+; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-OFF-NEXT: ret
+;
+; LA64-CONTRACT-FAST-LABEL: xvfnmsub_s_nsz:
+; LA64-CONTRACT-FAST: # %bb.0: # %entry
+; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-FAST-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-FAST-NEXT: ret
+;
+; LA64-CONTRACT-ON-LABEL: xvfnmsub_s_nsz:
+; LA64-CONTRACT-ON: # %bb.0: # %entry
+; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1
+; LA64-CONTRACT-ON-NEXT: xvfsub.s $xr0, $xr2, $xr0
+; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-ON-NEXT: ret
+;
+; LA64-CONTRACT-OFF-LABEL: xvfnmsub_s_nsz:
+; LA64-CONTRACT-OFF: # %bb.0: # %entry
+; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1
+; LA64-CONTRACT-OFF-NEXT: xvfsub.s $xr0, $xr2, $xr0
+; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-OFF-NEXT: ret
entry:
%v0 = load <8 x float>, ptr %a0
%v1 = load <8 x float>, ptr %a1
@@ -299,35 +517,65 @@ entry:
;; Check that fnmsub.s is not emitted.
define void @not_xvfnmsub_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
-; CONTRACT-FAST-LABEL: not_xvfnmsub_s:
-; CONTRACT-FAST: # %bb.0: # %entry
-; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-FAST-NEXT: xvbitrevi.w $xr0, $xr0, 31
-; CONTRACT-FAST-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2
-; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-FAST-NEXT: ret
-;
-; CONTRACT-ON-LABEL: not_xvfnmsub_s:
-; CONTRACT-ON: # %bb.0: # %entry
-; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1
-; CONTRACT-ON-NEXT: xvfsub.s $xr0, $xr2, $xr0
-; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-ON-NEXT: ret
-;
-; CONTRACT-OFF-LABEL: not_xvfnmsub_s:
-; CONTRACT-OFF: # %bb.0: # %entry
-; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1
-; CONTRACT-OFF-NEXT: xvfsub.s $xr0, $xr2, $xr0
-; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-OFF-NEXT: ret
+; LA32-CONTRACT-FAST-LABEL: not_xvfnmsub_s:
+; LA32-CONTRACT-FAST: # %bb.0: # %entry
+; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-FAST-NEXT: xvbitrevi.w $xr0, $xr0, 31
+; LA32-CONTRACT-FAST-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-FAST-NEXT: ret
+;
+; LA32-CONTRACT-ON-LABEL: not_xvfnmsub_s:
+; LA32-CONTRACT-ON: # %bb.0: # %entry
+; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1
+; LA32-CONTRACT-ON-NEXT: xvfsub.s $xr0, $xr2, $xr0
+; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-ON-NEXT: ret
+;
+; LA32-CONTRACT-OFF-LABEL: not_xvfnmsub_s:
+; LA32-CONTRACT-OFF: # %bb.0: # %entry
+; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1
+; LA32-CONTRACT-OFF-NEXT: xvfsub.s $xr0, $xr2, $xr0
+; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-OFF-NEXT: ret
+;
+; LA64-CONTRACT-FAST-LABEL: not_xvfnmsub_s:
+; LA64-CONTRACT-FAST: # %bb.0: # %entry
+; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-FAST-NEXT: xvbitrevi.w $xr0, $xr0, 31
+; LA64-CONTRACT-FAST-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-FAST-NEXT: ret
+;
+; LA64-CONTRACT-ON-LABEL: not_xvfnmsub_s:
+; LA64-CONTRACT-ON: # %bb.0: # %entry
+; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-ON-NEXT: xvfmul.s $xr0, $xr0, $xr1
+; LA64-CONTRACT-ON-NEXT: xvfsub.s $xr0, $xr2, $xr0
+; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-ON-NEXT: ret
+;
+; LA64-CONTRACT-OFF-LABEL: not_xvfnmsub_s:
+; LA64-CONTRACT-OFF: # %bb.0: # %entry
+; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-OFF-NEXT: xvfmul.s $xr0, $xr0, $xr1
+; LA64-CONTRACT-OFF-NEXT: xvfsub.s $xr0, $xr2, $xr0
+; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-OFF-NEXT: ret
entry:
%v0 = load <8 x float>, ptr %a0
%v1 = load <8 x float>, ptr %a1
@@ -340,32 +588,59 @@ entry:
}
define void @contract_xvfmadd_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
-; CONTRACT-FAST-LABEL: contract_xvfmadd_s:
-; CONTRACT-FAST: # %bb.0: # %entry
-; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-FAST-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2
-; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-FAST-NEXT: ret
-;
-; CONTRACT-ON-LABEL: contract_xvfmadd_s:
-; CONTRACT-ON: # %bb.0: # %entry
-; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-ON-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2
-; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-ON-NEXT: ret
-;
-; CONTRACT-OFF-LABEL: contract_xvfmadd_s:
-; CONTRACT-OFF: # %bb.0: # %entry
-; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-OFF-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2
-; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-OFF-NEXT: ret
+; LA32-CONTRACT-FAST-LABEL: contract_xvfmadd_s:
+; LA32-CONTRACT-FAST: # %bb.0: # %entry
+; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-FAST-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-FAST-NEXT: ret
+;
+; LA32-CONTRACT-ON-LABEL: contract_xvfmadd_s:
+; LA32-CONTRACT-ON: # %bb.0: # %entry
+; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-ON-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-ON-NEXT: ret
+;
+; LA32-CONTRACT-OFF-LABEL: contract_xvfmadd_s:
+; LA32-CONTRACT-OFF: # %bb.0: # %entry
+; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-OFF-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-OFF-NEXT: ret
+;
+; LA64-CONTRACT-FAST-LABEL: contract_xvfmadd_s:
+; LA64-CONTRACT-FAST: # %bb.0: # %entry
+; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-FAST-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-FAST-NEXT: ret
+;
+; LA64-CONTRACT-ON-LABEL: contract_xvfmadd_s:
+; LA64-CONTRACT-ON: # %bb.0: # %entry
+; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-ON-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-ON-NEXT: ret
+;
+; LA64-CONTRACT-OFF-LABEL: contract_xvfmadd_s:
+; LA64-CONTRACT-OFF: # %bb.0: # %entry
+; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-OFF-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-OFF-NEXT: ret
entry:
%v0 = load <8 x float>, ptr %a0
%v1 = load <8 x float>, ptr %a1
@@ -377,32 +652,59 @@ entry:
}
define void @contract_xvfmsub_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
-; CONTRACT-FAST-LABEL: contract_xvfmsub_s:
-; CONTRACT-FAST: # %bb.0: # %entry
-; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-FAST-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2
-; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-FAST-NEXT: ret
-;
-; CONTRACT-ON-LABEL: contract_xvfmsub_s:
-; CONTRACT-ON: # %bb.0: # %entry
-; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-ON-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2
-; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-ON-NEXT: ret
-;
-; CONTRACT-OFF-LABEL: contract_xvfmsub_s:
-; CONTRACT-OFF: # %bb.0: # %entry
-; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-OFF-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2
-; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-OFF-NEXT: ret
+; LA32-CONTRACT-FAST-LABEL: contract_xvfmsub_s:
+; LA32-CONTRACT-FAST: # %bb.0: # %entry
+; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-FAST-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-FAST-NEXT: ret
+;
+; LA32-CONTRACT-ON-LABEL: contract_xvfmsub_s:
+; LA32-CONTRACT-ON: # %bb.0: # %entry
+; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-ON-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-ON-NEXT: ret
+;
+; LA32-CONTRACT-OFF-LABEL: contract_xvfmsub_s:
+; LA32-CONTRACT-OFF: # %bb.0: # %entry
+; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-OFF-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-OFF-NEXT: ret
+;
+; LA64-CONTRACT-FAST-LABEL: contract_xvfmsub_s:
+; LA64-CONTRACT-FAST: # %bb.0: # %entry
+; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-FAST-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-FAST-NEXT: ret
+;
+; LA64-CONTRACT-ON-LABEL: contract_xvfmsub_s:
+; LA64-CONTRACT-ON: # %bb.0: # %entry
+; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-ON-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-ON-NEXT: ret
+;
+; LA64-CONTRACT-OFF-LABEL: contract_xvfmsub_s:
+; LA64-CONTRACT-OFF: # %bb.0: # %entry
+; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-OFF-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-OFF-NEXT: ret
entry:
%v0 = load <8 x float>, ptr %a0
%v1 = load <8 x float>, ptr %a1
@@ -414,32 +716,59 @@ entry:
}
define void @contract_xvfnmadd_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
-; CONTRACT-FAST-LABEL: contract_xvfnmadd_s:
-; CONTRACT-FAST: # %bb.0: # %entry
-; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-FAST-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2
-; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-FAST-NEXT: ret
-;
-; CONTRACT-ON-LABEL: contract_xvfnmadd_s:
-; CONTRACT-ON: # %bb.0: # %entry
-; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-ON-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2
-; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-ON-NEXT: ret
-;
-; CONTRACT-OFF-LABEL: contract_xvfnmadd_s:
-; CONTRACT-OFF: # %bb.0: # %entry
-; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-OFF-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2
-; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-OFF-NEXT: ret
+; LA32-CONTRACT-FAST-LABEL: contract_xvfnmadd_s:
+; LA32-CONTRACT-FAST: # %bb.0: # %entry
+; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-FAST-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-FAST-NEXT: ret
+;
+; LA32-CONTRACT-ON-LABEL: contract_xvfnmadd_s:
+; LA32-CONTRACT-ON: # %bb.0: # %entry
+; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-ON-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-ON-NEXT: ret
+;
+; LA32-CONTRACT-OFF-LABEL: contract_xvfnmadd_s:
+; LA32-CONTRACT-OFF: # %bb.0: # %entry
+; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-OFF-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-OFF-NEXT: ret
+;
+; LA64-CONTRACT-FAST-LABEL: contract_xvfnmadd_s:
+; LA64-CONTRACT-FAST: # %bb.0: # %entry
+; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-FAST-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-FAST-NEXT: ret
+;
+; LA64-CONTRACT-ON-LABEL: contract_xvfnmadd_s:
+; LA64-CONTRACT-ON: # %bb.0: # %entry
+; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-ON-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-ON-NEXT: ret
+;
+; LA64-CONTRACT-OFF-LABEL: contract_xvfnmadd_s:
+; LA64-CONTRACT-OFF: # %bb.0: # %entry
+; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-OFF-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-OFF-NEXT: ret
entry:
%v0 = load <8 x float>, ptr %a0
%v1 = load <8 x float>, ptr %a1
@@ -452,32 +781,59 @@ entry:
}
define void @contract_xvfnmadd_s_nsz(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
-; CONTRACT-FAST-LABEL: contract_xvfnmadd_s_nsz:
-; CONTRACT-FAST: # %bb.0: # %entry
-; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-FAST-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2
-; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-FAST-NEXT: ret
-;
-; CONTRACT-ON-LABEL: contract_xvfnmadd_s_nsz:
-; CONTRACT-ON: # %bb.0: # %entry
-; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-ON-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2
-; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-ON-NEXT: ret
-;
-; CONTRACT-OFF-LABEL: contract_xvfnmadd_s_nsz:
-; CONTRACT-OFF: # %bb.0: # %entry
-; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-OFF-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2
-; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-OFF-NEXT: ret
+; LA32-CONTRACT-FAST-LABEL: contract_xvfnmadd_s_nsz:
+; LA32-CONTRACT-FAST: # %bb.0: # %entry
+; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-FAST-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-FAST-NEXT: ret
+;
+; LA32-CONTRACT-ON-LABEL: contract_xvfnmadd_s_nsz:
+; LA32-CONTRACT-ON: # %bb.0: # %entry
+; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-ON-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-ON-NEXT: ret
+;
+; LA32-CONTRACT-OFF-LABEL: contract_xvfnmadd_s_nsz:
+; LA32-CONTRACT-OFF: # %bb.0: # %entry
+; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-OFF-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-OFF-NEXT: ret
+;
+; LA64-CONTRACT-FAST-LABEL: contract_xvfnmadd_s_nsz:
+; LA64-CONTRACT-FAST: # %bb.0: # %entry
+; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-FAST-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-FAST-NEXT: ret
+;
+; LA64-CONTRACT-ON-LABEL: contract_xvfnmadd_s_nsz:
+; LA64-CONTRACT-ON: # %bb.0: # %entry
+; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-ON-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-ON-NEXT: ret
+;
+; LA64-CONTRACT-OFF-LABEL: contract_xvfnmadd_s_nsz:
+; LA64-CONTRACT-OFF: # %bb.0: # %entry
+; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-OFF-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-OFF-NEXT: ret
entry:
%v0 = load <8 x float>, ptr %a0
%v1 = load <8 x float>, ptr %a1
@@ -492,35 +848,65 @@ entry:
;; Check that fnmadd.s is not emitted.
define void @not_contract_xvfnmadd_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
-; CONTRACT-FAST-LABEL: not_contract_xvfnmadd_s:
-; CONTRACT-FAST: # %bb.0: # %entry
-; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-FAST-NEXT: xvbitrevi.w $xr0, $xr0, 31
-; CONTRACT-FAST-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2
-; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-FAST-NEXT: ret
-;
-; CONTRACT-ON-LABEL: not_contract_xvfnmadd_s:
-; CONTRACT-ON: # %bb.0: # %entry
-; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-ON-NEXT: xvbitrevi.w $xr0, $xr0, 31
-; CONTRACT-ON-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2
-; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-ON-NEXT: ret
-;
-; CONTRACT-OFF-LABEL: not_contract_xvfnmadd_s:
-; CONTRACT-OFF: # %bb.0: # %entry
-; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-OFF-NEXT: xvbitrevi.w $xr0, $xr0, 31
-; CONTRACT-OFF-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2
-; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-OFF-NEXT: ret
+; LA32-CONTRACT-FAST-LABEL: not_contract_xvfnmadd_s:
+; LA32-CONTRACT-FAST: # %bb.0: # %entry
+; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-FAST-NEXT: xvbitrevi.w $xr0, $xr0, 31
+; LA32-CONTRACT-FAST-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-FAST-NEXT: ret
+;
+; LA32-CONTRACT-ON-LABEL: not_contract_xvfnmadd_s:
+; LA32-CONTRACT-ON: # %bb.0: # %entry
+; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-ON-NEXT: xvbitrevi.w $xr0, $xr0, 31
+; LA32-CONTRACT-ON-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-ON-NEXT: ret
+;
+; LA32-CONTRACT-OFF-LABEL: not_contract_xvfnmadd_s:
+; LA32-CONTRACT-OFF: # %bb.0: # %entry
+; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-OFF-NEXT: xvbitrevi.w $xr0, $xr0, 31
+; LA32-CONTRACT-OFF-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-OFF-NEXT: ret
+;
+; LA64-CONTRACT-FAST-LABEL: not_contract_xvfnmadd_s:
+; LA64-CONTRACT-FAST: # %bb.0: # %entry
+; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-FAST-NEXT: xvbitrevi.w $xr0, $xr0, 31
+; LA64-CONTRACT-FAST-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-FAST-NEXT: ret
+;
+; LA64-CONTRACT-ON-LABEL: not_contract_xvfnmadd_s:
+; LA64-CONTRACT-ON: # %bb.0: # %entry
+; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-ON-NEXT: xvbitrevi.w $xr0, $xr0, 31
+; LA64-CONTRACT-ON-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-ON-NEXT: ret
+;
+; LA64-CONTRACT-OFF-LABEL: not_contract_xvfnmadd_s:
+; LA64-CONTRACT-OFF: # %bb.0: # %entry
+; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-OFF-NEXT: xvbitrevi.w $xr0, $xr0, 31
+; LA64-CONTRACT-OFF-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-OFF-NEXT: ret
entry:
%v0 = load <8 x float>, ptr %a0
%v1 = load <8 x float>, ptr %a1
@@ -534,32 +920,59 @@ entry:
}
define void @contract_xvfnmsub_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
-; CONTRACT-FAST-LABEL: contract_xvfnmsub_s:
-; CONTRACT-FAST: # %bb.0: # %entry
-; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-FAST-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2
-; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-FAST-NEXT: ret
-;
-; CONTRACT-ON-LABEL: contract_xvfnmsub_s:
-; CONTRACT-ON: # %bb.0: # %entry
-; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-ON-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2
-; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-ON-NEXT: ret
-;
-; CONTRACT-OFF-LABEL: contract_xvfnmsub_s:
-; CONTRACT-OFF: # %bb.0: # %entry
-; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-OFF-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2
-; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-OFF-NEXT: ret
+; LA32-CONTRACT-FAST-LABEL: contract_xvfnmsub_s:
+; LA32-CONTRACT-FAST: # %bb.0: # %entry
+; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-FAST-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-FAST-NEXT: ret
+;
+; LA32-CONTRACT-ON-LABEL: contract_xvfnmsub_s:
+; LA32-CONTRACT-ON: # %bb.0: # %entry
+; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-ON-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-ON-NEXT: ret
+;
+; LA32-CONTRACT-OFF-LABEL: contract_xvfnmsub_s:
+; LA32-CONTRACT-OFF: # %bb.0: # %entry
+; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-OFF-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-OFF-NEXT: ret
+;
+; LA64-CONTRACT-FAST-LABEL: contract_xvfnmsub_s:
+; LA64-CONTRACT-FAST: # %bb.0: # %entry
+; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-FAST-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-FAST-NEXT: ret
+;
+; LA64-CONTRACT-ON-LABEL: contract_xvfnmsub_s:
+; LA64-CONTRACT-ON: # %bb.0: # %entry
+; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-ON-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-ON-NEXT: ret
+;
+; LA64-CONTRACT-OFF-LABEL: contract_xvfnmsub_s:
+; LA64-CONTRACT-OFF: # %bb.0: # %entry
+; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-OFF-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-OFF-NEXT: ret
entry:
%v0 = load <8 x float>, ptr %a0
%v1 = load <8 x float>, ptr %a1
@@ -573,32 +986,59 @@ entry:
}
define void @contract_xvfnmsub_s_nsz(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
-; CONTRACT-FAST-LABEL: contract_xvfnmsub_s_nsz:
-; CONTRACT-FAST: # %bb.0: # %entry
-; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-FAST-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2
-; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-FAST-NEXT: ret
-;
-; CONTRACT-ON-LABEL: contract_xvfnmsub_s_nsz:
-; CONTRACT-ON: # %bb.0: # %entry
-; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-ON-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2
-; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-ON-NEXT: ret
-;
-; CONTRACT-OFF-LABEL: contract_xvfnmsub_s_nsz:
-; CONTRACT-OFF: # %bb.0: # %entry
-; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-OFF-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2
-; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-OFF-NEXT: ret
+; LA32-CONTRACT-FAST-LABEL: contract_xvfnmsub_s_nsz:
+; LA32-CONTRACT-FAST: # %bb.0: # %entry
+; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-FAST-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-FAST-NEXT: ret
+;
+; LA32-CONTRACT-ON-LABEL: contract_xvfnmsub_s_nsz:
+; LA32-CONTRACT-ON: # %bb.0: # %entry
+; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-ON-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-ON-NEXT: ret
+;
+; LA32-CONTRACT-OFF-LABEL: contract_xvfnmsub_s_nsz:
+; LA32-CONTRACT-OFF: # %bb.0: # %entry
+; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-OFF-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-OFF-NEXT: ret
+;
+; LA64-CONTRACT-FAST-LABEL: contract_xvfnmsub_s_nsz:
+; LA64-CONTRACT-FAST: # %bb.0: # %entry
+; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-FAST-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-FAST-NEXT: ret
+;
+; LA64-CONTRACT-ON-LABEL: contract_xvfnmsub_s_nsz:
+; LA64-CONTRACT-ON: # %bb.0: # %entry
+; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-ON-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-ON-NEXT: ret
+;
+; LA64-CONTRACT-OFF-LABEL: contract_xvfnmsub_s_nsz:
+; LA64-CONTRACT-OFF: # %bb.0: # %entry
+; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-OFF-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-OFF-NEXT: ret
entry:
%v0 = load <8 x float>, ptr %a0
%v1 = load <8 x float>, ptr %a1
@@ -612,35 +1052,65 @@ entry:
;; Check that fnmsub.s is not emitted.
define void @not_contract_xvfnmsub_s(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
-; CONTRACT-FAST-LABEL: not_contract_xvfnmsub_s:
-; CONTRACT-FAST: # %bb.0: # %entry
-; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-FAST-NEXT: xvbitrevi.w $xr0, $xr0, 31
-; CONTRACT-FAST-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2
-; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-FAST-NEXT: ret
-;
-; CONTRACT-ON-LABEL: not_contract_xvfnmsub_s:
-; CONTRACT-ON: # %bb.0: # %entry
-; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-ON-NEXT: xvbitrevi.w $xr0, $xr0, 31
-; CONTRACT-ON-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2
-; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-ON-NEXT: ret
-;
-; CONTRACT-OFF-LABEL: not_contract_xvfnmsub_s:
-; CONTRACT-OFF: # %bb.0: # %entry
-; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-OFF-NEXT: xvbitrevi.w $xr0, $xr0, 31
-; CONTRACT-OFF-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2
-; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-OFF-NEXT: ret
+; LA32-CONTRACT-FAST-LABEL: not_contract_xvfnmsub_s:
+; LA32-CONTRACT-FAST: # %bb.0: # %entry
+; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-FAST-NEXT: xvbitrevi.w $xr0, $xr0, 31
+; LA32-CONTRACT-FAST-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-FAST-NEXT: ret
+;
+; LA32-CONTRACT-ON-LABEL: not_contract_xvfnmsub_s:
+; LA32-CONTRACT-ON: # %bb.0: # %entry
+; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-ON-NEXT: xvbitrevi.w $xr0, $xr0, 31
+; LA32-CONTRACT-ON-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-ON-NEXT: ret
+;
+; LA32-CONTRACT-OFF-LABEL: not_contract_xvfnmsub_s:
+; LA32-CONTRACT-OFF: # %bb.0: # %entry
+; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-OFF-NEXT: xvbitrevi.w $xr0, $xr0, 31
+; LA32-CONTRACT-OFF-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-OFF-NEXT: ret
+;
+; LA64-CONTRACT-FAST-LABEL: not_contract_xvfnmsub_s:
+; LA64-CONTRACT-FAST: # %bb.0: # %entry
+; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-FAST-NEXT: xvbitrevi.w $xr0, $xr0, 31
+; LA64-CONTRACT-FAST-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-FAST-NEXT: ret
+;
+; LA64-CONTRACT-ON-LABEL: not_contract_xvfnmsub_s:
+; LA64-CONTRACT-ON: # %bb.0: # %entry
+; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-ON-NEXT: xvbitrevi.w $xr0, $xr0, 31
+; LA64-CONTRACT-ON-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-ON-NEXT: ret
+;
+; LA64-CONTRACT-OFF-LABEL: not_contract_xvfnmsub_s:
+; LA64-CONTRACT-OFF: # %bb.0: # %entry
+; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-OFF-NEXT: xvbitrevi.w $xr0, $xr0, 31
+; LA64-CONTRACT-OFF-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-OFF-NEXT: ret
entry:
%v0 = load <8 x float>, ptr %a0
%v1 = load <8 x float>, ptr %a1
@@ -653,32 +1123,59 @@ entry:
}
define void @xvfmadd_s_contract(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
-; CONTRACT-FAST-LABEL: xvfmadd_s_contract:
-; CONTRACT-FAST: # %bb.0: # %entry
-; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-FAST-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2
-; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-FAST-NEXT: ret
-;
-; CONTRACT-ON-LABEL: xvfmadd_s_contract:
-; CONTRACT-ON: # %bb.0: # %entry
-; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-ON-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2
-; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-ON-NEXT: ret
-;
-; CONTRACT-OFF-LABEL: xvfmadd_s_contract:
-; CONTRACT-OFF: # %bb.0: # %entry
-; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-OFF-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2
-; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-OFF-NEXT: ret
+; LA32-CONTRACT-FAST-LABEL: xvfmadd_s_contract:
+; LA32-CONTRACT-FAST: # %bb.0: # %entry
+; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-FAST-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-FAST-NEXT: ret
+;
+; LA32-CONTRACT-ON-LABEL: xvfmadd_s_contract:
+; LA32-CONTRACT-ON: # %bb.0: # %entry
+; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-ON-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-ON-NEXT: ret
+;
+; LA32-CONTRACT-OFF-LABEL: xvfmadd_s_contract:
+; LA32-CONTRACT-OFF: # %bb.0: # %entry
+; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-OFF-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-OFF-NEXT: ret
+;
+; LA64-CONTRACT-FAST-LABEL: xvfmadd_s_contract:
+; LA64-CONTRACT-FAST: # %bb.0: # %entry
+; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-FAST-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-FAST-NEXT: ret
+;
+; LA64-CONTRACT-ON-LABEL: xvfmadd_s_contract:
+; LA64-CONTRACT-ON: # %bb.0: # %entry
+; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-ON-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-ON-NEXT: ret
+;
+; LA64-CONTRACT-OFF-LABEL: xvfmadd_s_contract:
+; LA64-CONTRACT-OFF: # %bb.0: # %entry
+; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-OFF-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-OFF-NEXT: ret
entry:
%v0 = load <8 x float>, ptr %a0
%v1 = load <8 x float>, ptr %a1
@@ -690,32 +1187,59 @@ entry:
}
define void @xvfmsub_s_contract(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
-; CONTRACT-FAST-LABEL: xvfmsub_s_contract:
-; CONTRACT-FAST: # %bb.0: # %entry
-; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-FAST-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2
-; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-FAST-NEXT: ret
-;
-; CONTRACT-ON-LABEL: xvfmsub_s_contract:
-; CONTRACT-ON: # %bb.0: # %entry
-; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-ON-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2
-; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-ON-NEXT: ret
-;
-; CONTRACT-OFF-LABEL: xvfmsub_s_contract:
-; CONTRACT-OFF: # %bb.0: # %entry
-; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-OFF-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2
-; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-OFF-NEXT: ret
+; LA32-CONTRACT-FAST-LABEL: xvfmsub_s_contract:
+; LA32-CONTRACT-FAST: # %bb.0: # %entry
+; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-FAST-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-FAST-NEXT: ret
+;
+; LA32-CONTRACT-ON-LABEL: xvfmsub_s_contract:
+; LA32-CONTRACT-ON: # %bb.0: # %entry
+; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-ON-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-ON-NEXT: ret
+;
+; LA32-CONTRACT-OFF-LABEL: xvfmsub_s_contract:
+; LA32-CONTRACT-OFF: # %bb.0: # %entry
+; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-OFF-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-OFF-NEXT: ret
+;
+; LA64-CONTRACT-FAST-LABEL: xvfmsub_s_contract:
+; LA64-CONTRACT-FAST: # %bb.0: # %entry
+; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-FAST-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-FAST-NEXT: ret
+;
+; LA64-CONTRACT-ON-LABEL: xvfmsub_s_contract:
+; LA64-CONTRACT-ON: # %bb.0: # %entry
+; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-ON-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-ON-NEXT: ret
+;
+; LA64-CONTRACT-OFF-LABEL: xvfmsub_s_contract:
+; LA64-CONTRACT-OFF: # %bb.0: # %entry
+; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-OFF-NEXT: xvfmsub.s $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-OFF-NEXT: ret
entry:
%v0 = load <8 x float>, ptr %a0
%v1 = load <8 x float>, ptr %a1
@@ -727,32 +1251,59 @@ entry:
}
define void @xvfnmadd_s_contract(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
-; CONTRACT-FAST-LABEL: xvfnmadd_s_contract:
-; CONTRACT-FAST: # %bb.0: # %entry
-; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-FAST-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2
-; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-FAST-NEXT: ret
-;
-; CONTRACT-ON-LABEL: xvfnmadd_s_contract:
-; CONTRACT-ON: # %bb.0: # %entry
-; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-ON-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2
-; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-ON-NEXT: ret
-;
-; CONTRACT-OFF-LABEL: xvfnmadd_s_contract:
-; CONTRACT-OFF: # %bb.0: # %entry
-; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-OFF-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2
-; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-OFF-NEXT: ret
+; LA32-CONTRACT-FAST-LABEL: xvfnmadd_s_contract:
+; LA32-CONTRACT-FAST: # %bb.0: # %entry
+; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-FAST-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-FAST-NEXT: ret
+;
+; LA32-CONTRACT-ON-LABEL: xvfnmadd_s_contract:
+; LA32-CONTRACT-ON: # %bb.0: # %entry
+; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-ON-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-ON-NEXT: ret
+;
+; LA32-CONTRACT-OFF-LABEL: xvfnmadd_s_contract:
+; LA32-CONTRACT-OFF: # %bb.0: # %entry
+; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-OFF-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-OFF-NEXT: ret
+;
+; LA64-CONTRACT-FAST-LABEL: xvfnmadd_s_contract:
+; LA64-CONTRACT-FAST: # %bb.0: # %entry
+; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-FAST-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-FAST-NEXT: ret
+;
+; LA64-CONTRACT-ON-LABEL: xvfnmadd_s_contract:
+; LA64-CONTRACT-ON: # %bb.0: # %entry
+; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-ON-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-ON-NEXT: ret
+;
+; LA64-CONTRACT-OFF-LABEL: xvfnmadd_s_contract:
+; LA64-CONTRACT-OFF: # %bb.0: # %entry
+; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-OFF-NEXT: xvfnmadd.s $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-OFF-NEXT: ret
entry:
%v0 = load <8 x float>, ptr %a0
%v1 = load <8 x float>, ptr %a1
@@ -765,32 +1316,59 @@ entry:
}
define void @xvfnmsub_s_contract(ptr %res, ptr %a0, ptr %a1, ptr %a2) nounwind {
-; CONTRACT-FAST-LABEL: xvfnmsub_s_contract:
-; CONTRACT-FAST: # %bb.0: # %entry
-; CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-FAST-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2
-; CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-FAST-NEXT: ret
-;
-; CONTRACT-ON-LABEL: xvfnmsub_s_contract:
-; CONTRACT-ON: # %bb.0: # %entry
-; CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-ON-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2
-; CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-ON-NEXT: ret
-;
-; CONTRACT-OFF-LABEL: xvfnmsub_s_contract:
-; CONTRACT-OFF: # %bb.0: # %entry
-; CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
-; CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
-; CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
-; CONTRACT-OFF-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2
-; CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
-; CONTRACT-OFF-NEXT: ret
+; LA32-CONTRACT-FAST-LABEL: xvfnmsub_s_contract:
+; LA32-CONTRACT-FAST: # %bb.0: # %entry
+; LA32-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-FAST-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-FAST-NEXT: ret
+;
+; LA32-CONTRACT-ON-LABEL: xvfnmsub_s_contract:
+; LA32-CONTRACT-ON: # %bb.0: # %entry
+; LA32-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-ON-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-ON-NEXT: ret
+;
+; LA32-CONTRACT-OFF-LABEL: xvfnmsub_s_contract:
+; LA32-CONTRACT-OFF: # %bb.0: # %entry
+; LA32-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA32-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA32-CONTRACT-OFF-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2
+; LA32-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA32-CONTRACT-OFF-NEXT: ret
+;
+; LA64-CONTRACT-FAST-LABEL: xvfnmsub_s_contract:
+; LA64-CONTRACT-FAST: # %bb.0: # %entry
+; LA64-CONTRACT-FAST-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-FAST-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-FAST-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-FAST-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-FAST-NEXT: ret
+;
+; LA64-CONTRACT-ON-LABEL: xvfnmsub_s_contract:
+; LA64-CONTRACT-ON: # %bb.0: # %entry
+; LA64-CONTRACT-ON-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-ON-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-ON-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-ON-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-ON-NEXT: ret
+;
+; LA64-CONTRACT-OFF-LABEL: xvfnmsub_s_contract:
+; LA64-CONTRACT-OFF: # %bb.0: # %entry
+; LA64-CONTRACT-OFF-NEXT: xvld $xr0, $a1, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr1, $a2, 0
+; LA64-CONTRACT-OFF-NEXT: xvld $xr2, $a3, 0
+; LA64-CONTRACT-OFF-NEXT: xvfnmsub.s $xr0, $xr0, $xr1, $xr2
+; LA64-CONTRACT-OFF-NEXT: xvst $xr0, $a0, 0
+; LA64-CONTRACT-OFF-NEXT: ret
entry:
%v0 = load <8 x float>, ptr %a0
%v1 = load <8 x float>, ptr %a1
diff --git a/llvm/test/CodeGen/LoongArch/lasx/fsqrt-reciprocal-estimate.ll b/llvm/test/CodeGen/LoongArch/lasx/fsqrt-reciprocal-estimate.ll
index 48fd12697417a..4e475daa8ced3 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/fsqrt-reciprocal-estimate.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/fsqrt-reciprocal-estimate.ll
@@ -1,31 +1,114 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc --mtriple=loongarch64 --mattr=+lasx,-frecipe < %s | FileCheck %s --check-prefix=FAULT
-; RUN: llc --mtriple=loongarch64 --mattr=+lasx,+frecipe < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx,-frecipe < %s | FileCheck %s --check-prefix=FAULT-LA32
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx,+frecipe < %s | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx,-frecipe < %s | FileCheck %s --check-prefix=FAULT-LA64
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx,+frecipe < %s | FileCheck %s --check-prefix=LA64
;; 1.0 / (fsqrt vec)
define void @one_div_sqrt_v8f32(ptr %res, ptr %a0) nounwind {
-; FAULT-LABEL: one_div_sqrt_v8f32:
-; FAULT: # %bb.0: # %entry
-; FAULT-NEXT: xvld $xr0, $a1, 0
-; FAULT-NEXT: xvfrsqrt.s $xr0, $xr0
-; FAULT-NEXT: xvst $xr0, $a0, 0
-; FAULT-NEXT: ret
+; FAULT-LA32-LABEL: one_div_sqrt_v8f32:
+; FAULT-LA32: # %bb.0: # %entry
+; FAULT-LA32-NEXT: addi.w $sp, $sp, -128
+; FAULT-LA32-NEXT: st.w $ra, $sp, 124 # 4-byte Folded Spill
+; FAULT-LA32-NEXT: st.w $fp, $sp, 120 # 4-byte Folded Spill
+; FAULT-LA32-NEXT: addi.w $fp, $sp, 128
+; FAULT-LA32-NEXT: bstrins.w $sp, $zero, 4, 0
+; FAULT-LA32-NEXT: vld $vr0, $a1, 16
+; FAULT-LA32-NEXT: vst $vr0, $sp, 48
+; FAULT-LA32-NEXT: ld.w $a2, $a1, 12
+; FAULT-LA32-NEXT: st.w $a2, $sp, 44
+; FAULT-LA32-NEXT: ld.w $a2, $a1, 8
+; FAULT-LA32-NEXT: st.w $a2, $sp, 40
+; FAULT-LA32-NEXT: ld.w $a2, $a1, 4
+; FAULT-LA32-NEXT: st.w $a2, $sp, 36
+; FAULT-LA32-NEXT: ld.w $a1, $a1, 0
+; FAULT-LA32-NEXT: st.w $a1, $sp, 32
+; FAULT-LA32-NEXT: xvld $xr0, $sp, 32
+; FAULT-LA32-NEXT: xvfrsqrt.s $xr0, $xr0
+; FAULT-LA32-NEXT: xvst $xr0, $sp, 64
+; FAULT-LA32-NEXT: vld $vr0, $sp, 80
+; FAULT-LA32-NEXT: vst $vr0, $a0, 16
+; FAULT-LA32-NEXT: ld.w $a1, $sp, 76
+; FAULT-LA32-NEXT: st.w $a1, $a0, 12
+; FAULT-LA32-NEXT: ld.w $a1, $sp, 72
+; FAULT-LA32-NEXT: st.w $a1, $a0, 8
+; FAULT-LA32-NEXT: ld.w $a1, $sp, 68
+; FAULT-LA32-NEXT: st.w $a1, $a0, 4
+; FAULT-LA32-NEXT: ld.w $a1, $sp, 64
+; FAULT-LA32-NEXT: st.w $a1, $a0, 0
+; FAULT-LA32-NEXT: addi.w $sp, $fp, -128
+; FAULT-LA32-NEXT: ld.w $fp, $sp, 120 # 4-byte Folded Reload
+; FAULT-LA32-NEXT: ld.w $ra, $sp, 124 # 4-byte Folded Reload
+; FAULT-LA32-NEXT: addi.w $sp, $sp, 128
+; FAULT-LA32-NEXT: ret
;
-; CHECK-LABEL: one_div_sqrt_v8f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xvld $xr0, $a1, 0
-; CHECK-NEXT: xvfrsqrte.s $xr1, $xr0
-; CHECK-NEXT: xvfmul.s $xr1, $xr0, $xr1
-; CHECK-NEXT: xvfmul.s $xr0, $xr0, $xr1
-; CHECK-NEXT: lu12i.w $a1, -261120
-; CHECK-NEXT: xvreplgr2vr.w $xr2, $a1
-; CHECK-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2
-; CHECK-NEXT: lu12i.w $a1, -266240
-; CHECK-NEXT: xvreplgr2vr.w $xr2, $a1
-; CHECK-NEXT: xvfmul.s $xr1, $xr1, $xr2
-; CHECK-NEXT: xvfmul.s $xr0, $xr1, $xr0
-; CHECK-NEXT: xvst $xr0, $a0, 0
-; CHECK-NEXT: ret
+; LA32-LABEL: one_div_sqrt_v8f32:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: addi.w $sp, $sp, -128
+; LA32-NEXT: st.w $ra, $sp, 124 # 4-byte Folded Spill
+; LA32-NEXT: st.w $fp, $sp, 120 # 4-byte Folded Spill
+; LA32-NEXT: addi.w $fp, $sp, 128
+; LA32-NEXT: bstrins.w $sp, $zero, 4, 0
+; LA32-NEXT: vld $vr0, $a1, 16
+; LA32-NEXT: vst $vr0, $sp, 48
+; LA32-NEXT: ld.w $a2, $a1, 12
+; LA32-NEXT: st.w $a2, $sp, 44
+; LA32-NEXT: ld.w $a2, $a1, 8
+; LA32-NEXT: st.w $a2, $sp, 40
+; LA32-NEXT: ld.w $a2, $a1, 4
+; LA32-NEXT: st.w $a2, $sp, 36
+; LA32-NEXT: ld.w $a1, $a1, 0
+; LA32-NEXT: st.w $a1, $sp, 32
+; LA32-NEXT: xvld $xr0, $sp, 32
+; LA32-NEXT: xvfrsqrte.s $xr1, $xr0
+; LA32-NEXT: xvfmul.s $xr1, $xr0, $xr1
+; LA32-NEXT: xvfmul.s $xr0, $xr0, $xr1
+; LA32-NEXT: lu12i.w $a1, -261120
+; LA32-NEXT: xvreplgr2vr.w $xr2, $a1
+; LA32-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2
+; LA32-NEXT: lu12i.w $a1, -266240
+; LA32-NEXT: xvreplgr2vr.w $xr2, $a1
+; LA32-NEXT: xvfmul.s $xr1, $xr1, $xr2
+; LA32-NEXT: xvfmul.s $xr0, $xr1, $xr0
+; LA32-NEXT: xvst $xr0, $sp, 64
+; LA32-NEXT: vld $vr0, $sp, 80
+; LA32-NEXT: vst $vr0, $a0, 16
+; LA32-NEXT: ld.w $a1, $sp, 76
+; LA32-NEXT: st.w $a1, $a0, 12
+; LA32-NEXT: ld.w $a1, $sp, 72
+; LA32-NEXT: st.w $a1, $a0, 8
+; LA32-NEXT: ld.w $a1, $sp, 68
+; LA32-NEXT: st.w $a1, $a0, 4
+; LA32-NEXT: ld.w $a1, $sp, 64
+; LA32-NEXT: st.w $a1, $a0, 0
+; LA32-NEXT: addi.w $sp, $fp, -128
+; LA32-NEXT: ld.w $fp, $sp, 120 # 4-byte Folded Reload
+; LA32-NEXT: ld.w $ra, $sp, 124 # 4-byte Folded Reload
+; LA32-NEXT: addi.w $sp, $sp, 128
+; LA32-NEXT: ret
+;
+; FAULT-LA64-LABEL: one_div_sqrt_v8f32:
+; FAULT-LA64: # %bb.0: # %entry
+; FAULT-LA64-NEXT: xvld $xr0, $a1, 0
+; FAULT-LA64-NEXT: xvfrsqrt.s $xr0, $xr0
+; FAULT-LA64-NEXT: xvst $xr0, $a0, 0
+; FAULT-LA64-NEXT: ret
+;
+; LA64-LABEL: one_div_sqrt_v8f32:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: xvld $xr0, $a1, 0
+; LA64-NEXT: xvfrsqrte.s $xr1, $xr0
+; LA64-NEXT: xvfmul.s $xr1, $xr0, $xr1
+; LA64-NEXT: xvfmul.s $xr0, $xr0, $xr1
+; LA64-NEXT: lu12i.w $a1, -261120
+; LA64-NEXT: xvreplgr2vr.w $xr2, $a1
+; LA64-NEXT: xvfmadd.s $xr0, $xr0, $xr1, $xr2
+; LA64-NEXT: lu12i.w $a1, -266240
+; LA64-NEXT: xvreplgr2vr.w $xr2, $a1
+; LA64-NEXT: xvfmul.s $xr1, $xr1, $xr2
+; LA64-NEXT: xvfmul.s $xr0, $xr1, $xr0
+; LA64-NEXT: xvst $xr0, $a0, 0
+; LA64-NEXT: ret
entry:
%v0 = load <8 x float>, ptr %a0, align 16
%sqrt = call fast <8 x float> @llvm.sqrt.v8f32 (<8 x float> %v0)
@@ -35,34 +118,122 @@ entry:
}
define void @one_div_sqrt_v4f64(ptr %res, ptr %a0) nounwind {
-; FAULT-LABEL: one_div_sqrt_v4f64:
-; FAULT: # %bb.0: # %entry
-; FAULT-NEXT: xvld $xr0, $a1, 0
-; FAULT-NEXT: xvfrsqrt.d $xr0, $xr0
-; FAULT-NEXT: xvst $xr0, $a0, 0
-; FAULT-NEXT: ret
+; FAULT-LA32-LABEL: one_div_sqrt_v4f64:
+; FAULT-LA32: # %bb.0: # %entry
+; FAULT-LA32-NEXT: addi.w $sp, $sp, -128
+; FAULT-LA32-NEXT: st.w $ra, $sp, 124 # 4-byte Folded Spill
+; FAULT-LA32-NEXT: st.w $fp, $sp, 120 # 4-byte Folded Spill
+; FAULT-LA32-NEXT: addi.w $fp, $sp, 128
+; FAULT-LA32-NEXT: bstrins.w $sp, $zero, 4, 0
+; FAULT-LA32-NEXT: vld $vr0, $a1, 16
+; FAULT-LA32-NEXT: vst $vr0, $sp, 48
+; FAULT-LA32-NEXT: ld.w $a2, $a1, 12
+; FAULT-LA32-NEXT: st.w $a2, $sp, 44
+; FAULT-LA32-NEXT: ld.w $a2, $a1, 8
+; FAULT-LA32-NEXT: st.w $a2, $sp, 40
+; FAULT-LA32-NEXT: ld.w $a2, $a1, 4
+; FAULT-LA32-NEXT: st.w $a2, $sp, 36
+; FAULT-LA32-NEXT: ld.w $a1, $a1, 0
+; FAULT-LA32-NEXT: st.w $a1, $sp, 32
+; FAULT-LA32-NEXT: xvld $xr0, $sp, 32
+; FAULT-LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI1_0)
+; FAULT-LA32-NEXT: xvld $xr1, $a1, %pc_lo12(.LCPI1_0)
+; FAULT-LA32-NEXT: xvfsqrt.d $xr0, $xr0
+; FAULT-LA32-NEXT: xvfdiv.d $xr0, $xr1, $xr0
+; FAULT-LA32-NEXT: xvst $xr0, $sp, 64
+; FAULT-LA32-NEXT: vld $vr0, $sp, 80
+; FAULT-LA32-NEXT: vst $vr0, $a0, 16
+; FAULT-LA32-NEXT: ld.w $a1, $sp, 76
+; FAULT-LA32-NEXT: st.w $a1, $a0, 12
+; FAULT-LA32-NEXT: ld.w $a1, $sp, 72
+; FAULT-LA32-NEXT: st.w $a1, $a0, 8
+; FAULT-LA32-NEXT: ld.w $a1, $sp, 68
+; FAULT-LA32-NEXT: st.w $a1, $a0, 4
+; FAULT-LA32-NEXT: ld.w $a1, $sp, 64
+; FAULT-LA32-NEXT: st.w $a1, $a0, 0
+; FAULT-LA32-NEXT: addi.w $sp, $fp, -128
+; FAULT-LA32-NEXT: ld.w $fp, $sp, 120 # 4-byte Folded Reload
+; FAULT-LA32-NEXT: ld.w $ra, $sp, 124 # 4-byte Folded Reload
+; FAULT-LA32-NEXT: addi.w $sp, $sp, 128
+; FAULT-LA32-NEXT: ret
+;
+; LA32-LABEL: one_div_sqrt_v4f64:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: addi.w $sp, $sp, -128
+; LA32-NEXT: st.w $ra, $sp, 124 # 4-byte Folded Spill
+; LA32-NEXT: st.w $fp, $sp, 120 # 4-byte Folded Spill
+; LA32-NEXT: addi.w $fp, $sp, 128
+; LA32-NEXT: bstrins.w $sp, $zero, 4, 0
+; LA32-NEXT: vld $vr0, $a1, 16
+; LA32-NEXT: vst $vr0, $sp, 48
+; LA32-NEXT: ld.w $a2, $a1, 12
+; LA32-NEXT: st.w $a2, $sp, 44
+; LA32-NEXT: ld.w $a2, $a1, 8
+; LA32-NEXT: st.w $a2, $sp, 40
+; LA32-NEXT: ld.w $a2, $a1, 4
+; LA32-NEXT: st.w $a2, $sp, 36
+; LA32-NEXT: ld.w $a1, $a1, 0
+; LA32-NEXT: st.w $a1, $sp, 32
+; LA32-NEXT: xvld $xr0, $sp, 32
+; LA32-NEXT: xvfrsqrte.d $xr1, $xr0
+; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI1_0)
+; LA32-NEXT: xvld $xr2, $a1, %pc_lo12(.LCPI1_0)
+; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI1_1)
+; LA32-NEXT: xvld $xr3, $a1, %pc_lo12(.LCPI1_1)
+; LA32-NEXT: xvfmul.d $xr1, $xr0, $xr1
+; LA32-NEXT: xvfmul.d $xr4, $xr0, $xr1
+; LA32-NEXT: xvfmadd.d $xr4, $xr4, $xr1, $xr2
+; LA32-NEXT: xvfmul.d $xr1, $xr1, $xr3
+; LA32-NEXT: xvfmul.d $xr1, $xr1, $xr4
+; LA32-NEXT: xvfmul.d $xr0, $xr0, $xr1
+; LA32-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr2
+; LA32-NEXT: xvfmul.d $xr1, $xr1, $xr3
+; LA32-NEXT: xvfmul.d $xr0, $xr1, $xr0
+; LA32-NEXT: xvst $xr0, $sp, 64
+; LA32-NEXT: vld $vr0, $sp, 80
+; LA32-NEXT: vst $vr0, $a0, 16
+; LA32-NEXT: ld.w $a1, $sp, 76
+; LA32-NEXT: st.w $a1, $a0, 12
+; LA32-NEXT: ld.w $a1, $sp, 72
+; LA32-NEXT: st.w $a1, $a0, 8
+; LA32-NEXT: ld.w $a1, $sp, 68
+; LA32-NEXT: st.w $a1, $a0, 4
+; LA32-NEXT: ld.w $a1, $sp, 64
+; LA32-NEXT: st.w $a1, $a0, 0
+; LA32-NEXT: addi.w $sp, $fp, -128
+; LA32-NEXT: ld.w $fp, $sp, 120 # 4-byte Folded Reload
+; LA32-NEXT: ld.w $ra, $sp, 124 # 4-byte Folded Reload
+; LA32-NEXT: addi.w $sp, $sp, 128
+; LA32-NEXT: ret
+;
+; FAULT-LA64-LABEL: one_div_sqrt_v4f64:
+; FAULT-LA64: # %bb.0: # %entry
+; FAULT-LA64-NEXT: xvld $xr0, $a1, 0
+; FAULT-LA64-NEXT: xvfrsqrt.d $xr0, $xr0
+; FAULT-LA64-NEXT: xvst $xr0, $a0, 0
+; FAULT-LA64-NEXT: ret
;
-; CHECK-LABEL: one_div_sqrt_v4f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xvld $xr0, $a1, 0
-; CHECK-NEXT: xvfrsqrte.d $xr1, $xr0
-; CHECK-NEXT: xvfmul.d $xr1, $xr0, $xr1
-; CHECK-NEXT: xvfmul.d $xr2, $xr0, $xr1
-; CHECK-NEXT: ori $a1, $zero, 0
-; CHECK-NEXT: lu32i.d $a1, -524288
-; CHECK-NEXT: lu52i.d $a1, $a1, -1024
-; CHECK-NEXT: xvreplgr2vr.d $xr3, $a1
-; CHECK-NEXT: xvfmadd.d $xr2, $xr2, $xr1, $xr3
-; CHECK-NEXT: lu52i.d $a1, $zero, -1026
-; CHECK-NEXT: xvreplgr2vr.d $xr4, $a1
-; CHECK-NEXT: xvfmul.d $xr1, $xr1, $xr4
-; CHECK-NEXT: xvfmul.d $xr1, $xr1, $xr2
-; CHECK-NEXT: xvfmul.d $xr0, $xr0, $xr1
-; CHECK-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr3
-; CHECK-NEXT: xvfmul.d $xr1, $xr1, $xr4
-; CHECK-NEXT: xvfmul.d $xr0, $xr1, $xr0
-; CHECK-NEXT: xvst $xr0, $a0, 0
-; CHECK-NEXT: ret
+; LA64-LABEL: one_div_sqrt_v4f64:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: xvld $xr0, $a1, 0
+; LA64-NEXT: xvfrsqrte.d $xr1, $xr0
+; LA64-NEXT: xvfmul.d $xr1, $xr0, $xr1
+; LA64-NEXT: xvfmul.d $xr2, $xr0, $xr1
+; LA64-NEXT: ori $a1, $zero, 0
+; LA64-NEXT: lu32i.d $a1, -524288
+; LA64-NEXT: lu52i.d $a1, $a1, -1024
+; LA64-NEXT: xvreplgr2vr.d $xr3, $a1
+; LA64-NEXT: xvfmadd.d $xr2, $xr2, $xr1, $xr3
+; LA64-NEXT: lu52i.d $a1, $zero, -1026
+; LA64-NEXT: xvreplgr2vr.d $xr4, $a1
+; LA64-NEXT: xvfmul.d $xr1, $xr1, $xr4
+; LA64-NEXT: xvfmul.d $xr1, $xr1, $xr2
+; LA64-NEXT: xvfmul.d $xr0, $xr0, $xr1
+; LA64-NEXT: xvfmadd.d $xr0, $xr0, $xr1, $xr3
+; LA64-NEXT: xvfmul.d $xr1, $xr1, $xr4
+; LA64-NEXT: xvfmul.d $xr0, $xr1, $xr0
+; LA64-NEXT: xvst $xr0, $a0, 0
+; LA64-NEXT: ret
entry:
%v0 = load <4 x double>, ptr %a0, align 16
%sqrt = call fast <4 x double> @llvm.sqrt.v4f64 (<4 x double> %v0)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/fsqrt.ll b/llvm/test/CodeGen/LoongArch/lasx/fsqrt.ll
index c4a881bdeae9f..f8a3284f04dc8 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/fsqrt.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/fsqrt.ll
@@ -1,14 +1,51 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefix=LA64
;; fsqrt
define void @sqrt_v8f32(ptr %res, ptr %a0) nounwind {
-; CHECK-LABEL: sqrt_v8f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xvld $xr0, $a1, 0
-; CHECK-NEXT: xvfsqrt.s $xr0, $xr0
-; CHECK-NEXT: xvst $xr0, $a0, 0
-; CHECK-NEXT: ret
+; LA32-LABEL: sqrt_v8f32:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: addi.w $sp, $sp, -128
+; LA32-NEXT: st.w $ra, $sp, 124 # 4-byte Folded Spill
+; LA32-NEXT: st.w $fp, $sp, 120 # 4-byte Folded Spill
+; LA32-NEXT: addi.w $fp, $sp, 128
+; LA32-NEXT: bstrins.w $sp, $zero, 4, 0
+; LA32-NEXT: vld $vr0, $a1, 16
+; LA32-NEXT: vst $vr0, $sp, 48
+; LA32-NEXT: ld.w $a2, $a1, 12
+; LA32-NEXT: st.w $a2, $sp, 44
+; LA32-NEXT: ld.w $a2, $a1, 8
+; LA32-NEXT: st.w $a2, $sp, 40
+; LA32-NEXT: ld.w $a2, $a1, 4
+; LA32-NEXT: st.w $a2, $sp, 36
+; LA32-NEXT: ld.w $a1, $a1, 0
+; LA32-NEXT: st.w $a1, $sp, 32
+; LA32-NEXT: xvld $xr0, $sp, 32
+; LA32-NEXT: xvfsqrt.s $xr0, $xr0
+; LA32-NEXT: xvst $xr0, $sp, 64
+; LA32-NEXT: vld $vr0, $sp, 80
+; LA32-NEXT: vst $vr0, $a0, 16
+; LA32-NEXT: ld.w $a1, $sp, 76
+; LA32-NEXT: st.w $a1, $a0, 12
+; LA32-NEXT: ld.w $a1, $sp, 72
+; LA32-NEXT: st.w $a1, $a0, 8
+; LA32-NEXT: ld.w $a1, $sp, 68
+; LA32-NEXT: st.w $a1, $a0, 4
+; LA32-NEXT: ld.w $a1, $sp, 64
+; LA32-NEXT: st.w $a1, $a0, 0
+; LA32-NEXT: addi.w $sp, $fp, -128
+; LA32-NEXT: ld.w $fp, $sp, 120 # 4-byte Folded Reload
+; LA32-NEXT: ld.w $ra, $sp, 124 # 4-byte Folded Reload
+; LA32-NEXT: addi.w $sp, $sp, 128
+; LA32-NEXT: ret
+;
+; LA64-LABEL: sqrt_v8f32:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: xvld $xr0, $a1, 0
+; LA64-NEXT: xvfsqrt.s $xr0, $xr0
+; LA64-NEXT: xvst $xr0, $a0, 0
+; LA64-NEXT: ret
entry:
%v0 = load <8 x float>, ptr %a0, align 16
%sqrt = call <8 x float> @llvm.sqrt.v8f32 (<8 x float> %v0)
@@ -17,12 +54,48 @@ entry:
}
define void @sqrt_v4f64(ptr %res, ptr %a0) nounwind {
-; CHECK-LABEL: sqrt_v4f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xvld $xr0, $a1, 0
-; CHECK-NEXT: xvfsqrt.d $xr0, $xr0
-; CHECK-NEXT: xvst $xr0, $a0, 0
-; CHECK-NEXT: ret
+; LA32-LABEL: sqrt_v4f64:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: addi.w $sp, $sp, -128
+; LA32-NEXT: st.w $ra, $sp, 124 # 4-byte Folded Spill
+; LA32-NEXT: st.w $fp, $sp, 120 # 4-byte Folded Spill
+; LA32-NEXT: addi.w $fp, $sp, 128
+; LA32-NEXT: bstrins.w $sp, $zero, 4, 0
+; LA32-NEXT: vld $vr0, $a1, 16
+; LA32-NEXT: vst $vr0, $sp, 48
+; LA32-NEXT: ld.w $a2, $a1, 12
+; LA32-NEXT: st.w $a2, $sp, 44
+; LA32-NEXT: ld.w $a2, $a1, 8
+; LA32-NEXT: st.w $a2, $sp, 40
+; LA32-NEXT: ld.w $a2, $a1, 4
+; LA32-NEXT: st.w $a2, $sp, 36
+; LA32-NEXT: ld.w $a1, $a1, 0
+; LA32-NEXT: st.w $a1, $sp, 32
+; LA32-NEXT: xvld $xr0, $sp, 32
+; LA32-NEXT: xvfsqrt.d $xr0, $xr0
+; LA32-NEXT: xvst $xr0, $sp, 64
+; LA32-NEXT: vld $vr0, $sp, 80
+; LA32-NEXT: vst $vr0, $a0, 16
+; LA32-NEXT: ld.w $a1, $sp, 76
+; LA32-NEXT: st.w $a1, $a0, 12
+; LA32-NEXT: ld.w $a1, $sp, 72
+; LA32-NEXT: st.w $a1, $a0, 8
+; LA32-NEXT: ld.w $a1, $sp, 68
+; LA32-NEXT: st.w $a1, $a0, 4
+; LA32-NEXT: ld.w $a1, $sp, 64
+; LA32-NEXT: st.w $a1, $a0, 0
+; LA32-NEXT: addi.w $sp, $fp, -128
+; LA32-NEXT: ld.w $fp, $sp, 120 # 4-byte Folded Reload
+; LA32-NEXT: ld.w $ra, $sp, 124 # 4-byte Folded Reload
+; LA32-NEXT: addi.w $sp, $sp, 128
+; LA32-NEXT: ret
+;
+; LA64-LABEL: sqrt_v4f64:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: xvld $xr0, $a1, 0
+; LA64-NEXT: xvfsqrt.d $xr0, $xr0
+; LA64-NEXT: xvst $xr0, $a0, 0
+; LA64-NEXT: ret
entry:
%v0 = load <4 x double>, ptr %a0, align 16
%sqrt = call <4 x double> @llvm.sqrt.v4f64 (<4 x double> %v0)
@@ -32,12 +105,48 @@ entry:
;; 1.0 / (fsqrt vec)
define void @one_div_sqrt_v8f32(ptr %res, ptr %a0) nounwind {
-; CHECK-LABEL: one_div_sqrt_v8f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xvld $xr0, $a1, 0
-; CHECK-NEXT: xvfrsqrt.s $xr0, $xr0
-; CHECK-NEXT: xvst $xr0, $a0, 0
-; CHECK-NEXT: ret
+; LA32-LABEL: one_div_sqrt_v8f32:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: addi.w $sp, $sp, -128
+; LA32-NEXT: st.w $ra, $sp, 124 # 4-byte Folded Spill
+; LA32-NEXT: st.w $fp, $sp, 120 # 4-byte Folded Spill
+; LA32-NEXT: addi.w $fp, $sp, 128
+; LA32-NEXT: bstrins.w $sp, $zero, 4, 0
+; LA32-NEXT: vld $vr0, $a1, 16
+; LA32-NEXT: vst $vr0, $sp, 48
+; LA32-NEXT: ld.w $a2, $a1, 12
+; LA32-NEXT: st.w $a2, $sp, 44
+; LA32-NEXT: ld.w $a2, $a1, 8
+; LA32-NEXT: st.w $a2, $sp, 40
+; LA32-NEXT: ld.w $a2, $a1, 4
+; LA32-NEXT: st.w $a2, $sp, 36
+; LA32-NEXT: ld.w $a1, $a1, 0
+; LA32-NEXT: st.w $a1, $sp, 32
+; LA32-NEXT: xvld $xr0, $sp, 32
+; LA32-NEXT: xvfrsqrt.s $xr0, $xr0
+; LA32-NEXT: xvst $xr0, $sp, 64
+; LA32-NEXT: vld $vr0, $sp, 80
+; LA32-NEXT: vst $vr0, $a0, 16
+; LA32-NEXT: ld.w $a1, $sp, 76
+; LA32-NEXT: st.w $a1, $a0, 12
+; LA32-NEXT: ld.w $a1, $sp, 72
+; LA32-NEXT: st.w $a1, $a0, 8
+; LA32-NEXT: ld.w $a1, $sp, 68
+; LA32-NEXT: st.w $a1, $a0, 4
+; LA32-NEXT: ld.w $a1, $sp, 64
+; LA32-NEXT: st.w $a1, $a0, 0
+; LA32-NEXT: addi.w $sp, $fp, -128
+; LA32-NEXT: ld.w $fp, $sp, 120 # 4-byte Folded Reload
+; LA32-NEXT: ld.w $ra, $sp, 124 # 4-byte Folded Reload
+; LA32-NEXT: addi.w $sp, $sp, 128
+; LA32-NEXT: ret
+;
+; LA64-LABEL: one_div_sqrt_v8f32:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: xvld $xr0, $a1, 0
+; LA64-NEXT: xvfrsqrt.s $xr0, $xr0
+; LA64-NEXT: xvst $xr0, $a0, 0
+; LA64-NEXT: ret
entry:
%v0 = load <8 x float>, ptr %a0, align 16
%sqrt = call <8 x float> @llvm.sqrt.v8f32 (<8 x float> %v0)
@@ -47,12 +156,51 @@ entry:
}
define void @one_div_sqrt_v4f64(ptr %res, ptr %a0) nounwind {
-; CHECK-LABEL: one_div_sqrt_v4f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xvld $xr0, $a1, 0
-; CHECK-NEXT: xvfrsqrt.d $xr0, $xr0
-; CHECK-NEXT: xvst $xr0, $a0, 0
-; CHECK-NEXT: ret
+; LA32-LABEL: one_div_sqrt_v4f64:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: addi.w $sp, $sp, -128
+; LA32-NEXT: st.w $ra, $sp, 124 # 4-byte Folded Spill
+; LA32-NEXT: st.w $fp, $sp, 120 # 4-byte Folded Spill
+; LA32-NEXT: addi.w $fp, $sp, 128
+; LA32-NEXT: bstrins.w $sp, $zero, 4, 0
+; LA32-NEXT: vld $vr0, $a1, 16
+; LA32-NEXT: vst $vr0, $sp, 48
+; LA32-NEXT: ld.w $a2, $a1, 12
+; LA32-NEXT: st.w $a2, $sp, 44
+; LA32-NEXT: ld.w $a2, $a1, 8
+; LA32-NEXT: st.w $a2, $sp, 40
+; LA32-NEXT: ld.w $a2, $a1, 4
+; LA32-NEXT: st.w $a2, $sp, 36
+; LA32-NEXT: ld.w $a1, $a1, 0
+; LA32-NEXT: st.w $a1, $sp, 32
+; LA32-NEXT: xvld $xr0, $sp, 32
+; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI3_0)
+; LA32-NEXT: xvld $xr1, $a1, %pc_lo12(.LCPI3_0)
+; LA32-NEXT: xvfsqrt.d $xr0, $xr0
+; LA32-NEXT: xvfdiv.d $xr0, $xr1, $xr0
+; LA32-NEXT: xvst $xr0, $sp, 64
+; LA32-NEXT: vld $vr0, $sp, 80
+; LA32-NEXT: vst $vr0, $a0, 16
+; LA32-NEXT: ld.w $a1, $sp, 76
+; LA32-NEXT: st.w $a1, $a0, 12
+; LA32-NEXT: ld.w $a1, $sp, 72
+; LA32-NEXT: st.w $a1, $a0, 8
+; LA32-NEXT: ld.w $a1, $sp, 68
+; LA32-NEXT: st.w $a1, $a0, 4
+; LA32-NEXT: ld.w $a1, $sp, 64
+; LA32-NEXT: st.w $a1, $a0, 0
+; LA32-NEXT: addi.w $sp, $fp, -128
+; LA32-NEXT: ld.w $fp, $sp, 120 # 4-byte Folded Reload
+; LA32-NEXT: ld.w $ra, $sp, 124 # 4-byte Folded Reload
+; LA32-NEXT: addi.w $sp, $sp, 128
+; LA32-NEXT: ret
+;
+; LA64-LABEL: one_div_sqrt_v4f64:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: xvld $xr0, $a1, 0
+; LA64-NEXT: xvfrsqrt.d $xr0, $xr0
+; LA64-NEXT: xvst $xr0, $a0, 0
+; LA64-NEXT: ret
entry:
%v0 = load <4 x double>, ptr %a0, align 16
%sqrt = call <4 x double> @llvm.sqrt.v4f64 (<4 x double> %v0)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/inline-asm-operand-modifier.ll b/llvm/test/CodeGen/LoongArch/lasx/inline-asm-operand-modifier.ll
index 8b25a6525381b..1e60b389bb238 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/inline-asm-operand-modifier.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/inline-asm-operand-modifier.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
define void @test_u() nounwind {
diff --git a/llvm/test/CodeGen/LoongArch/lasx/inline-asm-reg-names.ll b/llvm/test/CodeGen/LoongArch/lasx/inline-asm-reg-names.ll
index dd400ecfcf91d..1289892b2c03d 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/inline-asm-reg-names.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/inline-asm-reg-names.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA64
define void @register_xr1() nounwind {
; CHECK-LABEL: register_xr1:
@@ -42,16 +43,27 @@ entry:
;; is a callee-saved register which is preserved across calls.
;; That's why the fst.d and fld.d instructions are emitted.
define void @register_xr31() nounwind {
-; CHECK-LABEL: register_xr31:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi.d $sp, $sp, -16
-; CHECK-NEXT: fst.d $fs7, $sp, 8 # 8-byte Folded Spill
-; CHECK-NEXT: #APP
-; CHECK-NEXT: xvldi $xr31, 1
-; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: fld.d $fs7, $sp, 8 # 8-byte Folded Reload
-; CHECK-NEXT: addi.d $sp, $sp, 16
-; CHECK-NEXT: ret
+; LA32-LABEL: register_xr31:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: addi.w $sp, $sp, -16
+; LA32-NEXT: fst.d $fs7, $sp, 8 # 8-byte Folded Spill
+; LA32-NEXT: #APP
+; LA32-NEXT: xvldi $xr31, 1
+; LA32-NEXT: #NO_APP
+; LA32-NEXT: fld.d $fs7, $sp, 8 # 8-byte Folded Reload
+; LA32-NEXT: addi.w $sp, $sp, 16
+; LA32-NEXT: ret
+;
+; LA64-LABEL: register_xr31:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: addi.d $sp, $sp, -16
+; LA64-NEXT: fst.d $fs7, $sp, 8 # 8-byte Folded Spill
+; LA64-NEXT: #APP
+; LA64-NEXT: xvldi $xr31, 1
+; LA64-NEXT: #NO_APP
+; LA64-NEXT: fld.d $fs7, $sp, 8 # 8-byte Folded Reload
+; LA64-NEXT: addi.d $sp, $sp, 16
+; LA64-NEXT: ret
entry:
%0 = tail call <4 x i64> asm sideeffect "xvldi ${0:u}, 1", "={$xr31}"()
ret void
diff --git a/llvm/test/CodeGen/LoongArch/lasx/insert-extract-subvector.ll b/llvm/test/CodeGen/LoongArch/lasx/insert-extract-subvector.ll
index 7a90afca376db..48d6e0130105e 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/insert-extract-subvector.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/insert-extract-subvector.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <8 x i32> @llvm.experimental.vector.insert.v8i32.v4i32(<8 x i32>, <4 x i32>, i64)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-absd.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-absd.ll
index bf54f44357b03..09c4161728bdd 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-absd.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-absd.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvabsd.b(<32 x i8>, <32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-add.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-add.ll
index 0c2f2ace29fc9..2eac147a860c5 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-add.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-add.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvadd.b(<32 x i8>, <32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-adda.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-adda.ll
index c1258d53e913e..0f5bdad6c7776 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-adda.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-adda.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvadda.b(<32 x i8>, <32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-addi-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-addi-invalid-imm.ll
index 4998847f09100..8855a8a6cc1be 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-addi-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-addi-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvaddi.bu(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-addi-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-addi-non-imm.ll
index f25f0e61a28e1..cb7ae06a5f56f 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-addi-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-addi-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvaddi.bu(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-addi.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-addi.ll
index 09b5d07a0151c..fb39220b27c73 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-addi.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-addi.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvaddi.bu(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-addw.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-addw.ll
index ef7a1b5a50efb..7f6fc9c4dbc1c 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-addw.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-addw.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <16 x i16> @llvm.loongarch.lasx.xvaddwev.h.b(<32 x i8>, <32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-and.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-and.ll
index 15f3a8094770b..e726657bd6294 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-and.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-and.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvand.v(<32 x i8>, <32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-andi-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-andi-invalid-imm.ll
index 60f0b765f9546..cd85cdacdbb11 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-andi-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-andi-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvandi.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-andi-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-andi-non-imm.ll
index 1273dc6b450b5..ca12d53ddf299 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-andi-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-andi-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvandi.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-andi.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-andi.ll
index 88cf142d69682..924b69745ea29 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-andi.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-andi.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvandi.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-andn.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-andn.ll
index f385ef3661cb9..4eabdc021ec0b 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-andn.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-andn.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvandn.v(<32 x i8>, <32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-avg.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-avg.ll
index 488d3b96b0038..b89511cbeeb5e 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-avg.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-avg.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvavg.b(<32 x i8>, <32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-avgr.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-avgr.ll
index b5ab5a5366aaf..0aa573e64c49e 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-avgr.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-avgr.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvavgr.b(<32 x i8>, <32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitclr-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitclr-invalid-imm.ll
index ecc287e89bbc0..462ea24510be3 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitclr-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitclr-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvbitclri.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitclr-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitclr-non-imm.ll
index 09da85411082b..0ecd45ca296d9 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitclr-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitclr-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvbitclri.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitclr.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitclr.ll
index cec71bab2fe84..9f148e5a447a5 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitclr.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitclr.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA64
declare <32 x i8> @llvm.loongarch.lasx.xvbitclr.b(<32 x i8>, <32 x i8>)
@@ -40,10 +41,21 @@ entry:
declare <4 x i64> @llvm.loongarch.lasx.xvbitclr.d(<4 x i64>, <4 x i64>)
define <4 x i64> @lasx_xvbitclr_d(<4 x i64> %va, <4 x i64> %vb) nounwind {
-; CHECK-LABEL: lasx_xvbitclr_d:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xvbitclr.d $xr0, $xr0, $xr1
-; CHECK-NEXT: ret
+; LA32-LABEL: lasx_xvbitclr_d:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: xvrepli.d $xr2, 63
+; LA32-NEXT: xvand.v $xr1, $xr1, $xr2
+; LA32-NEXT: xvrepli.d $xr2, 1
+; LA32-NEXT: xvsll.d $xr1, $xr2, $xr1
+; LA32-NEXT: xvrepli.b $xr2, -1
+; LA32-NEXT: xvxor.v $xr1, $xr1, $xr2
+; LA32-NEXT: xvand.v $xr0, $xr0, $xr1
+; LA32-NEXT: ret
+;
+; LA64-LABEL: lasx_xvbitclr_d:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: xvbitclr.d $xr0, $xr0, $xr1
+; LA64-NEXT: ret
entry:
%res = call <4 x i64> @llvm.loongarch.lasx.xvbitclr.d(<4 x i64> %va, <4 x i64> %vb)
ret <4 x i64> %res
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitrev-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitrev-invalid-imm.ll
index dff0884fdd5aa..9532684ab4202 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitrev-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitrev-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvbitrevi.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitrev-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitrev-non-imm.ll
index e1aef1a82f0c1..800ce010e3179 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitrev-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitrev-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvbitrevi.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitrev.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitrev.ll
index fb4f9fbc2e4b3..01c56eebf6c51 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitrev.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitrev.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA64
declare <32 x i8> @llvm.loongarch.lasx.xvbitrev.b(<32 x i8>, <32 x i8>)
@@ -40,10 +41,19 @@ entry:
declare <4 x i64> @llvm.loongarch.lasx.xvbitrev.d(<4 x i64>, <4 x i64>)
define <4 x i64> @lasx_xvbitrev_d(<4 x i64> %va, <4 x i64> %vb) nounwind {
-; CHECK-LABEL: lasx_xvbitrev_d:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xvbitrev.d $xr0, $xr0, $xr1
-; CHECK-NEXT: ret
+; LA32-LABEL: lasx_xvbitrev_d:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: xvrepli.d $xr2, 63
+; LA32-NEXT: xvand.v $xr1, $xr1, $xr2
+; LA32-NEXT: xvrepli.d $xr2, 1
+; LA32-NEXT: xvsll.d $xr1, $xr2, $xr1
+; LA32-NEXT: xvxor.v $xr0, $xr0, $xr1
+; LA32-NEXT: ret
+;
+; LA64-LABEL: lasx_xvbitrev_d:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: xvbitrev.d $xr0, $xr0, $xr1
+; LA64-NEXT: ret
entry:
%res = call <4 x i64> @llvm.loongarch.lasx.xvbitrev.d(<4 x i64> %va, <4 x i64> %vb)
ret <4 x i64> %res
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitsel.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitsel.ll
index 2e91407590ac1..f112b58b28c8f 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitsel.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitsel.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvbitsel.v(<32 x i8>, <32 x i8>, <32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitseli-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitseli-invalid-imm.ll
index 3f6fd44f842c6..7b0b60ebbf453 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitseli-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitseli-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvbitseli.b(<32 x i8>, <32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitseli-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitseli-non-imm.ll
index 40533ab96d86a..6f582fd4a9a10 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitseli-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitseli-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvbitseli.b(<32 x i8>, <32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitseli.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitseli.ll
index 79dd55cbfef98..1a3d5799194a3 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitseli.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitseli.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvbitseli.b(<32 x i8>, <32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitset-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitset-invalid-imm.ll
index 17a77ece7775b..f05b5c7681a2a 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitset-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitset-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvbitseti.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitset-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitset-non-imm.ll
index 613285804e0e4..a684c1bfec444 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitset-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitset-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvbitseti.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitset.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitset.ll
index 83d1f0ef60c63..0baad661ad59f 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitset.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bitset.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA64
declare <32 x i8> @llvm.loongarch.lasx.xvbitset.b(<32 x i8>, <32 x i8>)
@@ -40,10 +41,19 @@ entry:
declare <4 x i64> @llvm.loongarch.lasx.xvbitset.d(<4 x i64>, <4 x i64>)
define <4 x i64> @lasx_xvbitset_d(<4 x i64> %va, <4 x i64> %vb) nounwind {
-; CHECK-LABEL: lasx_xvbitset_d:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xvbitset.d $xr0, $xr0, $xr1
-; CHECK-NEXT: ret
+; LA32-LABEL: lasx_xvbitset_d:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: xvrepli.d $xr2, 63
+; LA32-NEXT: xvand.v $xr1, $xr1, $xr2
+; LA32-NEXT: xvrepli.d $xr2, 1
+; LA32-NEXT: xvsll.d $xr1, $xr2, $xr1
+; LA32-NEXT: xvor.v $xr0, $xr0, $xr1
+; LA32-NEXT: ret
+;
+; LA64-LABEL: lasx_xvbitset_d:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: xvbitset.d $xr0, $xr0, $xr1
+; LA64-NEXT: ret
entry:
%res = call <4 x i64> @llvm.loongarch.lasx.xvbitset.d(<4 x i64> %va, <4 x i64> %vb)
ret <4 x i64> %res
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsll-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsll-invalid-imm.ll
index 1da08a633bd2b..fbe6b69b679a1 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsll-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsll-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvbsll.v(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsll-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsll-non-imm.ll
index e19a3232c1797..694de9ec5a031 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsll-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsll-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvbsll.v(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsll.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsll.ll
index cbb63ced5cc00..f6e3542ed7cc1 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsll.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsll.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvbsll.v(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsrl-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsrl-invalid-imm.ll
index 5d2b63391e677..72a75f491a916 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsrl-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsrl-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvbsrl.v(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsrl-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsrl-non-imm.ll
index 8dfd0ca579b84..b74676a73ad92 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsrl-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsrl-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvbsrl.v(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsrl.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsrl.ll
index b0c26cbe3e35c..3e865eaa95d6a 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsrl.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-bsrl.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvbsrl.v(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-clo.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-clo.ll
index 29b2be03d54ec..4e8110f74fc8f 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-clo.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-clo.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvclo.b(<32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-clz.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-clz.ll
index 5247ceedbd146..526bc8ee176d1 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-clz.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-clz.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvclz.b(<32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-div.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-div.ll
index 813204092e944..9e23ee1bf2405 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-div.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-div.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvdiv.b(<32 x i8>, <32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ext2xv.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ext2xv.ll
index 48721b52af009..faf2a58f90a2a 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ext2xv.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ext2xv.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <16 x i16> @llvm.loongarch.lasx.vext2xv.h.b(<32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-exth.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-exth.ll
index 543589e61b12f..1580a09ca9750 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-exth.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-exth.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <16 x i16> @llvm.loongarch.lasx.xvexth.h.b(<32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-extl.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-extl.ll
index 7040c8c784cdf..b437c1f87687c 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-extl.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-extl.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <4 x i64> @llvm.loongarch.lasx.xvextl.q.d(<4 x i64>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-extrins-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-extrins-invalid-imm.ll
index 1301b8a146eb7..337f46a45fc3e 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-extrins-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-extrins-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvextrins.b(<32 x i8>, <32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-extrins-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-extrins-non-imm.ll
index bca8f8b3c778f..9164f8f623faf 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-extrins-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-extrins-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvextrins.b(<32 x i8>, <32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-extrins.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-extrins.ll
index c8774a7b29c0b..af1b3e2959a7e 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-extrins.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-extrins.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvextrins.b(<32 x i8>, <32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fadd.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fadd.ll
index 563a0ce9e384d..6b309d89b62e4 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fadd.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fadd.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <8 x float> @llvm.loongarch.lasx.xvfadd.s(<8 x float>, <8 x float>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fclass.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fclass.ll
index 901ca5bb02601..1a22e3a7eca76 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fclass.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fclass.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <8 x i32> @llvm.loongarch.lasx.xvfclass.s(<8 x float>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fcmp.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fcmp.ll
index b01f908e71af5..581d1a68bddab 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fcmp.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fcmp.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <8 x i32> @llvm.loongarch.lasx.xvfcmp.caf.s(<8 x float>, <8 x float>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fcvt.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fcvt.ll
index 82bf1d3df72c6..62206d7b8496c 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fcvt.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fcvt.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <16 x i16> @llvm.loongarch.lasx.xvfcvt.h.s(<8 x float>, <8 x float>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fcvth.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fcvth.ll
index e1a6a2923e677..c562e29231355 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fcvth.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fcvth.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <8 x float> @llvm.loongarch.lasx.xvfcvth.s.h(<16 x i16>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fcvtl.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fcvtl.ll
index 0b3e693c7f51d..4e270284568b1 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fcvtl.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fcvtl.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <8 x float> @llvm.loongarch.lasx.xvfcvtl.s.h(<16 x i16>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fdiv.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fdiv.ll
index 49923ddd4e8de..45a4d4c4d5ca1 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fdiv.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fdiv.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <8 x float> @llvm.loongarch.lasx.xvfdiv.s(<8 x float>, <8 x float>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ffint.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ffint.ll
index 24da0bd338387..fb96482795c56 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ffint.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ffint.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <8 x float> @llvm.loongarch.lasx.xvffint.s.w(<8 x i32>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-flogb.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-flogb.ll
index bccef4504d70e..7e82739563314 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-flogb.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-flogb.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <8 x float> @llvm.loongarch.lasx.xvflogb.s(<8 x float>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmadd.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmadd.ll
index 0fc06f9716602..1caf43fb42996 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmadd.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmadd.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <8 x float> @llvm.loongarch.lasx.xvfmadd.s(<8 x float>, <8 x float>, <8 x float>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmax.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmax.ll
index 2422fa0c00d8b..eb2fa913311c7 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmax.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmax.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <8 x float> @llvm.loongarch.lasx.xvfmax.s(<8 x float>, <8 x float>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmaxa.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmaxa.ll
index cd9ccc656aef6..adc4649d39334 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmaxa.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmaxa.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <8 x float> @llvm.loongarch.lasx.xvfmaxa.s(<8 x float>, <8 x float>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmin.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmin.ll
index effb3f9e1d75a..61205890a440d 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmin.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmin.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <8 x float> @llvm.loongarch.lasx.xvfmin.s(<8 x float>, <8 x float>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmina.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmina.ll
index 753a6f31ba061..214ab30ee7b3c 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmina.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmina.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <8 x float> @llvm.loongarch.lasx.xvfmina.s(<8 x float>, <8 x float>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmsub.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmsub.ll
index 57909d0dd1689..132aae31c4ed6 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmsub.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmsub.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <8 x float> @llvm.loongarch.lasx.xvfmsub.s(<8 x float>, <8 x float>, <8 x float>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmul.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmul.ll
index 9cad6f3830661..aca107fd4c182 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmul.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fmul.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <8 x float> @llvm.loongarch.lasx.xvfmul.s(<8 x float>, <8 x float>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fnmadd.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fnmadd.ll
index c30993590f98a..007b9739fe6a3 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fnmadd.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fnmadd.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <8 x float> @llvm.loongarch.lasx.xvfnmadd.s(<8 x float>, <8 x float>, <8 x float>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fnmsub.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fnmsub.ll
index 2e7ca695be625..3e711803828c9 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fnmsub.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fnmsub.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <8 x float> @llvm.loongarch.lasx.xvfnmsub.s(<8 x float>, <8 x float>, <8 x float>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frecip.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frecip.ll
index da3a26df2824e..aa3581018befd 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frecip.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frecip.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <8 x float> @llvm.loongarch.lasx.xvfrecip.s(<8 x float>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frint.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frint.ll
index ddead27cd14b5..b410d76c395a4 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frint.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frint.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <8 x float> @llvm.loongarch.lasx.xvfrintrne.s(<8 x float>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frsqrt.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frsqrt.ll
index 6efa8122baf18..692cfc19218d5 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frsqrt.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frsqrt.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <8 x float> @llvm.loongarch.lasx.xvfrsqrt.s(<8 x float>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frstp-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frstp-invalid-imm.ll
index 64b4632669d29..e9d1bf38eb5a3 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frstp-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frstp-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvfrstpi.b(<32 x i8>, <32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frstp-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frstp-non-imm.ll
index ca92cff9b2d1e..767d69ccc09c3 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frstp-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frstp-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvfrstpi.b(<32 x i8>, <32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frstp.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frstp.ll
index e83e55a52a113..853778f292a18 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frstp.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-frstp.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvfrstp.b(<32 x i8>, <32 x i8>, <32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fsqrt.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fsqrt.ll
index a13333d8d81c2..4669f2c92ed17 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fsqrt.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fsqrt.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <8 x float> @llvm.loongarch.lasx.xvfsqrt.s(<8 x float>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fsub.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fsub.ll
index b52774a03618d..3dde655fd5680 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fsub.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-fsub.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <8 x float> @llvm.loongarch.lasx.xvfsub.s(<8 x float>, <8 x float>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ftint.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ftint.ll
index 74cd507f16d26..b716c32d43e23 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ftint.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ftint.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <8 x i32> @llvm.loongarch.lasx.xvftintrne.w.s(<8 x float>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-haddw.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-haddw.ll
index 2c64ab23806b5..a75325228213f 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-haddw.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-haddw.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <16 x i16> @llvm.loongarch.lasx.xvhaddw.h.b(<32 x i8>, <32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-hsubw.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-hsubw.ll
index a5223c1d89a04..a40e80b730d08 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-hsubw.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-hsubw.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <16 x i16> @llvm.loongarch.lasx.xvhsubw.h.b(<32 x i8>, <32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ilv.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ilv.ll
index c9d0ca6b0324a..7e83feb2ed9a9 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ilv.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ilv.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvilvl.b(<32 x i8>, <32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insgr2vr-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insgr2vr-invalid-imm.ll
index 4982f2c7d43a9..1dd4ffad8fb32 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insgr2vr-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insgr2vr-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <8 x i32> @llvm.loongarch.lasx.xvinsgr2vr.w(<8 x i32>, i32, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insgr2vr-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insgr2vr-non-imm.ll
index 3accabf6dbd98..ef3c09cc1c428 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insgr2vr-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insgr2vr-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <8 x i32> @llvm.loongarch.lasx.xvinsgr2vr.w(<8 x i32>, i32, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insgr2vr.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insgr2vr.ll
index ea98c96464aed..1d1b33b4f9e68 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insgr2vr.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insgr2vr.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA64
declare <8 x i32> @llvm.loongarch.lasx.xvinsgr2vr.w(<8 x i32>, i32, i32)
@@ -17,11 +18,18 @@ entry:
declare <4 x i64> @llvm.loongarch.lasx.xvinsgr2vr.d(<4 x i64>, i64, i32)
define <4 x i64> @lasx_xvinsgr2vr_d(<4 x i64> %va) nounwind {
-; CHECK-LABEL: lasx_xvinsgr2vr_d:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: ori $a0, $zero, 1
-; CHECK-NEXT: xvinsgr2vr.d $xr0, $a0, 1
-; CHECK-NEXT: ret
+; LA32-LABEL: lasx_xvinsgr2vr_d:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: ori $a0, $zero, 1
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 2
+; LA32-NEXT: xvinsgr2vr.w $xr0, $zero, 3
+; LA32-NEXT: ret
+;
+; LA64-LABEL: lasx_xvinsgr2vr_d:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: ori $a0, $zero, 1
+; LA64-NEXT: xvinsgr2vr.d $xr0, $a0, 1
+; LA64-NEXT: ret
entry:
%res = call <4 x i64> @llvm.loongarch.lasx.xvinsgr2vr.d(<4 x i64> %va, i64 1, i32 1)
ret <4 x i64> %res
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insve0-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insve0-invalid-imm.ll
index a54fa8515fbaf..98d1532b26d12 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insve0-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insve0-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <8 x i32> @llvm.loongarch.lasx.xvinsve0.w(<8 x i32>, <8 x i32>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insve0-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insve0-non-imm.ll
index 53e59db11aa69..04f64e7a9c291 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insve0-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insve0-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <8 x i32> @llvm.loongarch.lasx.xvinsve0.w(<8 x i32>, <8 x i32>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insve0.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insve0.ll
index 27ae819c4144c..561ba17e8ff15 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insve0.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-insve0.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <8 x i32> @llvm.loongarch.lasx.xvinsve0.w(<8 x i32>, <8 x i32>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ld-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ld-invalid-imm.ll
index 27c690c91aecb..4dd6fc037aa26 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ld-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ld-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvld(ptr, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ld-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ld-non-imm.ll
index 1d8d5c764ce8b..c0e3239dfb896 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ld-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ld-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvld(ptr, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldi-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldi-invalid-imm.ll
index f3dd3650cf8a4..c574833ec8f37 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldi-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldi-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <4 x i64> @llvm.loongarch.lasx.xvldi(i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldi-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldi-non-imm.ll
index 6466818bf674b..eb41e993b9d1c 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldi-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldi-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <4 x i64> @llvm.loongarch.lasx.xvldi(i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldi.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldi.ll
index 59f79dd32af36..e65ecf5fda195 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldi.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldi.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <4 x i64> @llvm.loongarch.lasx.xvldi(i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldrepl-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldrepl-invalid-imm.ll
index 6fe6de82e1c0f..14cf0593c2de3 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldrepl-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldrepl-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvldrepl.b(ptr, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldrepl-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldrepl-non-imm.ll
index 74c22298db500..05a44e9d2806b 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldrepl-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldrepl-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvldrepl.b(ptr, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldrepl.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldrepl.ll
index ccd969a9f2998..bb5bb6539d2ad 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldrepl.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ldrepl.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvldrepl.b(ptr, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-madd.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-madd.ll
index d3b09396727e7..8dd45221d421b 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-madd.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-madd.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvmadd.b(<32 x i8>, <32 x i8>, <32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-maddw.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-maddw.ll
index 146624a764a22..eb7189cf0ae7d 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-maddw.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-maddw.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <16 x i16> @llvm.loongarch.lasx.xvmaddwev.h.b(<16 x i16>, <32 x i8>, <32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-max-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-max-non-imm.ll
index b85798b53c92d..33035ffb14136 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-max-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-max-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvmaxi.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-max.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-max.ll
index 9cf09df4439ad..4739ed6be91de 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-max.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-max.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvmax.b(<32 x i8>, <32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-min-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-min-non-imm.ll
index b81931977aad4..f853ca45fce1e 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-min-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-min-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvmini.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-min.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-min.ll
index c94b1e4ea44cb..dde42a0239ad0 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-min.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-min.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvmin.b(<32 x i8>, <32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-mod.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-mod.ll
index a177246bb2350..9b13612c8d04d 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-mod.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-mod.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvmod.b(<32 x i8>, <32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-mskgez.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-mskgez.ll
index da87c20ad6ee0..afb8472d18a7c 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-mskgez.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-mskgez.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvmskgez.b(<32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-mskltz.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-mskltz.ll
index b2218487535c6..4a6640ead1714 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-mskltz.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-mskltz.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvmskltz.b(<32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-msknz.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-msknz.ll
index becd2c883a7ed..f6d4998f47d4d 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-msknz.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-msknz.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvmsknz.b(<32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-msub.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-msub.ll
index c89f9578b77d7..5a7f5bffe2281 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-msub.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-msub.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvmsub.b(<32 x i8>, <32 x i8>, <32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-muh.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-muh.ll
index 97461512ce166..4d7b14cc5fe0a 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-muh.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-muh.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvmuh.b(<32 x i8>, <32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-mul.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-mul.ll
index d5d852e58a9f9..305604ed6c08f 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-mul.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-mul.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvmul.b(<32 x i8>, <32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-mulw.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-mulw.ll
index f69e64aa76980..d7a8aaade2032 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-mulw.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-mulw.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <16 x i16> @llvm.loongarch.lasx.xvmulwev.h.b(<32 x i8>, <32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-neg.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-neg.ll
index ecbedf3346578..e4b7ef728490c 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-neg.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-neg.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvneg.b(<32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-nor.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-nor.ll
index 674746b7624ec..fa6f5a22cdbc2 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-nor.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-nor.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvnor.v(<32 x i8>, <32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-nori-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-nori-invalid-imm.ll
index 1130e094bf1f9..e3f061e6a1c94 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-nori-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-nori-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvnori.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-nori-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-nori-non-imm.ll
index 8f2333064d642..92feeeb00aa10 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-nori-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-nori-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvnori.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-nori.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-nori.ll
index 55eebf87ee921..fc3c6398d6f16 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-nori.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-nori.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvnori.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-or.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-or.ll
index 16462cfafc54a..b1b5e4b7e0091 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-or.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-or.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvor.v(<32 x i8>, <32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ori-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ori-invalid-imm.ll
index 90dec8e55f2d8..de37309a623f5 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ori-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ori-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvori.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ori-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ori-non-imm.ll
index ae6571d98f4af..49296350000bb 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ori-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ori-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvori.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ori.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ori.ll
index 8e53d88bac374..96eaf0140a419 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ori.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ori.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvori.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-orn.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-orn.ll
index 3a335cdd37167..ea2c69bbb1c8a 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-orn.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-orn.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvorn.v(<32 x i8>, <32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pack.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pack.ll
index 512b302349172..89ca5d4883c2f 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pack.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pack.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvpackev.b(<32 x i8>, <32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pcnt.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pcnt.ll
index d77f1d2082c8d..80c8f0a19c8ed 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pcnt.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pcnt.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvpcnt.b(<32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-perm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-perm.ll
index 4ec434edd4ec7..086b250324b10 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-perm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-perm.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <8 x i32> @llvm.loongarch.lasx.xvperm.w(<8 x i32>, <8 x i32>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-permi-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-permi-invalid-imm.ll
index 41f4856bd8f71..78f876cf46616 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-permi-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-permi-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <8 x i32> @llvm.loongarch.lasx.xvpermi.w(<8 x i32>, <8 x i32>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-permi-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-permi-non-imm.ll
index afb335c5d6cab..50723bb1960e0 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-permi-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-permi-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <8 x i32> @llvm.loongarch.lasx.xvpermi.w(<8 x i32>, <8 x i32>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-permi.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-permi.ll
index 0d9f9daabc448..73797899431b6 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-permi.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-permi.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <8 x i32> @llvm.loongarch.lasx.xvpermi.w(<8 x i32>, <8 x i32>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pick.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pick.ll
index bbd6d693ca0b3..cc3c4bb3ed385 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pick.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pick.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvpickev.b(<32 x i8>, <32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pickve-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pickve-invalid-imm.ll
index cfc6ec42874e1..f113ee2c3e9a6 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pickve-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pickve-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <8 x i32> @llvm.loongarch.lasx.xvpickve.w(<8 x i32>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pickve-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pickve-non-imm.ll
index be1f19a897370..eae84ac93d7e7 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pickve-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pickve-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <8 x i32> @llvm.loongarch.lasx.xvpickve.w(<8 x i32>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pickve.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pickve.ll
index 546777bc72ab4..a4f0bad28d410 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pickve.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pickve.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <8 x i32> @llvm.loongarch.lasx.xvpickve.w(<8 x i32>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pickve2gr-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pickve2gr-non-imm.ll
index 0fa8c94adc60c..f3d6e3149187b 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pickve2gr-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-pickve2gr-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare i32 @llvm.loongarch.lasx.xvpickve2gr.w(<8 x i32>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-repl128vei-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-repl128vei-invalid-imm.ll
index a0cb309c54e19..4a20a21baf4cc 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-repl128vei-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-repl128vei-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvrepl128vei.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-repl128vei-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-repl128vei-non-imm.ll
index c537ffa66ba7f..fd99f3b52f65e 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-repl128vei-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-repl128vei-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvrepl128vei.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-repl128vei.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-repl128vei.ll
index 25fab44f461f5..500ab529b725e 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-repl128vei.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-repl128vei.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvrepl128vei.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-replve.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-replve.ll
index 21d36ff7bb5ee..b95c5323d9731 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-replve.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-replve.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvreplve.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-replve0.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-replve0.ll
index 7996bb36ef03c..c70fb4e01e917 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-replve0.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-replve0.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvreplve0.b(<32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-rotr-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-rotr-invalid-imm.ll
index 40abdf4976050..1f7434c775940 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-rotr-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-rotr-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvrotri.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-rotr-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-rotr-non-imm.ll
index dd38301d05345..69ed350f3480c 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-rotr-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-rotr-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvrotri.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-rotr.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-rotr.ll
index 64d2773864e9f..c65f8d0737571 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-rotr.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-rotr.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvrotr.b(<32 x i8>, <32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sadd.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sadd.ll
index 54a5e2e9c8332..bec705422d199 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sadd.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sadd.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvsadd.b(<32 x i8>, <32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sat-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sat-invalid-imm.ll
index 839fbc9990d34..e9d9e9f5d18a3 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sat-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sat-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvsat.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sat-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sat-non-imm.ll
index b73b32ebd3b02..9d90274653407 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sat-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sat-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvsat.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sat.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sat.ll
index 293b9dc9eb4d9..77fc912e78f94 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sat.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sat.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvsat.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-seq-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-seq-invalid-imm.ll
index bb6ef0cc6574c..39ef86cc36b41 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-seq-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-seq-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvseqi.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-seq-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-seq-non-imm.ll
index fb2c6206da7b9..24cf5c0b940a8 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-seq-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-seq-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvseqi.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-seq.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-seq.ll
index 83bc93c88c73c..d4e48e8575a6a 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-seq.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-seq.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvseq.b(<32 x i8>, <32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-shuf.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-shuf.ll
index 9b9140f6ad621..35fab17aa6116 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-shuf.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-shuf.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvshuf.b(<32 x i8>, <32 x i8>, <32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-shuf4i-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-shuf4i-invalid-imm.ll
index 9217d1f6a05da..65660dbbe7807 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-shuf4i-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-shuf4i-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvshuf4i.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-shuf4i-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-shuf4i-non-imm.ll
index 8d6d1c6941938..0f2652472a642 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-shuf4i-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-shuf4i-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvshuf4i.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-shuf4i.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-shuf4i.ll
index 31205086759c4..7e0e6a8a2aa96 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-shuf4i.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-shuf4i.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvshuf4i.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-signcov.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-signcov.ll
index e6c6d8ccd0d35..2ee27d6128884 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-signcov.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-signcov.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvsigncov.b(<32 x i8>, <32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sle-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sle-invalid-imm.ll
index 5b10aca9801d6..791f7b2845805 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sle-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sle-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvslei.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sle-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sle-non-imm.ll
index 903bc10d88b78..6a3c6efe1e60a 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sle-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sle-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvslei.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sle.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sle.ll
index 8895efc84b845..fa3e3389ed8e8 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sle.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sle.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvsle.b(<32 x i8>, <32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sll-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sll-invalid-imm.ll
index bf8205376a6c2..2514788b1dffa 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sll-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sll-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvslli.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sll-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sll-non-imm.ll
index b5368a86b5c3b..0cc5f79621996 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sll-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sll-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvslli.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sll.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sll.ll
index 14110b613dbe3..228facde7b969 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sll.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sll.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA64
declare <32 x i8> @llvm.loongarch.lasx.xvsll.b(<32 x i8>, <32 x i8>)
@@ -40,10 +41,17 @@ entry:
declare <4 x i64> @llvm.loongarch.lasx.xvsll.d(<4 x i64>, <4 x i64>)
define <4 x i64> @lasx_xvsll_d(<4 x i64> %va, <4 x i64> %vb) nounwind {
-; CHECK-LABEL: lasx_xvsll_d:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xvsll.d $xr0, $xr0, $xr1
-; CHECK-NEXT: ret
+; LA32-LABEL: lasx_xvsll_d:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: xvrepli.d $xr2, 63
+; LA32-NEXT: xvand.v $xr1, $xr1, $xr2
+; LA32-NEXT: xvsll.d $xr0, $xr0, $xr1
+; LA32-NEXT: ret
+;
+; LA64-LABEL: lasx_xvsll_d:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: xvsll.d $xr0, $xr0, $xr1
+; LA64-NEXT: ret
entry:
%res = call <4 x i64> @llvm.loongarch.lasx.xvsll.d(<4 x i64> %va, <4 x i64> %vb)
ret <4 x i64> %res
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sllwil-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sllwil-invalid-imm.ll
index 18803767d6c01..28df3fcc37ec0 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sllwil-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sllwil-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <16 x i16> @llvm.loongarch.lasx.xvsllwil.h.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sllwil-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sllwil-non-imm.ll
index 3f5d4d6316715..49e1a1d4108ca 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sllwil-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sllwil-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <16 x i16> @llvm.loongarch.lasx.xvsllwil.h.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sllwil.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sllwil.ll
index a72b8a6cbb4f4..9cd6312d07ef6 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sllwil.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sllwil.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <16 x i16> @llvm.loongarch.lasx.xvsllwil.h.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-slt-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-slt-invalid-imm.ll
index dc0567da4e47e..c92c006672aa3 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-slt-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-slt-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvslti.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-slt-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-slt-non-imm.ll
index a2cedc8d3ef34..b129cb00caf67 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-slt-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-slt-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvslti.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-slt.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-slt.ll
index 3ea87adff110a..94e587288c13d 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-slt.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-slt.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvslt.b(<32 x i8>, <32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sra-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sra-invalid-imm.ll
index 15b522d5e7e3a..004f0ffb277cc 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sra-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sra-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvsrai.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sra-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sra-non-imm.ll
index fefee7246ae6d..1438becbea98d 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sra-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sra-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvsrai.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sra.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sra.ll
index a7498682559bd..12bc60695304b 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sra.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sra.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA64
declare <32 x i8> @llvm.loongarch.lasx.xvsra.b(<32 x i8>, <32 x i8>)
@@ -40,10 +41,17 @@ entry:
declare <4 x i64> @llvm.loongarch.lasx.xvsra.d(<4 x i64>, <4 x i64>)
define <4 x i64> @lasx_xvsra_d(<4 x i64> %va, <4 x i64> %vb) nounwind {
-; CHECK-LABEL: lasx_xvsra_d:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xvsra.d $xr0, $xr0, $xr1
-; CHECK-NEXT: ret
+; LA32-LABEL: lasx_xvsra_d:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: xvrepli.d $xr2, 63
+; LA32-NEXT: xvand.v $xr1, $xr1, $xr2
+; LA32-NEXT: xvsra.d $xr0, $xr0, $xr1
+; LA32-NEXT: ret
+;
+; LA64-LABEL: lasx_xvsra_d:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: xvsra.d $xr0, $xr0, $xr1
+; LA64-NEXT: ret
entry:
%res = call <4 x i64> @llvm.loongarch.lasx.xvsra.d(<4 x i64> %va, <4 x i64> %vb)
ret <4 x i64> %res
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sran.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sran.ll
index f59ae4c196621..9690b9b960d3c 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sran.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sran.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvsran.b.h(<16 x i16>, <16 x i16>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srani-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srani-invalid-imm.ll
index bedbfc4889d20..c4592d628e573 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srani-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srani-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvsrani.b.h(<32 x i8>, <32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srani-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srani-non-imm.ll
index 3c17f2b6090a9..2ac5cd9d6399d 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srani-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srani-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvsrani.b.h(<32 x i8>, <32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srani.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srani.ll
index 91fb90da9c525..dc017da9eddaf 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srani.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srani.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvsrani.b.h(<32 x i8>, <32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srar-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srar-invalid-imm.ll
index e417e3cc5bbfe..49f8505746ebb 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srar-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srar-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvsrari.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srar-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srar-non-imm.ll
index 15fed7966f1c2..430187b11b743 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srar-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srar-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvsrari.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srar.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srar.ll
index e2c160557c4dc..fcba1aa005e26 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srar.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srar.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvsrar.b(<32 x i8>, <32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srarn.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srarn.ll
index 02dd989773ca1..bfb725d13547e 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srarn.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srarn.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvsrarn.b.h(<16 x i16>, <16 x i16>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srarni-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srarni-invalid-imm.ll
index 83e977827e2d0..35786248752cb 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srarni-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srarni-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvsrarni.b.h(<32 x i8>, <32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srarni-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srarni-non-imm.ll
index eb577a29fb33b..fb7bcc380aab4 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srarni-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srarni-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvsrarni.b.h(<32 x i8>, <32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srarni.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srarni.ll
index a7d2c37397936..9c3848b396118 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srarni.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srarni.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvsrarni.b.h(<32 x i8>, <32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srl-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srl-invalid-imm.ll
index 3ab02dcb97edd..2824c3944b88e 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srl-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srl-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvsrli.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srl-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srl-non-imm.ll
index bc085aeaa232a..52a84c8b5bcc1 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srl-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srl-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvsrli.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srl.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srl.ll
index 7b2992f2ca3bc..315ca74ad6dcb 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srl.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srl.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA64
declare <32 x i8> @llvm.loongarch.lasx.xvsrl.b(<32 x i8>, <32 x i8>)
@@ -40,10 +41,17 @@ entry:
declare <4 x i64> @llvm.loongarch.lasx.xvsrl.d(<4 x i64>, <4 x i64>)
define <4 x i64> @lasx_xvsrl_d(<4 x i64> %va, <4 x i64> %vb) nounwind {
-; CHECK-LABEL: lasx_xvsrl_d:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xvsrl.d $xr0, $xr0, $xr1
-; CHECK-NEXT: ret
+; LA32-LABEL: lasx_xvsrl_d:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: xvrepli.d $xr2, 63
+; LA32-NEXT: xvand.v $xr1, $xr1, $xr2
+; LA32-NEXT: xvsrl.d $xr0, $xr0, $xr1
+; LA32-NEXT: ret
+;
+; LA64-LABEL: lasx_xvsrl_d:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: xvsrl.d $xr0, $xr0, $xr1
+; LA64-NEXT: ret
entry:
%res = call <4 x i64> @llvm.loongarch.lasx.xvsrl.d(<4 x i64> %va, <4 x i64> %vb)
ret <4 x i64> %res
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srln.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srln.ll
index dc5c0e016ea0a..f72672ffba5ab 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srln.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srln.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvsrln.b.h(<16 x i16>, <16 x i16>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlni-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlni-invalid-imm.ll
index 9e7c94305630b..67f9fb70fcaf8 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlni-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlni-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvsrlni.b.h(<32 x i8>, <32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlni-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlni-non-imm.ll
index 66d8004700034..58b2182e929bc 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlni-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlni-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvsrlni.b.h(<32 x i8>, <32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlni.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlni.ll
index 0301ebb195e26..f87b41304f03e 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlni.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlni.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvsrlni.b.h(<32 x i8>, <32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlr-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlr-invalid-imm.ll
index 52621ddc6f49a..de78e88c3e481 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlr-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlr-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvsrlri.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlr-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlr-non-imm.ll
index 5663e3475b122..e088643d97b33 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlr-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlr-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvsrlri.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlr.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlr.ll
index e04504158e274..0a57b07b38f6c 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlr.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlr.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvsrlr.b(<32 x i8>, <32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlrn.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlrn.ll
index 1e7df379c6e1e..546da10306981 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlrn.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlrn.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvsrlrn.b.h(<16 x i16>, <16 x i16>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlrni-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlrni-invalid-imm.ll
index 2d65a75b175a3..eafdbf5b2bdee 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlrni-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlrni-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvsrlrni.b.h(<32 x i8>, <32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlrni-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlrni-non-imm.ll
index 82da0d21d013e..8a401ef8a9927 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlrni-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlrni-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvsrlrni.b.h(<32 x i8>, <32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlrni.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlrni.ll
index 56dbafe8b1ac3..2851d47154732 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlrni.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-srlrni.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvsrlrni.b.h(<32 x i8>, <32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssran.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssran.ll
index da1857dad1451..29640da6f7c60 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssran.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssran.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvssran.b.h(<16 x i16>, <16 x i16>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrani-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrani-invalid-imm.ll
index e10d5d7bd4882..cd3b3baa9a589 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrani-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrani-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvssrani.b.h(<32 x i8>, <32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrani-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrani-non-imm.ll
index a928cc2de8c81..3d912502e0cc0 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrani-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrani-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvssrani.b.h(<32 x i8>, <32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrani.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrani.ll
index 9efa659b4a1e0..7461f4c71c01c 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrani.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrani.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvssrani.b.h(<32 x i8>, <32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrarn.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrarn.ll
index b5d59ff06f4d1..9502b29b5d677 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrarn.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrarn.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvssrarn.b.h(<16 x i16>, <16 x i16>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrarni-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrarni-invalid-imm.ll
index 42cd6ac99754e..5d0153fd4c8d8 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrarni-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrarni-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvssrarni.b.h(<32 x i8>, <32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrarni-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrarni-non-imm.ll
index f050e7d79b0f5..d7ba76e878df2 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrarni-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrarni-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvssrarni.b.h(<32 x i8>, <32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrarni.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrarni.ll
index da411dad645bb..90abf2fab74d3 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrarni.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrarni.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvssrarni.b.h(<32 x i8>, <32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrln.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrln.ll
index c60b5bdf81a03..1352baecd12af 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrln.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrln.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvssrln.b.h(<16 x i16>, <16 x i16>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlni-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlni-invalid-imm.ll
index 26be21a83aa4d..fc41df8c6fbfe 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlni-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlni-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvssrlni.b.h(<32 x i8>, <32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlni-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlni-non-imm.ll
index 72da2a746dd5d..99b0d45617921 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlni-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlni-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvssrlni.b.h(<32 x i8>, <32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlni.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlni.ll
index e57dd426bde8c..1a49761dedaea 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlni.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlni.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvssrlni.b.h(<32 x i8>, <32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlrn.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlrn.ll
index 774cf1bd5e849..d89511ba180ea 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlrn.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlrn.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvssrlrn.b.h(<16 x i16>, <16 x i16>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlrni-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlrni-invalid-imm.ll
index cd778e2c0627d..36d19b5ce9f47 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlrni-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlrni-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvssrlrni.b.h(<32 x i8>, <32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlrni-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlrni-non-imm.ll
index a10c543291499..69f5baa8536b0 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlrni-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlrni-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvssrlrni.b.h(<32 x i8>, <32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlrni.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlrni.ll
index 9a80516d8d783..b3119d6b27bb0 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlrni.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssrlrni.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvssrlrni.b.h(<32 x i8>, <32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssub.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssub.ll
index cd3ccd9f52625..e600eac3f0023 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssub.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-ssub.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvssub.b(<32 x i8>, <32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-st-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-st-invalid-imm.ll
index 6108ae1883da5..d659f1d95865e 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-st-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-st-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare void @llvm.loongarch.lasx.xvst(<32 x i8>, ptr, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-st-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-st-non-imm.ll
index 969fb5765dd82..0882834b23a3b 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-st-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-st-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare void @llvm.loongarch.lasx.xvst(<32 x i8>, ptr, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-stelm-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-stelm-invalid-imm.ll
index 4593de13fbff7..a1de4f49b5802 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-stelm-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-stelm-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare void @llvm.loongarch.lasx.xvstelm.b(<32 x i8>, ptr, i32, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-stelm-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-stelm-non-imm.ll
index faa7d501eb743..d970689e63d4d 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-stelm-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-stelm-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare void @llvm.loongarch.lasx.xvstelm.b(<32 x i8>, ptr, i32, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-stelm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-stelm.ll
index 34d1866e9d5ed..87c5946270ef8 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-stelm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-stelm.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare void @llvm.loongarch.lasx.xvstelm.b(<32 x i8>, ptr, i32, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sub.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sub.ll
index 4d69dd83dcde7..f8778adb458e4 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sub.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-sub.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvsub.b(<32 x i8>, <32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-subi-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-subi-invalid-imm.ll
index 810008c17f7e5..8e24ec98d0c57 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-subi-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-subi-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvsubi.bu(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-subi-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-subi-non-imm.ll
index 924b89ce9d6c4..73ff9268230d6 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-subi-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-subi-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvsubi.bu(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-subi.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-subi.ll
index cc3235ff4657d..1992628aefbcb 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-subi.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-subi.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvsubi.bu(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-subw.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-subw.ll
index 6f203e8949900..afdd7b2e79357 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-subw.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-subw.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <16 x i16> @llvm.loongarch.lasx.xvsubwev.h.b(<32 x i8>, <32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-xor.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-xor.ll
index 6395b3d6f2e7a..98d180f3560fb 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-xor.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-xor.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvxor.v(<32 x i8>, <32 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-xori-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-xori-invalid-imm.ll
index 0170d204cf425..d12082b3eafcb 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-xori-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-xori-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvxori.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-xori-non-imm.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-xori-non-imm.ll
index 1478f691a1cc6..e1c9574aeafa9 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-xori-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-xori-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lasx < %s 2>&1 | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvxori.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-xori.ll b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-xori.ll
index c71d7e7311656..8cc53991fb6eb 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/intrinsic-xori.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/intrinsic-xori.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
declare <32 x i8> @llvm.loongarch.lasx.xvxori.b(<32 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/absd.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/absd.ll
index c5df9f8420837..20934480dce93 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/absd.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/absd.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc -mtriple=loongarch64 -mattr=+lasx < %s | FileCheck %s
;; 1. trunc(abs(sub(sext(a),sext(b)))) -> abds(a,b) or abdu(a,b)
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/add.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/add.ll
index 136f34bafb32a..030f75b775adb 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/add.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/add.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
define void @add_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind {
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/and.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/and.ll
index b06d1bea4ef62..a2df7aa1ae6d7 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/and.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/and.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
define void @and_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind {
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/ashr.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/ashr.ll
index 4dd2cee7a2ed5..edcbe15839458 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/ashr.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/ashr.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
define void @ashr_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind {
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/bitcast-extract-element.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/bitcast-extract-element.ll
index 09ce1a04d6c9d..073fc54f5654c 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/bitcast-extract-element.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/bitcast-extract-element.ll
@@ -1,11 +1,18 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefix=LA64
define i32 @bitcast_extract_v8f32(<8 x float> %a) nounwind {
-; CHECK-LABEL: bitcast_extract_v8f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xvpickve2gr.w $a0, $xr0, 7
-; CHECK-NEXT: ret
+; LA32-LABEL: bitcast_extract_v8f32:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: xvpickve.w $xr0, $xr0, 7
+; LA32-NEXT: movfr2gr.s $a0, $fa0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: bitcast_extract_v8f32:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: xvpickve2gr.w $a0, $xr0, 7
+; LA64-NEXT: ret
entry:
%b = extractelement <8 x float> %a, i32 7
%c = bitcast float %b to i32
@@ -13,10 +20,17 @@ entry:
}
define i64 @bitcast_extract_v4f64(<4 x double> %a) nounwind {
-; CHECK-LABEL: bitcast_extract_v4f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xvpickve2gr.d $a0, $xr0, 3
-; CHECK-NEXT: ret
+; LA32-LABEL: bitcast_extract_v4f64:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: xvpickve.d $xr0, $xr0, 3
+; LA32-NEXT: movfr2gr.s $a0, $fa0
+; LA32-NEXT: movfrh2gr.s $a1, $fa0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: bitcast_extract_v4f64:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: xvpickve2gr.d $a0, $xr0, 3
+; LA64-NEXT: ret
entry:
%b = extractelement <4 x double> %a, i32 3
%c = bitcast double %b to i64
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fadd.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fadd.ll
index b3eb328e8d446..b4d5dc10c20c9 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fadd.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fadd.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
define void @fadd_v8f32(ptr %res, ptr %a0, ptr %a1) nounwind {
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fcmp.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fcmp.ll
index 4f56dd29c1b25..be60b7518e399 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fcmp.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fcmp.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
;; TREU
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fdiv.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fdiv.ll
index 63d8c222ae54f..ae6f091ddb498 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fdiv.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fdiv.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA64
define void @fdiv_v8f32(ptr %res, ptr %a0, ptr %a1) nounwind {
; CHECK-LABEL: fdiv_v8f32:
@@ -49,12 +50,21 @@ entry:
}
define void @one_fdiv_v4f64(ptr %res, ptr %a0) nounwind {
-; CHECK-LABEL: one_fdiv_v4f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xvld $xr0, $a1, 0
-; CHECK-NEXT: xvfrecip.d $xr0, $xr0
-; CHECK-NEXT: xvst $xr0, $a0, 0
-; CHECK-NEXT: ret
+; LA32-LABEL: one_fdiv_v4f64:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: xvld $xr0, $a1, 0
+; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI3_0)
+; LA32-NEXT: xvld $xr1, $a1, %pc_lo12(.LCPI3_0)
+; LA32-NEXT: xvfdiv.d $xr0, $xr1, $xr0
+; LA32-NEXT: xvst $xr0, $a0, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: one_fdiv_v4f64:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: xvld $xr0, $a1, 0
+; LA64-NEXT: xvfrecip.d $xr0, $xr0
+; LA64-NEXT: xvst $xr0, $a0, 0
+; LA64-NEXT: ret
entry:
%v0 = load <4 x double>, ptr %a0
%div = fdiv <4 x double> <double 1.0, double 1.0, double 1.0, double 1.0>, %v0
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fix-xvshuf.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fix-xvshuf.ll
index 8ee567c2a92f9..ffb793dd13016 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fix-xvshuf.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fix-xvshuf.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx %s -o - | FileCheck %s
;; Fix https://github.com/llvm/llvm-project/issues/137000.
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fmul.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fmul.ll
index f777151cdb0ac..430ab98a5c697 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fmul.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fmul.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
define void @fmul_v8f32(ptr %res, ptr %a0, ptr %a1) nounwind {
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fneg.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fneg.ll
index 5eb468fc55a0e..515403f8362ca 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fneg.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fneg.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
define void @fneg_v8f32(ptr %res, ptr %a0) nounwind {
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fptosi.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fptosi.ll
index ed333c303879c..5b63ef3e53a4c 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fptosi.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fptosi.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
define void @fptosi_v8f32_v8i32(ptr %res, ptr %in){
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fptoui.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fptoui.ll
index 9c499ba71d646..4c699a0721bff 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fptoui.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fptoui.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
define void @fptoui_v8f32_v8i32(ptr %res, ptr %in){
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fsub.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fsub.ll
index 201ba5f5df66f..99074e08c0de1 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fsub.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/fsub.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
define void @fsub_v8f32(ptr %res, ptr %a0, ptr %a1) nounwind {
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/icmp.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/icmp.ll
index d15c4133855f4..47229fc9a0fc4 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/icmp.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/icmp.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
;; SETEQ
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insert-bitcast-element.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insert-bitcast-element.ll
index b37b525981fd9..4a9d2579766ba 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insert-bitcast-element.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insert-bitcast-element.ll
@@ -1,11 +1,18 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefix=LA64
define <8 x float> @insert_bitcast_v8f32(<8 x float> %a, i32 %b) nounwind {
-; CHECK-LABEL: insert_bitcast_v8f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xvinsgr2vr.w $xr0, $a0, 1
-; CHECK-NEXT: ret
+; LA32-LABEL: insert_bitcast_v8f32:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: movgr2fr.w $fa1, $a0
+; LA32-NEXT: xvinsve0.w $xr0, $xr1, 1
+; LA32-NEXT: ret
+;
+; LA64-LABEL: insert_bitcast_v8f32:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: xvinsgr2vr.w $xr0, $a0, 1
+; LA64-NEXT: ret
entry:
%c = bitcast i32 %b to float
%d = insertelement <8 x float> %a, float %c, i32 1
@@ -13,10 +20,17 @@ entry:
}
define <4 x double> @insert_bitcast_v4f64(<4 x double> %a, i64 %b) nounwind {
-; CHECK-LABEL: insert_bitcast_v4f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: xvinsgr2vr.d $xr0, $a0, 1
-; CHECK-NEXT: ret
+; LA32-LABEL: insert_bitcast_v4f64:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: movgr2fr.w $fa1, $a0
+; LA32-NEXT: movgr2frh.w $fa1, $a1
+; LA32-NEXT: xvinsve0.d $xr0, $xr1, 1
+; LA32-NEXT: ret
+;
+; LA64-LABEL: insert_bitcast_v4f64:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: xvinsgr2vr.d $xr0, $a0, 1
+; LA64-NEXT: ret
entry:
%c = bitcast i64 %b to double
%d = insertelement <4 x double> %a, double %c, i32 1
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/lshr.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/lshr.ll
index 5b992b5e38de5..4baa6e2bf1a28 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/lshr.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/lshr.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
define void @lshr_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind {
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/mul.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/mul.ll
index 4745e7003cb1c..620d2233c904c 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/mul.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/mul.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
define void @mul_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind {
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/or.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/or.ll
index f32b8897bebce..07ccb88f2bbad 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/or.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/or.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
define void @or_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind {
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sdiv.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sdiv.ll
index 879caa5a6700d..2c783e3a5e229 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sdiv.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sdiv.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
define void @sdiv_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind {
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shl.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shl.ll
index 56c69171c9d44..3e496eac475c9 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shl.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shl.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
define void @shl_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind {
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvilv.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvilv.ll
index 22ab19b9fa446..382c0f5516927 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvilv.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvilv.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx %s -o - | FileCheck %s
;; xvilvl.b
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvpack.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvpack.ll
index 2ff9af4069b9b..c36a87f77bb2e 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvpack.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvpack.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx %s -o - | FileCheck %s
;; xvpackev.b
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvpick.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvpick.ll
index 294d292d17640..327f1d4f54812 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvpick.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/shuffle-as-xvpick.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx %s -o - | FileCheck %s
;; xvpickev.b
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sitofp.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sitofp.ll
index 208a758ea4e9a..3673f594094be 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sitofp.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sitofp.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
define void @sitofp_v8i32_v8f32(ptr %res, ptr %in){
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sub.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sub.ll
index 5102abac83d80..bf9f29b578d7d 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sub.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/sub.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
define void @sub_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind {
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/udiv.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/udiv.ll
index 43f558f3cdf37..c3bd69a8a0bcb 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/udiv.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/udiv.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
define void @udiv_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind {
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/uitofp.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/uitofp.ll
index 70cf71c4cec21..6e417032acff5 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/uitofp.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/uitofp.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
define void @uitofp_v8i32_v8f32(ptr %res, ptr %in){
diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/xor.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/xor.ll
index e062e10b21d9f..5365685d395e4 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/xor.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/xor.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
define void @xor_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind {
diff --git a/llvm/test/CodeGen/LoongArch/lasx/issue107355.ll b/llvm/test/CodeGen/LoongArch/lasx/issue107355.ll
index 506b5c1232f25..249414f5b1bb9 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/issue107355.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/issue107355.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefix=LA64
;; Without this patch(codegen for concat_vectors), the test will hang.
@g_156 = external global [12 x i32]
@@ -7,23 +8,51 @@
@g_813 = external global i32
define void @foo() {
-; CHECK-LABEL: foo:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: pcalau12i $a0, %got_pc_hi20(g_156)
-; CHECK-NEXT: ld.d $a0, $a0, %got_pc_lo12(g_156)
-; CHECK-NEXT: pcalau12i $a1, %got_pc_hi20(g_490)
-; CHECK-NEXT: ld.d $a1, $a1, %got_pc_lo12(g_490)
-; CHECK-NEXT: ld.w $a2, $a0, 24
-; CHECK-NEXT: pcalau12i $a3, %got_pc_hi20(g_813)
-; CHECK-NEXT: ld.d $a3, $a3, %got_pc_lo12(g_813)
-; CHECK-NEXT: st.w $zero, $a1, 0
-; CHECK-NEXT: st.w $a2, $a3, 0
-; CHECK-NEXT: xvrepli.b $xr0, 0
-; CHECK-NEXT: xvst $xr0, $a0, 0
-; CHECK-NEXT: vrepli.b $vr0, 0
-; CHECK-NEXT: vst $vr0, $a0, 32
-; CHECK-NEXT: st.w $zero, $a0, 20
-; CHECK-NEXT: ret
+; LA32-LABEL: foo:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: addi.w $sp, $sp, -16
+; LA32-NEXT: .cfi_def_cfa_offset 16
+; LA32-NEXT: st.w $ra, $sp, 12 # 4-byte Folded Spill
+; LA32-NEXT: st.w $fp, $sp, 8 # 4-byte Folded Spill
+; LA32-NEXT: .cfi_offset 1, -4
+; LA32-NEXT: .cfi_offset 22, -8
+; LA32-NEXT: pcalau12i $a0, %got_pc_hi20(g_156)
+; LA32-NEXT: ld.w $fp, $a0, %got_pc_lo12(g_156)
+; LA32-NEXT: pcalau12i $a0, %got_pc_hi20(g_490)
+; LA32-NEXT: ld.w $a0, $a0, %got_pc_lo12(g_490)
+; LA32-NEXT: ld.w $a1, $fp, 24
+; LA32-NEXT: pcalau12i $a2, %got_pc_hi20(g_813)
+; LA32-NEXT: ld.w $a2, $a2, %got_pc_lo12(g_813)
+; LA32-NEXT: st.w $zero, $fp, 20
+; LA32-NEXT: st.w $zero, $a0, 0
+; LA32-NEXT: st.w $a1, $a2, 0
+; LA32-NEXT: ori $a2, $zero, 48
+; LA32-NEXT: move $a0, $fp
+; LA32-NEXT: move $a1, $zero
+; LA32-NEXT: bl memset
+; LA32-NEXT: st.w $zero, $fp, 20
+; LA32-NEXT: ld.w $fp, $sp, 8 # 4-byte Folded Reload
+; LA32-NEXT: ld.w $ra, $sp, 12 # 4-byte Folded Reload
+; LA32-NEXT: addi.w $sp, $sp, 16
+; LA32-NEXT: ret
+;
+; LA64-LABEL: foo:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: pcalau12i $a0, %got_pc_hi20(g_156)
+; LA64-NEXT: ld.d $a0, $a0, %got_pc_lo12(g_156)
+; LA64-NEXT: pcalau12i $a1, %got_pc_hi20(g_490)
+; LA64-NEXT: ld.d $a1, $a1, %got_pc_lo12(g_490)
+; LA64-NEXT: ld.w $a2, $a0, 24
+; LA64-NEXT: pcalau12i $a3, %got_pc_hi20(g_813)
+; LA64-NEXT: ld.d $a3, $a3, %got_pc_lo12(g_813)
+; LA64-NEXT: st.w $zero, $a1, 0
+; LA64-NEXT: st.w $a2, $a3, 0
+; LA64-NEXT: xvrepli.b $xr0, 0
+; LA64-NEXT: xvst $xr0, $a0, 0
+; LA64-NEXT: vrepli.b $vr0, 0
+; LA64-NEXT: vst $vr0, $a0, 32
+; LA64-NEXT: st.w $zero, $a0, 20
+; LA64-NEXT: ret
entry:
store i32 0, ptr getelementptr inbounds (i8, ptr @g_156, i64 20), align 4
store i32 0, ptr @g_490, align 4
diff --git a/llvm/test/CodeGen/LoongArch/lasx/mulh.ll b/llvm/test/CodeGen/LoongArch/lasx/mulh.ll
index db3cc7f38774d..f99cc0a6cc333 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/mulh.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/mulh.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
define void @mulhs_v32i8(ptr %res, ptr %a0, ptr %a1) nounwind {
diff --git a/llvm/test/CodeGen/LoongArch/lasx/scalar-to-vector.ll b/llvm/test/CodeGen/LoongArch/lasx/scalar-to-vector.ll
index 05fbb746bd9d3..5593890bb7684 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/scalar-to-vector.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/scalar-to-vector.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA64
;; Test scalar_to_vector expansion.
@@ -31,10 +32,16 @@ define <8 x i32> @scalar_to_8xi32(i32 %val) {
}
define <4 x i64> @scalar_to_4xi64(i64 %val) {
-; CHECK-LABEL: scalar_to_4xi64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: xvinsgr2vr.d $xr0, $a0, 0
-; CHECK-NEXT: ret
+; LA32-LABEL: scalar_to_4xi64:
+; LA32: # %bb.0:
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a0, 0
+; LA32-NEXT: xvinsgr2vr.w $xr0, $a1, 1
+; LA32-NEXT: ret
+;
+; LA64-LABEL: scalar_to_4xi64:
+; LA64: # %bb.0:
+; LA64-NEXT: xvinsgr2vr.d $xr0, $a0, 0
+; LA64-NEXT: ret
%ret = insertelement <4 x i64> poison, i64 %val, i32 0
ret <4 x i64> %ret
}
diff --git a/llvm/test/CodeGen/LoongArch/lasx/vec-shuffle-bit-shift.ll b/llvm/test/CodeGen/LoongArch/lasx/vec-shuffle-bit-shift.ll
index 72e06f680e436..48a534f43a0d5 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/vec-shuffle-bit-shift.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/vec-shuffle-bit-shift.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
define <32 x i8> @shuffle_to_xvslli_h_8(<32 x i8> %a) nounwind {
diff --git a/llvm/test/CodeGen/LoongArch/lasx/vec-shuffle-byte-shift.ll b/llvm/test/CodeGen/LoongArch/lasx/vec-shuffle-byte-shift.ll
index 15bfce902f9dd..cea604e96bc10 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/vec-shuffle-byte-shift.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/vec-shuffle-byte-shift.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
define <32 x i8> @shuffle_32i8_byte_left_shift_1(<32 x i8> %a) {
diff --git a/llvm/test/CodeGen/LoongArch/lasx/vselect.ll b/llvm/test/CodeGen/LoongArch/lasx/vselect.ll
index 17ba28afc81f5..44e4f71c8d08d 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/vselect.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/vselect.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s --check-prefixes=CHECK,LA64
define void @select_v32i8_imm(ptr %res, ptr %a0) nounwind {
; CHECK-LABEL: select_v32i8_imm:
@@ -49,16 +50,26 @@ define void @select_v16i16(ptr %res, ptr %a0, ptr %a1) nounwind {
}
define void @select_v8i32(ptr %res, ptr %a0, ptr %a1) nounwind {
-; CHECK-LABEL: select_v8i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: xvld $xr0, $a1, 0
-; CHECK-NEXT: xvld $xr1, $a2, 0
-; CHECK-NEXT: ori $a1, $zero, 0
-; CHECK-NEXT: lu32i.d $a1, -1
-; CHECK-NEXT: xvreplgr2vr.d $xr2, $a1
-; CHECK-NEXT: xvbitsel.v $xr0, $xr1, $xr0, $xr2
-; CHECK-NEXT: xvst $xr0, $a0, 0
-; CHECK-NEXT: ret
+; LA32-LABEL: select_v8i32:
+; LA32: # %bb.0:
+; LA32-NEXT: xvld $xr0, $a1, 0
+; LA32-NEXT: xvld $xr1, $a2, 0
+; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI3_0)
+; LA32-NEXT: xvld $xr2, $a1, %pc_lo12(.LCPI3_0)
+; LA32-NEXT: xvbitsel.v $xr0, $xr1, $xr0, $xr2
+; LA32-NEXT: xvst $xr0, $a0, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: select_v8i32:
+; LA64: # %bb.0:
+; LA64-NEXT: xvld $xr0, $a1, 0
+; LA64-NEXT: xvld $xr1, $a2, 0
+; LA64-NEXT: ori $a1, $zero, 0
+; LA64-NEXT: lu32i.d $a1, -1
+; LA64-NEXT: xvreplgr2vr.d $xr2, $a1
+; LA64-NEXT: xvbitsel.v $xr0, $xr1, $xr0, $xr2
+; LA64-NEXT: xvst $xr0, $a0, 0
+; LA64-NEXT: ret
%v0 = load <8 x i32>, ptr %a0
%v1 = load <8 x i32>, ptr %a1
%sel = select <8 x i1> <i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true>, <8 x i32> %v0, <8 x i32> %v1
diff --git a/llvm/test/CodeGen/LoongArch/lasx/widen-shuffle-mask.ll b/llvm/test/CodeGen/LoongArch/lasx/widen-shuffle-mask.ll
index df639cb78cd1f..2efe96fe18d41 100644
--- a/llvm/test/CodeGen/LoongArch/lasx/widen-shuffle-mask.ll
+++ b/llvm/test/CodeGen/LoongArch/lasx/widen-shuffle-mask.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lasx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lasx < %s | FileCheck %s
define <32 x i8> @widen_shuffle_mask_v32i8_to_v16i16(<32 x i8> %a, <32 x i8> %b) {
diff --git a/llvm/test/CodeGen/LoongArch/lsx/broadcast-load.ll b/llvm/test/CodeGen/LoongArch/lsx/broadcast-load.ll
index c46747ef30509..12224f8d59b9f 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/broadcast-load.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/broadcast-load.ll
@@ -1,16 +1,29 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc --mtriple=loongarch64 -mattr=+lsx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 -mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32
+; RUN: llc --mtriple=loongarch64 -mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64
; TODO: Load a element and splat it to a vector could be lowerd to vldrepl
; A load has more than one user shouldn't be lowered to vldrepl
define <2 x i64> @should_not_be_optimized(ptr %ptr, ptr %dst){
-; CHECK-LABEL: should_not_be_optimized:
-; CHECK: # %bb.0:
-; CHECK-NEXT: ld.d $a0, $a0, 0
-; CHECK-NEXT: vreplgr2vr.d $vr0, $a0
-; CHECK-NEXT: st.d $a0, $a1, 0
-; CHECK-NEXT: ret
+; LA32-LABEL: should_not_be_optimized:
+; LA32: # %bb.0:
+; LA32-NEXT: ld.w $a2, $a0, 0
+; LA32-NEXT: ld.w $a0, $a0, 4
+; LA32-NEXT: st.w $a2, $a1, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 2
+; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 3
+; LA32-NEXT: st.w $a0, $a1, 4
+; LA32-NEXT: ret
+;
+; LA64-LABEL: should_not_be_optimized:
+; LA64: # %bb.0:
+; LA64-NEXT: ld.d $a0, $a0, 0
+; LA64-NEXT: vreplgr2vr.d $vr0, $a0
+; LA64-NEXT: st.d $a0, $a1, 0
+; LA64-NEXT: ret
%tmp = load i64, ptr %ptr
store i64 %tmp, ptr %dst
%tmp1 = insertelement <2 x i64> zeroinitializer, i64 %tmp, i32 0
@@ -19,11 +32,21 @@ define <2 x i64> @should_not_be_optimized(ptr %ptr, ptr %dst){
}
define <2 x i64> @vldrepl_d_unaligned_offset(ptr %ptr) {
-; CHECK-LABEL: vldrepl_d_unaligned_offset:
-; CHECK: # %bb.0:
-; CHECK-NEXT: addi.d $a0, $a0, 4
-; CHECK-NEXT: vldrepl.d $vr0, $a0, 0
-; CHECK-NEXT: ret
+; LA32-LABEL: vldrepl_d_unaligned_offset:
+; LA32: # %bb.0:
+; LA32-NEXT: ld.w $a1, $a0, 4
+; LA32-NEXT: ld.w $a0, $a0, 8
+; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 2
+; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 3
+; LA32-NEXT: ret
+;
+; LA64-LABEL: vldrepl_d_unaligned_offset:
+; LA64: # %bb.0:
+; LA64-NEXT: addi.d $a0, $a0, 4
+; LA64-NEXT: vldrepl.d $vr0, $a0, 0
+; LA64-NEXT: ret
%p = getelementptr i32, ptr %ptr, i32 1
%tmp = load i64, ptr %p
%tmp1 = insertelement <2 x i64> zeroinitializer, i64 %tmp, i32 0
@@ -102,10 +125,20 @@ define <4 x i32> @vldrepl_w_offset(ptr %ptr) {
}
define <2 x i64> @vldrepl_d(ptr %ptr) {
-; CHECK-LABEL: vldrepl_d:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vldrepl.d $vr0, $a0, 0
-; CHECK-NEXT: ret
+; LA32-LABEL: vldrepl_d:
+; LA32: # %bb.0:
+; LA32-NEXT: ld.w $a1, $a0, 0
+; LA32-NEXT: ld.w $a0, $a0, 4
+; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 2
+; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 3
+; LA32-NEXT: ret
+;
+; LA64-LABEL: vldrepl_d:
+; LA64: # %bb.0:
+; LA64-NEXT: vldrepl.d $vr0, $a0, 0
+; LA64-NEXT: ret
%tmp = load i64, ptr %ptr
%tmp1 = insertelement <2 x i64> zeroinitializer, i64 %tmp, i32 0
%tmp2 = shufflevector <2 x i64> %tmp1, <2 x i64> poison, <2 x i32> zeroinitializer
@@ -113,10 +146,20 @@ define <2 x i64> @vldrepl_d(ptr %ptr) {
}
define <2 x i64> @vldrepl_d_offset(ptr %ptr) {
-; CHECK-LABEL: vldrepl_d_offset:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vldrepl.d $vr0, $a0, 264
-; CHECK-NEXT: ret
+; LA32-LABEL: vldrepl_d_offset:
+; LA32: # %bb.0:
+; LA32-NEXT: ld.w $a1, $a0, 264
+; LA32-NEXT: ld.w $a0, $a0, 268
+; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 2
+; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 3
+; LA32-NEXT: ret
+;
+; LA64-LABEL: vldrepl_d_offset:
+; LA64: # %bb.0:
+; LA64-NEXT: vldrepl.d $vr0, $a0, 264
+; LA64-NEXT: ret
%p = getelementptr i64, ptr %ptr, i64 33
%tmp = load i64, ptr %p
%tmp1 = insertelement <2 x i64> zeroinitializer, i64 %tmp, i32 0
diff --git a/llvm/test/CodeGen/LoongArch/lsx/bswap.ll b/llvm/test/CodeGen/LoongArch/lsx/bswap.ll
index 8172e21eae34d..ecfb82627fe9d 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/bswap.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/bswap.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 -mattr=+32s,+lsx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 -mattr=+lsx < %s | FileCheck %s
define void @bswap_v8i16(ptr %src, ptr %dst) nounwind {
; CHECK-LABEL: bswap_v8i16:
diff --git a/llvm/test/CodeGen/LoongArch/lsx/build-vector.ll b/llvm/test/CodeGen/LoongArch/lsx/build-vector.ll
index 3d45686a8b619..abe954c70374e 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/build-vector.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/build-vector.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
define void @buildvector_v16i8_splat(ptr %dst, i8 %a0) nounwind {
@@ -41,11 +42,6 @@ entry:
}
define void @buildvector_v2i64_splat(ptr %dst, i64 %a0) nounwind {
-; CHECK-LABEL: buildvector_v2i64_splat:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vreplgr2vr.d $vr0, $a1
-; CHECK-NEXT: vst $vr0, $a0, 0
-; CHECK-NEXT: ret
entry:
%insert = insertelement <2 x i64> undef, i64 %a0, i8 0
%splat = shufflevector <2 x i64> %insert, <2 x i64> undef, <2 x i32> zeroinitializer
@@ -138,12 +134,6 @@ entry:
}
define void @buildvector_v2f64_const_splat(ptr %dst) nounwind {
-; CHECK-LABEL: buildvector_v2f64_const_splat:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: lu52i.d $a1, $zero, 1023
-; CHECK-NEXT: vreplgr2vr.d $vr0, $a1
-; CHECK-NEXT: vst $vr0, $a0, 0
-; CHECK-NEXT: ret
entry:
store <2 x double> <double 1.0, double 1.0>, ptr %dst
ret void
@@ -222,35 +212,6 @@ entry:
}
define void @buildvector_v16i8(ptr %dst, i8 %a0, i8 %a1, i8 %a2, i8 %a3, i8 %a4, i8 %a5, i8 %a6, i8 %a7, i8 %a8, i8 %a9, i8 %a10, i8 %a11, i8 %a12, i8 %a13, i8 %a14, i8 %a15) nounwind {
-; CHECK-LABEL: buildvector_v16i8:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: ld.b $t0, $sp, 64
-; CHECK-NEXT: ld.b $t1, $sp, 56
-; CHECK-NEXT: ld.b $t2, $sp, 48
-; CHECK-NEXT: ld.b $t3, $sp, 40
-; CHECK-NEXT: ld.b $t4, $sp, 32
-; CHECK-NEXT: ld.b $t5, $sp, 24
-; CHECK-NEXT: ld.b $t6, $sp, 16
-; CHECK-NEXT: ld.b $t7, $sp, 8
-; CHECK-NEXT: ld.b $t8, $sp, 0
-; CHECK-NEXT: vinsgr2vr.b $vr0, $a1, 0
-; CHECK-NEXT: vinsgr2vr.b $vr0, $a2, 1
-; CHECK-NEXT: vinsgr2vr.b $vr0, $a3, 2
-; CHECK-NEXT: vinsgr2vr.b $vr0, $a4, 3
-; CHECK-NEXT: vinsgr2vr.b $vr0, $a5, 4
-; CHECK-NEXT: vinsgr2vr.b $vr0, $a6, 5
-; CHECK-NEXT: vinsgr2vr.b $vr0, $a7, 6
-; CHECK-NEXT: vinsgr2vr.b $vr0, $t8, 7
-; CHECK-NEXT: vinsgr2vr.b $vr0, $t7, 8
-; CHECK-NEXT: vinsgr2vr.b $vr0, $t6, 9
-; CHECK-NEXT: vinsgr2vr.b $vr0, $t5, 10
-; CHECK-NEXT: vinsgr2vr.b $vr0, $t4, 11
-; CHECK-NEXT: vinsgr2vr.b $vr0, $t3, 12
-; CHECK-NEXT: vinsgr2vr.b $vr0, $t2, 13
-; CHECK-NEXT: vinsgr2vr.b $vr0, $t1, 14
-; CHECK-NEXT: vinsgr2vr.b $vr0, $t0, 15
-; CHECK-NEXT: vst $vr0, $a0, 0
-; CHECK-NEXT: ret
entry:
%ins0 = insertelement <16 x i8> undef, i8 %a0, i32 0
%ins1 = insertelement <16 x i8> %ins0, i8 %a1, i32 1
@@ -660,12 +621,6 @@ entry:
}
define void @buildvector_v2i64(ptr %dst, i64 %a0, i64 %a1) nounwind {
-; CHECK-LABEL: buildvector_v2i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vinsgr2vr.d $vr0, $a1, 0
-; CHECK-NEXT: vinsgr2vr.d $vr0, $a2, 1
-; CHECK-NEXT: vst $vr0, $a0, 0
-; CHECK-NEXT: ret
entry:
%ins0 = insertelement <2 x i64> undef, i64 %a0, i32 0
%ins1 = insertelement <2 x i64> %ins0, i64 %a1, i32 1
@@ -674,11 +629,6 @@ entry:
}
define void @buildvector_v2i64_partial(ptr %dst, i64 %a0) nounwind {
-; CHECK-LABEL: buildvector_v2i64_partial:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vinsgr2vr.d $vr0, $a1, 0
-; CHECK-NEXT: vst $vr0, $a0, 0
-; CHECK-NEXT: ret
entry:
%ins0 = insertelement <2 x i64> undef, i64 %a0, i32 0
%ins1 = insertelement <2 x i64> %ins0, i64 undef, i32 1
@@ -687,12 +637,6 @@ entry:
}
define void @buildvector_v2i64_with_constant(ptr %dst, i64 %a1) nounwind {
-; CHECK-LABEL: buildvector_v2i64_with_constant:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vrepli.b $vr0, 0
-; CHECK-NEXT: vinsgr2vr.d $vr0, $a1, 1
-; CHECK-NEXT: vst $vr0, $a0, 0
-; CHECK-NEXT: ret
entry:
%ins0 = insertelement <2 x i64> undef, i64 0, i32 0
%ins1 = insertelement <2 x i64> %ins0, i64 %a1, i32 1
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ctpop-ctlz.ll b/llvm/test/CodeGen/LoongArch/lsx/ctpop-ctlz.ll
index 5df553fba7ef7..a9a38e8f75f9c 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ctpop-ctlz.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ctpop-ctlz.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 -mattr=+32s,+lsx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 -mattr=+lsx < %s | FileCheck %s
define void @ctpop_v16i8(ptr %src, ptr %dst) nounwind {
; CHECK-LABEL: ctpop_v16i8:
diff --git a/llvm/test/CodeGen/LoongArch/lsx/fdiv-reciprocal-estimate.ll b/llvm/test/CodeGen/LoongArch/lsx/fdiv-reciprocal-estimate.ll
index 21dbbf310ad87..58e16d37ae278 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/fdiv-reciprocal-estimate.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/fdiv-reciprocal-estimate.ll
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; RUN: llc --mtriple=loongarch64 --mattr=+lsx,-frecipe < %s | FileCheck %s --check-prefix=FAULT
-; RUN: llc --mtriple=loongarch64 --mattr=+lsx,+frecipe < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx,-frecipe < %s | FileCheck %s --check-prefixes=FAULT,FAULT-LA32
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx,+frecipe < %s | FileCheck %s --check-prefixes=CHECK,LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx,-frecipe < %s | FileCheck %s --check-prefixes=FAULT,FAULT-LA64
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx,+frecipe < %s | FileCheck %s --check-prefixes=CHECK,LA64
define void @fdiv_v4f32(ptr %res, ptr %a0, ptr %a1) nounwind {
; FAULT-LABEL: fdiv_v4f32:
@@ -13,13 +15,13 @@ define void @fdiv_v4f32(ptr %res, ptr %a0, ptr %a1) nounwind {
;
; CHECK-LABEL: fdiv_v4f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vld $vr0, $a2, 0
-; CHECK-NEXT: vld $vr1, $a1, 0
-; CHECK-NEXT: vfrecipe.s $vr2, $vr0
-; CHECK-NEXT: vfmul.s $vr3, $vr1, $vr2
-; CHECK-NEXT: vfnmsub.s $vr0, $vr0, $vr3, $vr1
-; CHECK-NEXT: vfmadd.s $vr0, $vr2, $vr0, $vr3
-; CHECK-NEXT: vst $vr0, $a0, 0
+; CHECK-NEXT: vld $vr0, $a2, 0
+; CHECK-NEXT: vld $vr1, $a1, 0
+; CHECK-NEXT: vfrecipe.s $vr2, $vr0
+; CHECK-NEXT: vfmul.s $vr3, $vr1, $vr2
+; CHECK-NEXT: vfnmsub.s $vr0, $vr0, $vr3, $vr1
+; CHECK-NEXT: vfmadd.s $vr0, $vr2, $vr0, $vr3
+; CHECK-NEXT: vst $vr0, $a0, 0
; CHECK-NEXT: ret
entry:
%v0 = load <4 x float>, ptr %a0
@@ -38,20 +40,35 @@ define void @fdiv_v2f64(ptr %res, ptr %a0, ptr %a1) nounwind {
; FAULT-NEXT: vst $vr0, $a0, 0
; FAULT-NEXT: ret
;
-; CHECK-LABEL: fdiv_v2f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vld $vr0, $a2, 0
-; CHECK-NEXT: vld $vr1, $a1, 0
-; CHECK-NEXT: lu52i.d $a1, $zero, -1025
-; CHECK-NEXT: vreplgr2vr.d $vr2, $a1
-; CHECK-NEXT: vfrecipe.d $vr3, $vr0
-; CHECK-NEXT: vfmadd.d $vr2, $vr0, $vr3, $vr2
-; CHECK-NEXT: vfnmsub.d $vr2, $vr2, $vr3, $vr3
-; CHECK-NEXT: vfmul.d $vr3, $vr1, $vr2
-; CHECK-NEXT: vfnmsub.d $vr0, $vr0, $vr3, $vr1
-; CHECK-NEXT: vfmadd.d $vr0, $vr2, $vr0, $vr3
-; CHECK-NEXT: vst $vr0, $a0, 0
-; CHECK-NEXT: ret
+; LA32-LABEL: fdiv_v2f64:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: pcalau12i $a3, %pc_hi20(.LCPI1_0)
+; LA32-NEXT: vld $vr0, $a2, 0
+; LA32-NEXT: vld $vr1, $a3, %pc_lo12(.LCPI1_0)
+; LA32-NEXT: vld $vr2, $a1, 0
+; LA32-NEXT: vfrecipe.d $vr3, $vr0
+; LA32-NEXT: vfmadd.d $vr1, $vr0, $vr3, $vr1
+; LA32-NEXT: vfnmsub.d $vr1, $vr1, $vr3, $vr3
+; LA32-NEXT: vfmul.d $vr3, $vr2, $vr1
+; LA32-NEXT: vfnmsub.d $vr0, $vr0, $vr3, $vr2
+; LA32-NEXT: vfmadd.d $vr0, $vr1, $vr0, $vr3
+; LA32-NEXT: vst $vr0, $a0, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: fdiv_v2f64:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: vld $vr0, $a2, 0
+; LA64-NEXT: vld $vr1, $a1, 0
+; LA64-NEXT: lu52i.d $a1, $zero, -1025
+; LA64-NEXT: vreplgr2vr.d $vr2, $a1
+; LA64-NEXT: vfrecipe.d $vr3, $vr0
+; LA64-NEXT: vfmadd.d $vr2, $vr0, $vr3, $vr2
+; LA64-NEXT: vfnmsub.d $vr2, $vr2, $vr3, $vr3
+; LA64-NEXT: vfmul.d $vr3, $vr1, $vr2
+; LA64-NEXT: vfnmsub.d $vr0, $vr0, $vr3, $vr1
+; LA64-NEXT: vfmadd.d $vr0, $vr2, $vr0, $vr3
+; LA64-NEXT: vst $vr0, $a0, 0
+; LA64-NEXT: ret
entry:
%v0 = load <2 x double>, ptr %a0
%v1 = load <2 x double>, ptr %a1
@@ -71,13 +88,13 @@ define void @one_fdiv_v4f32(ptr %res, ptr %a0) nounwind {
;
; CHECK-LABEL: one_fdiv_v4f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vld $vr0, $a1, 0
-; CHECK-NEXT: vfrecipe.s $vr1, $vr0
-; CHECK-NEXT: lu12i.w $a1, -264192
-; CHECK-NEXT: vreplgr2vr.w $vr2, $a1
-; CHECK-NEXT: vfmadd.s $vr0, $vr0, $vr1, $vr2
-; CHECK-NEXT: vfnmsub.s $vr0, $vr0, $vr1, $vr1
-; CHECK-NEXT: vst $vr0, $a0, 0
+; CHECK-NEXT: vld $vr0, $a1, 0
+; CHECK-NEXT: vfrecipe.s $vr1, $vr0
+; CHECK-NEXT: lu12i.w $a1, -264192
+; CHECK-NEXT: vreplgr2vr.w $vr2, $a1
+; CHECK-NEXT: vfmadd.s $vr0, $vr0, $vr1, $vr2
+; CHECK-NEXT: vfnmsub.s $vr0, $vr0, $vr1, $vr1
+; CHECK-NEXT: vst $vr0, $a0, 0
; CHECK-NEXT: ret
entry:
%v0 = load <4 x float>, ptr %a0
@@ -87,25 +104,47 @@ entry:
}
define void @one_fdiv_v2f64(ptr %res, ptr %a0) nounwind {
-; FAULT-LABEL: one_fdiv_v2f64:
-; FAULT: # %bb.0: # %entry
-; FAULT-NEXT: vld $vr0, $a1, 0
-; FAULT-NEXT: vfrecip.d $vr0, $vr0
-; FAULT-NEXT: vst $vr0, $a0, 0
-; FAULT-NEXT: ret
+; FAULT-LA32-LABEL: one_fdiv_v2f64:
+; FAULT-LA32: # %bb.0: # %entry
+; FAULT-LA32-NEXT: vld $vr0, $a1, 0
+; FAULT-LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI3_0)
+; FAULT-LA32-NEXT: vld $vr1, $a1, %pc_lo12(.LCPI3_0)
+; FAULT-LA32-NEXT: vfdiv.d $vr0, $vr1, $vr0
+; FAULT-LA32-NEXT: vst $vr0, $a0, 0
+; FAULT-LA32-NEXT: ret
;
-; CHECK-LABEL: one_fdiv_v2f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vld $vr0, $a1, 0
-; CHECK-NEXT: vfrecipe.d $vr1, $vr0
-; CHECK-NEXT: lu52i.d $a1, $zero, 1023
-; CHECK-NEXT: vreplgr2vr.d $vr2, $a1
-; CHECK-NEXT: vfnmsub.d $vr3, $vr0, $vr1, $vr2
-; CHECK-NEXT: vfmadd.d $vr1, $vr1, $vr3, $vr1
-; CHECK-NEXT: vfnmsub.d $vr0, $vr0, $vr1, $vr2
-; CHECK-NEXT: vfmadd.d $vr0, $vr1, $vr0, $vr1
-; CHECK-NEXT: vst $vr0, $a0, 0
-; CHECK-NEXT: ret
+; LA32-LABEL: one_fdiv_v2f64:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: vld $vr0, $a1, 0
+; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI3_0)
+; LA32-NEXT: vld $vr1, $a1, %pc_lo12(.LCPI3_0)
+; LA32-NEXT: vfrecipe.d $vr2, $vr0
+; LA32-NEXT: vfnmsub.d $vr3, $vr0, $vr2, $vr1
+; LA32-NEXT: vfmadd.d $vr2, $vr2, $vr3, $vr2
+; LA32-NEXT: vfnmsub.d $vr0, $vr0, $vr2, $vr1
+; LA32-NEXT: vfmadd.d $vr0, $vr2, $vr0, $vr2
+; LA32-NEXT: vst $vr0, $a0, 0
+; LA32-NEXT: ret
+;
+; FAULT-LA64-LABEL: one_fdiv_v2f64:
+; FAULT-LA64: # %bb.0: # %entry
+; FAULT-LA64-NEXT: vld $vr0, $a1, 0
+; FAULT-LA64-NEXT: vfrecip.d $vr0, $vr0
+; FAULT-LA64-NEXT: vst $vr0, $a0, 0
+; FAULT-LA64-NEXT: ret
+;
+; LA64-LABEL: one_fdiv_v2f64:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: vld $vr0, $a1, 0
+; LA64-NEXT: vfrecipe.d $vr1, $vr0
+; LA64-NEXT: lu52i.d $a1, $zero, 1023
+; LA64-NEXT: vreplgr2vr.d $vr2, $a1
+; LA64-NEXT: vfnmsub.d $vr3, $vr0, $vr1, $vr2
+; LA64-NEXT: vfmadd.d $vr1, $vr1, $vr3, $vr1
+; LA64-NEXT: vfnmsub.d $vr0, $vr0, $vr1, $vr2
+; LA64-NEXT: vfmadd.d $vr0, $vr1, $vr0, $vr1
+; LA64-NEXT: vst $vr0, $a0, 0
+; LA64-NEXT: ret
entry:
%v0 = load <2 x double>, ptr %a0
%div = fdiv fast <2 x double> <double 1.0, double 1.0>, %v0
diff --git a/llvm/test/CodeGen/LoongArch/lsx/fma-v2f64.ll b/llvm/test/CodeGen/LoongArch/lsx/fma-v2f64.ll
index c83c563952d4f..89442908b31be 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/fma-v2f64.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/fma-v2f64.ll
@@ -1,8 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx --fp-contract=fast < %s \
+; RUN: | FileCheck %s --check-prefix=CONTRACT-FAST
; RUN: llc --mtriple=loongarch64 --mattr=+lsx --fp-contract=fast < %s \
; RUN: | FileCheck %s --check-prefix=CONTRACT-FAST
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx --fp-contract=on < %s \
+; RUN: | FileCheck %s --check-prefix=CONTRACT-ON
; RUN: llc --mtriple=loongarch64 --mattr=+lsx --fp-contract=on < %s \
; RUN: | FileCheck %s --check-prefix=CONTRACT-ON
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx --fp-contract=off < %s \
+; RUN: | FileCheck %s --check-prefix=CONTRACT-OFF
; RUN: llc --mtriple=loongarch64 --mattr=+lsx --fp-contract=off < %s \
; RUN: | FileCheck %s --check-prefix=CONTRACT-OFF
diff --git a/llvm/test/CodeGen/LoongArch/lsx/fma-v4f32.ll b/llvm/test/CodeGen/LoongArch/lsx/fma-v4f32.ll
index 1f316d5b1c8a4..0e5cd3cdcd35a 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/fma-v4f32.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/fma-v4f32.ll
@@ -1,8 +1,14 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx --fp-contract=fast < %s \
+; RUN: | FileCheck %s --check-prefix=CONTRACT-FAST
; RUN: llc --mtriple=loongarch64 --mattr=+lsx --fp-contract=fast < %s \
; RUN: | FileCheck %s --check-prefix=CONTRACT-FAST
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx --fp-contract=on < %s \
+; RUN: | FileCheck %s --check-prefix=CONTRACT-ON
; RUN: llc --mtriple=loongarch64 --mattr=+lsx --fp-contract=on < %s \
; RUN: | FileCheck %s --check-prefix=CONTRACT-ON
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx --fp-contract=off < %s \
+; RUN: | FileCheck %s --check-prefix=CONTRACT-OFF
; RUN: llc --mtriple=loongarch64 --mattr=+lsx --fp-contract=off < %s \
; RUN: | FileCheck %s --check-prefix=CONTRACT-OFF
diff --git a/llvm/test/CodeGen/LoongArch/lsx/fpowi.ll b/llvm/test/CodeGen/LoongArch/lsx/fpowi.ll
index 735dad453660e..8005318f4f620 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/fpowi.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/fpowi.ll
@@ -1,57 +1,102 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 -mattr=+32s,+lsx < %s | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 -mattr=+lsx < %s | FileCheck %s --check-prefix=LA64
declare <4 x float> @llvm.powi.v4f32.i32(<4 x float>, i32)
define <4 x float> @powi_v4f32(<4 x float> %va, i32 %b) nounwind {
-; CHECK-LABEL: powi_v4f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi.d $sp, $sp, -48
-; CHECK-NEXT: st.d $ra, $sp, 40 # 8-byte Folded Spill
-; CHECK-NEXT: st.d $fp, $sp, 32 # 8-byte Folded Spill
-; CHECK-NEXT: vst $vr0, $sp, 16 # 16-byte Folded Spill
-; CHECK-NEXT: addi.w $fp, $a0, 0
-; CHECK-NEXT: vreplvei.w $vr0, $vr0, 1
-; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
-; CHECK-NEXT: move $a0, $fp
-; CHECK-NEXT: pcaddu18i $ra, %call36(__powisf2)
-; CHECK-NEXT: jirl $ra, $ra, 0
-; CHECK-NEXT: # kill: def $f0 killed $f0 def $vr0
-; CHECK-NEXT: vst $vr0, $sp, 0 # 16-byte Folded Spill
-; CHECK-NEXT: vld $vr0, $sp, 16 # 16-byte Folded Reload
-; CHECK-NEXT: vreplvei.w $vr0, $vr0, 0
-; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
-; CHECK-NEXT: move $a0, $fp
-; CHECK-NEXT: pcaddu18i $ra, %call36(__powisf2)
-; CHECK-NEXT: jirl $ra, $ra, 0
-; CHECK-NEXT: # kill: def $f0 killed $f0 def $vr0
-; CHECK-NEXT: vld $vr1, $sp, 0 # 16-byte Folded Reload
-; CHECK-NEXT: vextrins.w $vr0, $vr1, 16
-; CHECK-NEXT: vst $vr0, $sp, 0 # 16-byte Folded Spill
-; CHECK-NEXT: vld $vr0, $sp, 16 # 16-byte Folded Reload
-; CHECK-NEXT: vreplvei.w $vr0, $vr0, 2
-; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
-; CHECK-NEXT: move $a0, $fp
-; CHECK-NEXT: pcaddu18i $ra, %call36(__powisf2)
-; CHECK-NEXT: jirl $ra, $ra, 0
-; CHECK-NEXT: # kill: def $f0 killed $f0 def $vr0
-; CHECK-NEXT: vld $vr1, $sp, 0 # 16-byte Folded Reload
-; CHECK-NEXT: vextrins.w $vr1, $vr0, 32
-; CHECK-NEXT: vst $vr1, $sp, 0 # 16-byte Folded Spill
-; CHECK-NEXT: vld $vr0, $sp, 16 # 16-byte Folded Reload
-; CHECK-NEXT: vreplvei.w $vr0, $vr0, 3
-; CHECK-NEXT: # kill: def $f0 killed $f0 killed $vr0
-; CHECK-NEXT: move $a0, $fp
-; CHECK-NEXT: pcaddu18i $ra, %call36(__powisf2)
-; CHECK-NEXT: jirl $ra, $ra, 0
-; CHECK-NEXT: # kill: def $f0 killed $f0 def $vr0
-; CHECK-NEXT: vld $vr1, $sp, 0 # 16-byte Folded Reload
-; CHECK-NEXT: vextrins.w $vr1, $vr0, 48
-; CHECK-NEXT: vori.b $vr0, $vr1, 0
-; CHECK-NEXT: ld.d $fp, $sp, 32 # 8-byte Folded Reload
-; CHECK-NEXT: ld.d $ra, $sp, 40 # 8-byte Folded Reload
-; CHECK-NEXT: addi.d $sp, $sp, 48
-; CHECK-NEXT: ret
+; LA32-LABEL: powi_v4f32:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: addi.w $sp, $sp, -48
+; LA32-NEXT: st.w $ra, $sp, 44 # 4-byte Folded Spill
+; LA32-NEXT: st.w $fp, $sp, 40 # 4-byte Folded Spill
+; LA32-NEXT: move $fp, $a0
+; LA32-NEXT: vst $vr0, $sp, 16 # 16-byte Folded Spill
+; LA32-NEXT: vreplvei.w $vr0, $vr0, 1
+; LA32-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; LA32-NEXT: bl __powisf2
+; LA32-NEXT: # kill: def $f0 killed $f0 def $vr0
+; LA32-NEXT: vst $vr0, $sp, 0 # 16-byte Folded Spill
+; LA32-NEXT: vld $vr0, $sp, 16 # 16-byte Folded Reload
+; LA32-NEXT: vreplvei.w $vr0, $vr0, 0
+; LA32-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; LA32-NEXT: move $a0, $fp
+; LA32-NEXT: bl __powisf2
+; LA32-NEXT: # kill: def $f0 killed $f0 def $vr0
+; LA32-NEXT: vld $vr1, $sp, 0 # 16-byte Folded Reload
+; LA32-NEXT: vextrins.w $vr0, $vr1, 16
+; LA32-NEXT: vst $vr0, $sp, 0 # 16-byte Folded Spill
+; LA32-NEXT: vld $vr0, $sp, 16 # 16-byte Folded Reload
+; LA32-NEXT: vreplvei.w $vr0, $vr0, 2
+; LA32-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; LA32-NEXT: move $a0, $fp
+; LA32-NEXT: bl __powisf2
+; LA32-NEXT: # kill: def $f0 killed $f0 def $vr0
+; LA32-NEXT: vld $vr1, $sp, 0 # 16-byte Folded Reload
+; LA32-NEXT: vextrins.w $vr1, $vr0, 32
+; LA32-NEXT: vst $vr1, $sp, 0 # 16-byte Folded Spill
+; LA32-NEXT: vld $vr0, $sp, 16 # 16-byte Folded Reload
+; LA32-NEXT: vreplvei.w $vr0, $vr0, 3
+; LA32-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; LA32-NEXT: move $a0, $fp
+; LA32-NEXT: bl __powisf2
+; LA32-NEXT: # kill: def $f0 killed $f0 def $vr0
+; LA32-NEXT: vld $vr1, $sp, 0 # 16-byte Folded Reload
+; LA32-NEXT: vextrins.w $vr1, $vr0, 48
+; LA32-NEXT: vori.b $vr0, $vr1, 0
+; LA32-NEXT: ld.w $fp, $sp, 40 # 4-byte Folded Reload
+; LA32-NEXT: ld.w $ra, $sp, 44 # 4-byte Folded Reload
+; LA32-NEXT: addi.w $sp, $sp, 48
+; LA32-NEXT: ret
+;
+; LA64-LABEL: powi_v4f32:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: addi.d $sp, $sp, -48
+; LA64-NEXT: st.d $ra, $sp, 40 # 8-byte Folded Spill
+; LA64-NEXT: st.d $fp, $sp, 32 # 8-byte Folded Spill
+; LA64-NEXT: vst $vr0, $sp, 16 # 16-byte Folded Spill
+; LA64-NEXT: addi.w $fp, $a0, 0
+; LA64-NEXT: vreplvei.w $vr0, $vr0, 1
+; LA64-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; LA64-NEXT: move $a0, $fp
+; LA64-NEXT: pcaddu18i $ra, %call36(__powisf2)
+; LA64-NEXT: jirl $ra, $ra, 0
+; LA64-NEXT: # kill: def $f0 killed $f0 def $vr0
+; LA64-NEXT: vst $vr0, $sp, 0 # 16-byte Folded Spill
+; LA64-NEXT: vld $vr0, $sp, 16 # 16-byte Folded Reload
+; LA64-NEXT: vreplvei.w $vr0, $vr0, 0
+; LA64-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; LA64-NEXT: move $a0, $fp
+; LA64-NEXT: pcaddu18i $ra, %call36(__powisf2)
+; LA64-NEXT: jirl $ra, $ra, 0
+; LA64-NEXT: # kill: def $f0 killed $f0 def $vr0
+; LA64-NEXT: vld $vr1, $sp, 0 # 16-byte Folded Reload
+; LA64-NEXT: vextrins.w $vr0, $vr1, 16
+; LA64-NEXT: vst $vr0, $sp, 0 # 16-byte Folded Spill
+; LA64-NEXT: vld $vr0, $sp, 16 # 16-byte Folded Reload
+; LA64-NEXT: vreplvei.w $vr0, $vr0, 2
+; LA64-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; LA64-NEXT: move $a0, $fp
+; LA64-NEXT: pcaddu18i $ra, %call36(__powisf2)
+; LA64-NEXT: jirl $ra, $ra, 0
+; LA64-NEXT: # kill: def $f0 killed $f0 def $vr0
+; LA64-NEXT: vld $vr1, $sp, 0 # 16-byte Folded Reload
+; LA64-NEXT: vextrins.w $vr1, $vr0, 32
+; LA64-NEXT: vst $vr1, $sp, 0 # 16-byte Folded Spill
+; LA64-NEXT: vld $vr0, $sp, 16 # 16-byte Folded Reload
+; LA64-NEXT: vreplvei.w $vr0, $vr0, 3
+; LA64-NEXT: # kill: def $f0 killed $f0 killed $vr0
+; LA64-NEXT: move $a0, $fp
+; LA64-NEXT: pcaddu18i $ra, %call36(__powisf2)
+; LA64-NEXT: jirl $ra, $ra, 0
+; LA64-NEXT: # kill: def $f0 killed $f0 def $vr0
+; LA64-NEXT: vld $vr1, $sp, 0 # 16-byte Folded Reload
+; LA64-NEXT: vextrins.w $vr1, $vr0, 48
+; LA64-NEXT: vori.b $vr0, $vr1, 0
+; LA64-NEXT: ld.d $fp, $sp, 32 # 8-byte Folded Reload
+; LA64-NEXT: ld.d $ra, $sp, 40 # 8-byte Folded Reload
+; LA64-NEXT: addi.d $sp, $sp, 48
+; LA64-NEXT: ret
entry:
%res = call <4 x float> @llvm.powi.v4f32.i32(<4 x float> %va, i32 %b)
ret <4 x float> %res
@@ -60,33 +105,58 @@ entry:
declare <2 x double> @llvm.powi.v2f64.i32(<2 x double>, i32)
define <2 x double> @powi_v2f64(<2 x double> %va, i32 %b) nounwind {
-; CHECK-LABEL: powi_v2f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi.d $sp, $sp, -48
-; CHECK-NEXT: st.d $ra, $sp, 40 # 8-byte Folded Spill
-; CHECK-NEXT: st.d $fp, $sp, 32 # 8-byte Folded Spill
-; CHECK-NEXT: vst $vr0, $sp, 0 # 16-byte Folded Spill
-; CHECK-NEXT: addi.w $fp, $a0, 0
-; CHECK-NEXT: vreplvei.d $vr0, $vr0, 1
-; CHECK-NEXT: # kill: def $f0_64 killed $f0_64 killed $vr0
-; CHECK-NEXT: move $a0, $fp
-; CHECK-NEXT: pcaddu18i $ra, %call36(__powidf2)
-; CHECK-NEXT: jirl $ra, $ra, 0
-; CHECK-NEXT: # kill: def $f0_64 killed $f0_64 def $vr0
-; CHECK-NEXT: vst $vr0, $sp, 16 # 16-byte Folded Spill
-; CHECK-NEXT: vld $vr0, $sp, 0 # 16-byte Folded Reload
-; CHECK-NEXT: vreplvei.d $vr0, $vr0, 0
-; CHECK-NEXT: # kill: def $f0_64 killed $f0_64 killed $vr0
-; CHECK-NEXT: move $a0, $fp
-; CHECK-NEXT: pcaddu18i $ra, %call36(__powidf2)
-; CHECK-NEXT: jirl $ra, $ra, 0
-; CHECK-NEXT: # kill: def $f0_64 killed $f0_64 def $vr0
-; CHECK-NEXT: vld $vr1, $sp, 16 # 16-byte Folded Reload
-; CHECK-NEXT: vextrins.d $vr0, $vr1, 16
-; CHECK-NEXT: ld.d $fp, $sp, 32 # 8-byte Folded Reload
-; CHECK-NEXT: ld.d $ra, $sp, 40 # 8-byte Folded Reload
-; CHECK-NEXT: addi.d $sp, $sp, 48
-; CHECK-NEXT: ret
+; LA32-LABEL: powi_v2f64:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: addi.w $sp, $sp, -48
+; LA32-NEXT: st.w $ra, $sp, 44 # 4-byte Folded Spill
+; LA32-NEXT: st.w $fp, $sp, 40 # 4-byte Folded Spill
+; LA32-NEXT: move $fp, $a0
+; LA32-NEXT: vst $vr0, $sp, 0 # 16-byte Folded Spill
+; LA32-NEXT: vreplvei.d $vr0, $vr0, 1
+; LA32-NEXT: # kill: def $f0_64 killed $f0_64 killed $vr0
+; LA32-NEXT: bl __powidf2
+; LA32-NEXT: # kill: def $f0_64 killed $f0_64 def $vr0
+; LA32-NEXT: vst $vr0, $sp, 16 # 16-byte Folded Spill
+; LA32-NEXT: vld $vr0, $sp, 0 # 16-byte Folded Reload
+; LA32-NEXT: vreplvei.d $vr0, $vr0, 0
+; LA32-NEXT: # kill: def $f0_64 killed $f0_64 killed $vr0
+; LA32-NEXT: move $a0, $fp
+; LA32-NEXT: bl __powidf2
+; LA32-NEXT: # kill: def $f0_64 killed $f0_64 def $vr0
+; LA32-NEXT: vld $vr1, $sp, 16 # 16-byte Folded Reload
+; LA32-NEXT: vextrins.d $vr0, $vr1, 16
+; LA32-NEXT: ld.w $fp, $sp, 40 # 4-byte Folded Reload
+; LA32-NEXT: ld.w $ra, $sp, 44 # 4-byte Folded Reload
+; LA32-NEXT: addi.w $sp, $sp, 48
+; LA32-NEXT: ret
+;
+; LA64-LABEL: powi_v2f64:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: addi.d $sp, $sp, -48
+; LA64-NEXT: st.d $ra, $sp, 40 # 8-byte Folded Spill
+; LA64-NEXT: st.d $fp, $sp, 32 # 8-byte Folded Spill
+; LA64-NEXT: vst $vr0, $sp, 0 # 16-byte Folded Spill
+; LA64-NEXT: addi.w $fp, $a0, 0
+; LA64-NEXT: vreplvei.d $vr0, $vr0, 1
+; LA64-NEXT: # kill: def $f0_64 killed $f0_64 killed $vr0
+; LA64-NEXT: move $a0, $fp
+; LA64-NEXT: pcaddu18i $ra, %call36(__powidf2)
+; LA64-NEXT: jirl $ra, $ra, 0
+; LA64-NEXT: # kill: def $f0_64 killed $f0_64 def $vr0
+; LA64-NEXT: vst $vr0, $sp, 16 # 16-byte Folded Spill
+; LA64-NEXT: vld $vr0, $sp, 0 # 16-byte Folded Reload
+; LA64-NEXT: vreplvei.d $vr0, $vr0, 0
+; LA64-NEXT: # kill: def $f0_64 killed $f0_64 killed $vr0
+; LA64-NEXT: move $a0, $fp
+; LA64-NEXT: pcaddu18i $ra, %call36(__powidf2)
+; LA64-NEXT: jirl $ra, $ra, 0
+; LA64-NEXT: # kill: def $f0_64 killed $f0_64 def $vr0
+; LA64-NEXT: vld $vr1, $sp, 16 # 16-byte Folded Reload
+; LA64-NEXT: vextrins.d $vr0, $vr1, 16
+; LA64-NEXT: ld.d $fp, $sp, 32 # 8-byte Folded Reload
+; LA64-NEXT: ld.d $ra, $sp, 40 # 8-byte Folded Reload
+; LA64-NEXT: addi.d $sp, $sp, 48
+; LA64-NEXT: ret
entry:
%res = call <2 x double> @llvm.powi.v2f64.i32(<2 x double> %va, i32 %b)
ret <2 x double> %res
diff --git a/llvm/test/CodeGen/LoongArch/lsx/fsqrt-reciprocal-estimate.ll b/llvm/test/CodeGen/LoongArch/lsx/fsqrt-reciprocal-estimate.ll
index 912d06242f7d3..1f744830bd56b 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/fsqrt-reciprocal-estimate.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/fsqrt-reciprocal-estimate.ll
@@ -1,6 +1,8 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc --mtriple=loongarch64 --mattr=+lsx,-frecipe < %s | FileCheck %s --check-prefix=FAULT
-; RUN: llc --mtriple=loongarch64 --mattr=+lsx,+frecipe < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx,-frecipe < %s | FileCheck %s --check-prefixes=FAULT,FAULT-LA32
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx,+frecipe < %s | FileCheck %s --check-prefixes=CHECK,LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx,-frecipe < %s | FileCheck %s --check-prefixes=FAULT,FAULT-LA64
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx,+frecipe < %s | FileCheck %s --check-prefixes=CHECK,LA64
;; 1.0 / (fsqrt vec)
define void @one_div_sqrt_v4f32(ptr %res, ptr %a0) nounwind {
@@ -11,20 +13,20 @@ define void @one_div_sqrt_v4f32(ptr %res, ptr %a0) nounwind {
; FAULT-NEXT: vst $vr0, $a0, 0
; FAULT-NEXT: ret
;
-; CHECK-LABEL one_div_sqrt_v4f32:
+; CHECK-LABEL: one_div_sqrt_v4f32:
; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vld $vr0, $a1, 0
-; CHECK-NEXT: vfrsqrte.s $vr1, $vr0
-; CHECK-NEXT: vfmul.s $vr1, $vr0, $vr1
-; CHECK-NEXT: vfmul.s $vr0, $vr0, $vr1
-; CHECK-NEXT: lu12i.w $a1, -261120
-; CHECK-NEXT: vreplgr2vr.w $vr2, $a1
-; CHECK-NEXT: vfmadd.s $vr0, $vr0, $vr1, $vr2
-; CHECK-NEXT: lu12i.w $a1, -266240
-; CHECK-NEXT: vreplgr2vr.w $vr2, $a1
-; CHECK-NEXT: vfmul.s $vr1, $vr1, $vr2
-; CHECK-NEXT: vfmul.s $vr0, $vr1, $vr0
-; CHECK-NEXT: vst $vr0, $a0, 0
+; CHECK-NEXT: vld $vr0, $a1, 0
+; CHECK-NEXT: vfrsqrte.s $vr1, $vr0
+; CHECK-NEXT: vfmul.s $vr1, $vr0, $vr1
+; CHECK-NEXT: vfmul.s $vr0, $vr0, $vr1
+; CHECK-NEXT: lu12i.w $a1, -261120
+; CHECK-NEXT: vreplgr2vr.w $vr2, $a1
+; CHECK-NEXT: vfmadd.s $vr0, $vr0, $vr1, $vr2
+; CHECK-NEXT: lu12i.w $a1, -266240
+; CHECK-NEXT: vreplgr2vr.w $vr2, $a1
+; CHECK-NEXT: vfmul.s $vr1, $vr1, $vr2
+; CHECK-NEXT: vfmul.s $vr0, $vr1, $vr0
+; CHECK-NEXT: vst $vr0, $a0, 0
; CHECK-NEXT: ret
entry:
%v0 = load <4 x float>, ptr %a0, align 16
@@ -35,34 +37,64 @@ entry:
}
define void @one_div_sqrt_v2f64(ptr %res, ptr %a0) nounwind {
-; FAULT-LABEL: one_div_sqrt_v2f64:
-; FAULT: # %bb.0: # %entry
-; FAULT-NEXT: vld $vr0, $a1, 0
-; FAULT-NEXT: vfrsqrt.d $vr0, $vr0
-; FAULT-NEXT: vst $vr0, $a0, 0
-; FAULT-NEXT: ret
+; FAULT-LA32-LABEL: one_div_sqrt_v2f64:
+; FAULT-LA32: # %bb.0: # %entry
+; FAULT-LA32-NEXT: vld $vr0, $a1, 0
+; FAULT-LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI1_0)
+; FAULT-LA32-NEXT: vld $vr1, $a1, %pc_lo12(.LCPI1_0)
+; FAULT-LA32-NEXT: vfsqrt.d $vr0, $vr0
+; FAULT-LA32-NEXT: vfdiv.d $vr0, $vr1, $vr0
+; FAULT-LA32-NEXT: vst $vr0, $a0, 0
+; FAULT-LA32-NEXT: ret
;
-; CHECK-LABEL one_div_sqrt_v2f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vld $vr0, $a1, 0
-; CHECK-NEXT: vfrsqrte.d $vr1, $vr0
-; CHECK-NEXT: vfmul.d $vr1, $vr0, $vr1
-; CHECK-NEXT: vfmul.d $vr2, $vr0, $vr1
-; CHECK-NEXT: ori $a1, $zero, 0
-; CHECK-NEXT: lu32i.d $a1, -524288
-; CHECK-NEXT: lu52i.d $a1, $a1, -1024
-; CHECK-NEXT: vreplgr2vr.d $vr3, $a1
-; CHECK-NEXT: vfmadd.d $vr2, $vr2, $vr1, $vr3
-; CHECK-NEXT: lu52i.d $a1, $zero, -1026
-; CHECK-NEXT: vreplgr2vr.d $vr4, $a1
-; CHECK-NEXT: vfmul.d $vr1, $vr1, $vr4
-; CHECK-NEXT: vfmul.d $vr1, $vr1, $vr2
-; CHECK-NEXT: vfmul.d $vr0, $vr0, $vr1
-; CHECK-NEXT: vfmadd.d $vr0, $vr0, $vr1, $vr3
-; CHECK-NEXT: vfmul.d $vr1, $vr1, $vr4
-; CHECK-NEXT: vfmul.d $vr0, $vr1, $vr0
-; CHECK-NEXT: vst $vr0, $a0, 0
-; CHECK-NEXT: ret
+; LA32-LABEL: one_div_sqrt_v2f64:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: vld $vr0, $a1, 0
+; LA32-NEXT: vfrsqrte.d $vr1, $vr0
+; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI1_0)
+; LA32-NEXT: vld $vr2, $a1, %pc_lo12(.LCPI1_0)
+; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI1_1)
+; LA32-NEXT: vld $vr3, $a1, %pc_lo12(.LCPI1_1)
+; LA32-NEXT: vfmul.d $vr1, $vr0, $vr1
+; LA32-NEXT: vfmul.d $vr4, $vr0, $vr1
+; LA32-NEXT: vfmadd.d $vr4, $vr4, $vr1, $vr2
+; LA32-NEXT: vfmul.d $vr1, $vr1, $vr3
+; LA32-NEXT: vfmul.d $vr1, $vr1, $vr4
+; LA32-NEXT: vfmul.d $vr0, $vr0, $vr1
+; LA32-NEXT: vfmadd.d $vr0, $vr0, $vr1, $vr2
+; LA32-NEXT: vfmul.d $vr1, $vr1, $vr3
+; LA32-NEXT: vfmul.d $vr0, $vr1, $vr0
+; LA32-NEXT: vst $vr0, $a0, 0
+; LA32-NEXT: ret
+;
+; FAULT-LA64-LABEL: one_div_sqrt_v2f64:
+; FAULT-LA64: # %bb.0: # %entry
+; FAULT-LA64-NEXT: vld $vr0, $a1, 0
+; FAULT-LA64-NEXT: vfrsqrt.d $vr0, $vr0
+; FAULT-LA64-NEXT: vst $vr0, $a0, 0
+; FAULT-LA64-NEXT: ret
+;
+; LA64-LABEL: one_div_sqrt_v2f64:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: vld $vr0, $a1, 0
+; LA64-NEXT: vfrsqrte.d $vr1, $vr0
+; LA64-NEXT: vfmul.d $vr1, $vr0, $vr1
+; LA64-NEXT: vfmul.d $vr2, $vr0, $vr1
+; LA64-NEXT: ori $a1, $zero, 0
+; LA64-NEXT: lu32i.d $a1, -524288
+; LA64-NEXT: lu52i.d $a1, $a1, -1024
+; LA64-NEXT: vreplgr2vr.d $vr3, $a1
+; LA64-NEXT: vfmadd.d $vr2, $vr2, $vr1, $vr3
+; LA64-NEXT: lu52i.d $a1, $zero, -1026
+; LA64-NEXT: vreplgr2vr.d $vr4, $a1
+; LA64-NEXT: vfmul.d $vr1, $vr1, $vr4
+; LA64-NEXT: vfmul.d $vr1, $vr1, $vr2
+; LA64-NEXT: vfmul.d $vr0, $vr0, $vr1
+; LA64-NEXT: vfmadd.d $vr0, $vr0, $vr1, $vr3
+; LA64-NEXT: vfmul.d $vr1, $vr1, $vr4
+; LA64-NEXT: vfmul.d $vr0, $vr1, $vr0
+; LA64-NEXT: vst $vr0, $a0, 0
+; LA64-NEXT: ret
entry:
%v0 = load <2 x double>, ptr %a0, align 16
%sqrt = call fast <2 x double> @llvm.sqrt.v2f64 (<2 x double> %v0)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/fsqrt.ll b/llvm/test/CodeGen/LoongArch/lsx/fsqrt.ll
index a57bc1ca0e948..d88e0d1ea7c2d 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/fsqrt.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/fsqrt.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64
;; fsqrt
define void @sqrt_v4f32(ptr %res, ptr %a0) nounwind {
@@ -47,12 +48,22 @@ entry:
}
define void @one_div_sqrt_v2f64(ptr %res, ptr %a0) nounwind {
-; CHECK-LABEL: one_div_sqrt_v2f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vld $vr0, $a1, 0
-; CHECK-NEXT: vfrsqrt.d $vr0, $vr0
-; CHECK-NEXT: vst $vr0, $a0, 0
-; CHECK-NEXT: ret
+; LA32-LABEL: one_div_sqrt_v2f64:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: vld $vr0, $a1, 0
+; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI3_0)
+; LA32-NEXT: vld $vr1, $a1, %pc_lo12(.LCPI3_0)
+; LA32-NEXT: vfsqrt.d $vr0, $vr0
+; LA32-NEXT: vfdiv.d $vr0, $vr1, $vr0
+; LA32-NEXT: vst $vr0, $a0, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: one_div_sqrt_v2f64:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: vld $vr0, $a1, 0
+; LA64-NEXT: vfrsqrt.d $vr0, $vr0
+; LA64-NEXT: vst $vr0, $a0, 0
+; LA64-NEXT: ret
entry:
%v0 = load <2 x double>, ptr %a0, align 16
%sqrt = call <2 x double> @llvm.sqrt.v2f64 (<2 x double> %v0)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/inline-asm-operand-modifier.ll b/llvm/test/CodeGen/LoongArch/lsx/inline-asm-operand-modifier.ll
index c46e624ddaa82..951ccbe4d08c9 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/inline-asm-operand-modifier.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/inline-asm-operand-modifier.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 -mattr=+32s,+lsx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch64 -mattr=+lsx < %s | FileCheck %s
define void @test_w() nounwind {
; CHECK-LABEL: test_w:
diff --git a/llvm/test/CodeGen/LoongArch/lsx/inline-asm-reg-names.ll b/llvm/test/CodeGen/LoongArch/lsx/inline-asm-reg-names.ll
index ceea3621be2f6..eacfca88fc748 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/inline-asm-reg-names.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/inline-asm-reg-names.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
-; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 -mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32
+; RUN: llc --mtriple=loongarch64 -mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64
define void @register_vr1() nounwind {
; CHECK-LABEL: register_vr1:
@@ -42,16 +43,27 @@ entry:
;; register which is preserved across calls. That's why the
;; fst.d and fld.d instructions are emitted.
define void @register_vr31() nounwind {
-; CHECK-LABEL: register_vr31:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: addi.d $sp, $sp, -16
-; CHECK-NEXT: fst.d $fs7, $sp, 8 # 8-byte Folded Spill
-; CHECK-NEXT: #APP
-; CHECK-NEXT: vldi $vr31, 1
-; CHECK-NEXT: #NO_APP
-; CHECK-NEXT: fld.d $fs7, $sp, 8 # 8-byte Folded Reload
-; CHECK-NEXT: addi.d $sp, $sp, 16
-; CHECK-NEXT: ret
+; LA32-LABEL: register_vr31:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: addi.w $sp, $sp, -16
+; LA32-NEXT: fst.d $fs7, $sp, 8 # 8-byte Folded Spill
+; LA32-NEXT: #APP
+; LA32-NEXT: vldi $vr31, 1
+; LA32-NEXT: #NO_APP
+; LA32-NEXT: fld.d $fs7, $sp, 8 # 8-byte Folded Reload
+; LA32-NEXT: addi.w $sp, $sp, 16
+; LA32-NEXT: ret
+;
+; LA64-LABEL: register_vr31:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: addi.d $sp, $sp, -16
+; LA64-NEXT: fst.d $fs7, $sp, 8 # 8-byte Folded Spill
+; LA64-NEXT: #APP
+; LA64-NEXT: vldi $vr31, 1
+; LA64-NEXT: #NO_APP
+; LA64-NEXT: fld.d $fs7, $sp, 8 # 8-byte Folded Reload
+; LA64-NEXT: addi.d $sp, $sp, 16
+; LA64-NEXT: ret
entry:
%0 = tail call <2 x i64> asm sideeffect "vldi ${0:w}, 1", "={$vr31}"()
ret void
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-absd.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-absd.ll
index 811d9d712de4e..0b3c559ef97d7 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-absd.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-absd.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vabsd.b(<16 x i8>, <16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-add.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-add.ll
index fac16c8308daf..daaed8388bca2 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-add.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-add.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vadd.b(<16 x i8>, <16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-adda.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-adda.ll
index 79be0a184bfb1..c2d5264d54415 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-adda.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-adda.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vadda.b(<16 x i8>, <16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-addi-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-addi-invalid-imm.ll
index 6875872b6f83b..a1fa4f3449b26 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-addi-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-addi-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vaddi.bu(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-addi-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-addi-non-imm.ll
index 87d32b3ce02a8..19100bc1426c7 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-addi-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-addi-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vaddi.bu(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-addi.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-addi.ll
index b9134e0724fe4..68ce36ccd8018 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-addi.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-addi.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vaddi.bu(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-addw.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-addw.ll
index 086e3bec12d23..3951e121bdc66 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-addw.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-addw.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <8 x i16> @llvm.loongarch.lsx.vaddwev.h.b(<16 x i8>, <16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-and.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-and.ll
index 77496239c3a9f..6fe22ea83b7d2 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-and.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-and.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vand.v(<16 x i8>, <16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-andi-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-andi-invalid-imm.ll
index 82a117b2aba57..f36b2f39bc1e1 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-andi-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-andi-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vandi.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-andi-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-andi-non-imm.ll
index c0c35c775266d..43f60d9e56e4e 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-andi-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-andi-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vandi.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-andi.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-andi.ll
index 9a1c38a641d05..f6966213e32f5 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-andi.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-andi.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vandi.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-andn.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-andn.ll
index b08c759ecc322..2484051943c48 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-andn.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-andn.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vandn.v(<16 x i8>, <16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-avg.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-avg.ll
index fb0861f4cd5ee..189e95ccb0c0f 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-avg.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-avg.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vavg.b(<16 x i8>, <16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-avgr.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-avgr.ll
index 8bf7d0ed88173..0675361263e2e 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-avgr.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-avgr.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vavgr.b(<16 x i8>, <16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitclr-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitclr-invalid-imm.ll
index b020806cd86cb..3b968483dee87 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitclr-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitclr-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vbitclri.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitclr-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitclr-non-imm.ll
index df6cdb99cdbcb..335dd66ba740b 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitclr-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitclr-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vbitclri.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitclr.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitclr.ll
index f5fba6dbb1414..ac0eca2fc33ea 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitclr.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitclr.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64
declare <16 x i8> @llvm.loongarch.lsx.vbitclr.b(<16 x i8>, <16 x i8>)
@@ -40,10 +41,21 @@ entry:
declare <2 x i64> @llvm.loongarch.lsx.vbitclr.d(<2 x i64>, <2 x i64>)
define <2 x i64> @lsx_vbitclr_d(<2 x i64> %va, <2 x i64> %vb) nounwind {
-; CHECK-LABEL: lsx_vbitclr_d:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vbitclr.d $vr0, $vr0, $vr1
-; CHECK-NEXT: ret
+; LA32-LABEL: lsx_vbitclr_d:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: vrepli.d $vr2, 63
+; LA32-NEXT: vand.v $vr1, $vr1, $vr2
+; LA32-NEXT: vrepli.d $vr2, 1
+; LA32-NEXT: vsll.d $vr1, $vr2, $vr1
+; LA32-NEXT: vrepli.b $vr2, -1
+; LA32-NEXT: vxor.v $vr1, $vr1, $vr2
+; LA32-NEXT: vand.v $vr0, $vr0, $vr1
+; LA32-NEXT: ret
+;
+; LA64-LABEL: lsx_vbitclr_d:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: vbitclr.d $vr0, $vr0, $vr1
+; LA64-NEXT: ret
entry:
%res = call <2 x i64> @llvm.loongarch.lsx.vbitclr.d(<2 x i64> %va, <2 x i64> %vb)
ret <2 x i64> %res
@@ -88,10 +100,17 @@ entry:
declare <2 x i64> @llvm.loongarch.lsx.vbitclri.d(<2 x i64>, i32)
define <2 x i64> @lsx_vbitclri_d(<2 x i64> %va) nounwind {
-; CHECK-LABEL: lsx_vbitclri_d:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vbitclri.d $vr0, $vr0, 63
-; CHECK-NEXT: ret
+; LA32-LABEL: lsx_vbitclri_d:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: pcalau12i $a0, %pc_hi20(.LCPI7_0)
+; LA32-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI7_0)
+; LA32-NEXT: vand.v $vr0, $vr0, $vr1
+; LA32-NEXT: ret
+;
+; LA64-LABEL: lsx_vbitclri_d:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: vbitclri.d $vr0, $vr0, 63
+; LA64-NEXT: ret
entry:
%res = call <2 x i64> @llvm.loongarch.lsx.vbitclri.d(<2 x i64> %va, i32 63)
ret <2 x i64> %res
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitrev-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitrev-invalid-imm.ll
index 24b6ec3284cb8..a664bdebf642b 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitrev-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitrev-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vbitrevi.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitrev-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitrev-non-imm.ll
index 3ffb494c9907a..379ba45863a91 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitrev-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitrev-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vbitrevi.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitrev.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitrev.ll
index ad56e88fdb882..ece12db99ce2c 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitrev.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitrev.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64
declare <16 x i8> @llvm.loongarch.lsx.vbitrev.b(<16 x i8>, <16 x i8>)
@@ -40,10 +41,19 @@ entry:
declare <2 x i64> @llvm.loongarch.lsx.vbitrev.d(<2 x i64>, <2 x i64>)
define <2 x i64> @lsx_vbitrev_d(<2 x i64> %va, <2 x i64> %vb) nounwind {
-; CHECK-LABEL: lsx_vbitrev_d:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vbitrev.d $vr0, $vr0, $vr1
-; CHECK-NEXT: ret
+; LA32-LABEL: lsx_vbitrev_d:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: vrepli.d $vr2, 63
+; LA32-NEXT: vand.v $vr1, $vr1, $vr2
+; LA32-NEXT: vrepli.d $vr2, 1
+; LA32-NEXT: vsll.d $vr1, $vr2, $vr1
+; LA32-NEXT: vxor.v $vr0, $vr0, $vr1
+; LA32-NEXT: ret
+;
+; LA64-LABEL: lsx_vbitrev_d:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: vbitrev.d $vr0, $vr0, $vr1
+; LA64-NEXT: ret
entry:
%res = call <2 x i64> @llvm.loongarch.lsx.vbitrev.d(<2 x i64> %va, <2 x i64> %vb)
ret <2 x i64> %res
@@ -88,10 +98,17 @@ entry:
declare <2 x i64> @llvm.loongarch.lsx.vbitrevi.d(<2 x i64>, i32)
define <2 x i64> @lsx_vbitrevi_d(<2 x i64> %va) nounwind {
-; CHECK-LABEL: lsx_vbitrevi_d:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vbitrevi.d $vr0, $vr0, 63
-; CHECK-NEXT: ret
+; LA32-LABEL: lsx_vbitrevi_d:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: pcalau12i $a0, %pc_hi20(.LCPI7_0)
+; LA32-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI7_0)
+; LA32-NEXT: vxor.v $vr0, $vr0, $vr1
+; LA32-NEXT: ret
+;
+; LA64-LABEL: lsx_vbitrevi_d:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: vbitrevi.d $vr0, $vr0, 63
+; LA64-NEXT: ret
entry:
%res = call <2 x i64> @llvm.loongarch.lsx.vbitrevi.d(<2 x i64> %va, i32 63)
ret <2 x i64> %res
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitsel.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitsel.ll
index 4b4b5ff1fc8cd..23caf9c128363 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitsel.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitsel.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vbitsel.v(<16 x i8>, <16 x i8>, <16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitseli-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitseli-invalid-imm.ll
index bc63b40e9fca7..5fa9db3bd0ea9 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitseli-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitseli-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vbitseli.b(<16 x i8>, <16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitseli-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitseli-non-imm.ll
index 52c1eb7d20243..05724df0a3ddc 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitseli-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitseli-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vbitseli.b(<16 x i8>, <16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitseli.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitseli.ll
index 28d342b5c378f..93111bc86c2b1 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitseli.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitseli.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vbitseli.b(<16 x i8>, <16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitset-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitset-invalid-imm.ll
index e57e14d8cb077..089c192b567a2 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitset-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitset-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vbitseti.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitset-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitset-non-imm.ll
index 9b2bde015ed93..182c46078505b 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitset-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitset-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vbitseti.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitset.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitset.ll
index 75d98e6f8bce1..b01e533a1c8b6 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitset.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bitset.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64
declare <16 x i8> @llvm.loongarch.lsx.vbitset.b(<16 x i8>, <16 x i8>)
@@ -40,10 +41,19 @@ entry:
declare <2 x i64> @llvm.loongarch.lsx.vbitset.d(<2 x i64>, <2 x i64>)
define <2 x i64> @lsx_vbitset_d(<2 x i64> %va, <2 x i64> %vb) nounwind {
-; CHECK-LABEL: lsx_vbitset_d:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vbitset.d $vr0, $vr0, $vr1
-; CHECK-NEXT: ret
+; LA32-LABEL: lsx_vbitset_d:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: vrepli.d $vr2, 63
+; LA32-NEXT: vand.v $vr1, $vr1, $vr2
+; LA32-NEXT: vrepli.d $vr2, 1
+; LA32-NEXT: vsll.d $vr1, $vr2, $vr1
+; LA32-NEXT: vor.v $vr0, $vr0, $vr1
+; LA32-NEXT: ret
+;
+; LA64-LABEL: lsx_vbitset_d:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: vbitset.d $vr0, $vr0, $vr1
+; LA64-NEXT: ret
entry:
%res = call <2 x i64> @llvm.loongarch.lsx.vbitset.d(<2 x i64> %va, <2 x i64> %vb)
ret <2 x i64> %res
@@ -88,10 +98,17 @@ entry:
declare <2 x i64> @llvm.loongarch.lsx.vbitseti.d(<2 x i64>, i32)
define <2 x i64> @lsx_vbitseti_d(<2 x i64> %va) nounwind {
-; CHECK-LABEL: lsx_vbitseti_d:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vbitseti.d $vr0, $vr0, 63
-; CHECK-NEXT: ret
+; LA32-LABEL: lsx_vbitseti_d:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: pcalau12i $a0, %pc_hi20(.LCPI7_0)
+; LA32-NEXT: vld $vr1, $a0, %pc_lo12(.LCPI7_0)
+; LA32-NEXT: vor.v $vr0, $vr0, $vr1
+; LA32-NEXT: ret
+;
+; LA64-LABEL: lsx_vbitseti_d:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: vbitseti.d $vr0, $vr0, 63
+; LA64-NEXT: ret
entry:
%res = call <2 x i64> @llvm.loongarch.lsx.vbitseti.d(<2 x i64> %va, i32 63)
ret <2 x i64> %res
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsll-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsll-invalid-imm.ll
index eb49af49c9bee..84771bf4ea95d 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsll-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsll-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vbsll.v(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsll-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsll-non-imm.ll
index 5b10c9e91a4f4..8a4fb0c9364cb 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsll-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsll-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vbsll.v(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsll.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsll.ll
index e7eb1cfcb4074..5613b4dd0c7fc 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsll.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsll.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vbsll.v(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsrl-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsrl-invalid-imm.ll
index bf56822e2ef59..8ff1a23c58d07 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsrl-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsrl-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vbsrl.v(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsrl-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsrl-non-imm.ll
index 0bc038c869ced..89fb0c6b922a8 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsrl-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsrl-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vbsrl.v(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsrl.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsrl.ll
index fe0565297641b..04b4894b6cff1 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsrl.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-bsrl.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vbsrl.v(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-clo.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-clo.ll
index c581109f3fd0b..7f7f25c690139 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-clo.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-clo.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vclo.b(<16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-clz.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-clz.ll
index 25c37b64349b3..d205c171c0917 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-clz.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-clz.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vclz.b(<16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-div.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-div.ll
index 53166e84d269a..04434d9fb0146 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-div.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-div.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vdiv.b(<16 x i8>, <16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-exth.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-exth.ll
index 2f3e891a9eef2..93b08b2cfe00d 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-exth.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-exth.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <8 x i16> @llvm.loongarch.lsx.vexth.h.b(<16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-extl.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-extl.ll
index cbf19e2a39190..c4c86f928e93e 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-extl.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-extl.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <2 x i64> @llvm.loongarch.lsx.vextl.q.d(<2 x i64>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-extrins-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-extrins-invalid-imm.ll
index 7f94234ed603b..9ef68997b4af1 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-extrins-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-extrins-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vextrins.b(<16 x i8>, <16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-extrins-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-extrins-non-imm.ll
index e834002bb60b8..aa0fa319c82e9 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-extrins-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-extrins-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vextrins.b(<16 x i8>, <16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-extrins.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-extrins.ll
index 8f03a2b812917..895cffc072081 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-extrins.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-extrins.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vextrins.b(<16 x i8>, <16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fadd.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fadd.ll
index 569002314c929..9d6c1cc22e8ad 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fadd.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fadd.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <4 x float> @llvm.loongarch.lsx.vfadd.s(<4 x float>, <4 x float>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fclass.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fclass.ll
index 0c66821871017..aa35970017cba 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fclass.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fclass.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <4 x i32> @llvm.loongarch.lsx.vfclass.s(<4 x float>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fcvt.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fcvt.ll
index a6a151a96d84e..4da977ca398dd 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fcvt.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fcvt.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <8 x i16> @llvm.loongarch.lsx.vfcvt.h.s(<4 x float>, <4 x float>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fcvth.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fcvth.ll
index a9e4328bd011d..81897ecf5deab 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fcvth.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fcvth.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <4 x float> @llvm.loongarch.lsx.vfcvth.s.h(<8 x i16>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fcvtl.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fcvtl.ll
index 9a69964bb2274..0abbbe3dba132 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fcvtl.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fcvtl.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <4 x float> @llvm.loongarch.lsx.vfcvtl.s.h(<8 x i16>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fdiv.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fdiv.ll
index 1ca8e5e2c0e9c..4f39b2d5cee96 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fdiv.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fdiv.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <4 x float> @llvm.loongarch.lsx.vfdiv.s(<4 x float>, <4 x float>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ffint.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ffint.ll
index 62fbcfa339cda..c3286a5298981 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ffint.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ffint.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <4 x float> @llvm.loongarch.lsx.vffint.s.w(<4 x i32>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-flogb.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-flogb.ll
index d8382acc70ed6..d382b862b506f 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-flogb.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-flogb.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <4 x float> @llvm.loongarch.lsx.vflogb.s(<4 x float>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmadd.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmadd.ll
index adbaf6c76b1b6..6f921a490ac3b 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmadd.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmadd.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <4 x float> @llvm.loongarch.lsx.vfmadd.s(<4 x float>, <4 x float>, <4 x float>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmax.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmax.ll
index 89f757c4e4567..850170db39f29 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmax.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmax.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <4 x float> @llvm.loongarch.lsx.vfmax.s(<4 x float>, <4 x float>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmaxa.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmaxa.ll
index 5662acc0b9a14..3365841b804a1 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmaxa.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmaxa.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <4 x float> @llvm.loongarch.lsx.vfmaxa.s(<4 x float>, <4 x float>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmin.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmin.ll
index 0f844240277fb..da7e4d203c145 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmin.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmin.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <4 x float> @llvm.loongarch.lsx.vfmin.s(<4 x float>, <4 x float>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmina.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmina.ll
index 27f70b5fba322..4fb1c5bfeb842 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmina.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmina.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <4 x float> @llvm.loongarch.lsx.vfmina.s(<4 x float>, <4 x float>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmsub.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmsub.ll
index 856ca9cadbd90..090c1dd0d09c4 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmsub.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmsub.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <4 x float> @llvm.loongarch.lsx.vfmsub.s(<4 x float>, <4 x float>, <4 x float>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmul.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmul.ll
index 1e6c4c77d536b..50b335f17563b 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmul.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fmul.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <4 x float> @llvm.loongarch.lsx.vfmul.s(<4 x float>, <4 x float>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fnmadd.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fnmadd.ll
index e1a9ea78ef9db..bdb7667e19621 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fnmadd.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fnmadd.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <4 x float> @llvm.loongarch.lsx.vfnmadd.s(<4 x float>, <4 x float>, <4 x float>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fnmsub.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fnmsub.ll
index 46db0f4a50613..ac035b3bc7f13 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fnmsub.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fnmsub.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <4 x float> @llvm.loongarch.lsx.vfnmsub.s(<4 x float>, <4 x float>, <4 x float>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frecip.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frecip.ll
index 669fde5912d4b..db63deb618e60 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frecip.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frecip.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <4 x float> @llvm.loongarch.lsx.vfrecip.s(<4 x float>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frint.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frint.ll
index 8d872fc729625..ba40b6d8ceaeb 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frint.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frint.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <4 x float> @llvm.loongarch.lsx.vfrintrne.s(<4 x float>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frsqrt.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frsqrt.ll
index 326d87308b0ba..9ddd45b5dd534 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frsqrt.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frsqrt.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <4 x float> @llvm.loongarch.lsx.vfrsqrt.s(<4 x float>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frstp-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frstp-invalid-imm.ll
index 0184c855c9c10..8758478f47356 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frstp-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frstp-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vfrstpi.b(<16 x i8>, <16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frstp-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frstp-non-imm.ll
index 9583f672a305e..164c0676b76c8 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frstp-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frstp-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vfrstpi.b(<16 x i8>, <16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frstp.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frstp.ll
index 5c072b194d4fe..dfe75b2181a0d 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frstp.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-frstp.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vfrstp.b(<16 x i8>, <16 x i8>, <16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fsqrt.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fsqrt.ll
index 55bffba9e99e9..f8d0713dad08e 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fsqrt.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fsqrt.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <4 x float> @llvm.loongarch.lsx.vfsqrt.s(<4 x float>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fsub.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fsub.ll
index 2beba4a70dc96..cc0f88d9d32c8 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fsub.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-fsub.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <4 x float> @llvm.loongarch.lsx.vfsub.s(<4 x float>, <4 x float>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ftint.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ftint.ll
index 2a494cd7fa874..1024ee34715af 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ftint.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ftint.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <4 x i32> @llvm.loongarch.lsx.vftintrne.w.s(<4 x float>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-haddw.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-haddw.ll
index 05725582334ae..349c2ddccf3b8 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-haddw.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-haddw.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <8 x i16> @llvm.loongarch.lsx.vhaddw.h.b(<16 x i8>, <16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-hsubw.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-hsubw.ll
index dd5815b2ea85a..039f5994bfbae 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-hsubw.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-hsubw.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <8 x i16> @llvm.loongarch.lsx.vhsubw.h.b(<16 x i8>, <16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ilv.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ilv.ll
index 77b0b3484df8c..0c731f45f7ea1 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ilv.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ilv.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vilvl.b(<16 x i8>, <16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-insgr2vr-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-insgr2vr-invalid-imm.ll
index 3d4f84fb6e038..4ba83bc5cb660 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-insgr2vr-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-insgr2vr-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vinsgr2vr.b(<16 x i8>, i32, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-insgr2vr-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-insgr2vr-non-imm.ll
index 2a4c2218de8c9..3633ba0a2d91e 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-insgr2vr-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-insgr2vr-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vinsgr2vr.b(<16 x i8>, i32, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-insgr2vr.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-insgr2vr.ll
index 61d2cbd280664..8ededfd38d1f6 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-insgr2vr.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-insgr2vr.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64
declare <16 x i8> @llvm.loongarch.lsx.vinsgr2vr.b(<16 x i8>, i32, i32)
@@ -43,11 +44,18 @@ entry:
declare <2 x i64> @llvm.loongarch.lsx.vinsgr2vr.d(<2 x i64>, i64, i32)
define <2 x i64> @lsx_vinsgr2vr_d(<2 x i64> %va) nounwind {
-; CHECK-LABEL: lsx_vinsgr2vr_d:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: ori $a0, $zero, 1
-; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 1
-; CHECK-NEXT: ret
+; LA32-LABEL: lsx_vinsgr2vr_d:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: ori $a0, $zero, 1
+; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 2
+; LA32-NEXT: vinsgr2vr.w $vr0, $zero, 3
+; LA32-NEXT: ret
+;
+; LA64-LABEL: lsx_vinsgr2vr_d:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: ori $a0, $zero, 1
+; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 1
+; LA64-NEXT: ret
entry:
%res = call <2 x i64> @llvm.loongarch.lsx.vinsgr2vr.d(<2 x i64> %va, i64 1, i32 1)
ret <2 x i64> %res
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ld-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ld-invalid-imm.ll
index 9375f9f01a92e..de2189a8e8929 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ld-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ld-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vld(ptr, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ld-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ld-non-imm.ll
index f8b4c42326df0..be7365d0ee5ad 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ld-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ld-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vld(ptr, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldi-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldi-invalid-imm.ll
index 57f6f8e81d91c..106b8e6e6dfd9 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldi-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldi-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <2 x i64> @llvm.loongarch.lsx.vldi(i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldi-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldi-non-imm.ll
index a8f8278f8097a..2f4a577f36c3f 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldi-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldi-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <2 x i64> @llvm.loongarch.lsx.vldi(i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldi.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldi.ll
index ace910b54d9a6..582b49a74cb43 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldi.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldi.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <2 x i64> @llvm.loongarch.lsx.vldi(i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldrepl-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldrepl-invalid-imm.ll
index 34bf945c9df46..f0dd800631895 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldrepl-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldrepl-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vldrepl.b(ptr, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldrepl-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldrepl-non-imm.ll
index 9613c1a62540c..8f8f0aeade054 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldrepl-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldrepl-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vldrepl.b(ptr, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldrepl.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldrepl.ll
index 9ebe0c2fccd57..74f20745a3d0a 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldrepl.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ldrepl.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vldrepl.b(ptr, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-madd.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-madd.ll
index 89503724fd730..14634fe8daec6 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-madd.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-madd.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vmadd.b(<16 x i8>, <16 x i8>, <16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-maddw.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-maddw.ll
index 1e3ab25a5fcf1..58ee70aacae97 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-maddw.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-maddw.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <8 x i16> @llvm.loongarch.lsx.vmaddwev.h.b(<8 x i16>, <16 x i8>, <16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-max-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-max-non-imm.ll
index 34bbe34956707..6c7a0657940e1 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-max-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-max-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vmaxi.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-max.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-max.ll
index 4dd289cf6ed72..caea2e0d68180 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-max.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-max.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vmax.b(<16 x i8>, <16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-min-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-min-non-imm.ll
index 5d9b98cec4d0e..444220f870399 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-min-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-min-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vmini.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-min.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-min.ll
index aa12a5ead6a3f..fa26a5bc430da 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-min.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-min.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vmin.b(<16 x i8>, <16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-mod.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-mod.ll
index 6b3dc6865584e..46630562c84fb 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-mod.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-mod.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vmod.b(<16 x i8>, <16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-mskgez.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-mskgez.ll
index 3ecd777aee678..8bc4c572e7281 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-mskgez.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-mskgez.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vmskgez.b(<16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-mskltz.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-mskltz.ll
index be00c76137c77..9e36cc77080aa 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-mskltz.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-mskltz.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vmskltz.b(<16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-msknz.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-msknz.ll
index 02f1752f7190d..a47f0303db276 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-msknz.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-msknz.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vmsknz.b(<16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-msub.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-msub.ll
index 98684e10c78e5..1b7ae48b44ad4 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-msub.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-msub.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vmsub.b(<16 x i8>, <16 x i8>, <16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-muh.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-muh.ll
index a4deb8f8f823e..ce584fe9ed0c4 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-muh.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-muh.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vmuh.b(<16 x i8>, <16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-mul.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-mul.ll
index aca60d1663b74..46f6f0919571c 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-mul.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-mul.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vmul.b(<16 x i8>, <16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-mulw.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-mulw.ll
index eb55c1f809e3a..74358585a4444 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-mulw.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-mulw.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <8 x i16> @llvm.loongarch.lsx.vmulwev.h.b(<16 x i8>, <16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-neg.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-neg.ll
index 43c6e97576149..2e6dbdbc99b18 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-neg.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-neg.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vneg.b(<16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-nor.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-nor.ll
index 16619225f2d17..2bf21fb2dc318 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-nor.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-nor.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vnor.v(<16 x i8>, <16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-nori-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-nori-invalid-imm.ll
index 8c59d8fb9fa5e..e82f9c78f2ab1 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-nori-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-nori-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vnori.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-nori-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-nori-non-imm.ll
index 322a39c106a68..0dd3accc8e5e1 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-nori-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-nori-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vnori.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-nori.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-nori.ll
index c2388a1e0da37..0777fab45d090 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-nori.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-nori.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vnori.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-or.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-or.ll
index ab557003d1504..40b4549d1b586 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-or.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-or.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vor.v(<16 x i8>, <16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ori-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ori-invalid-imm.ll
index 4a7fc7e109d96..612fecfd239e6 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ori-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ori-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vori.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ori-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ori-non-imm.ll
index 5644b8581dce7..d8b78e71fcb40 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ori-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ori-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vori.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ori.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ori.ll
index 85c0f432c54a2..71bd9f03feea9 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ori.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ori.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vori.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-orn.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-orn.ll
index 4528628e02c3c..8974703ba6e1a 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-orn.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-orn.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vorn.v(<16 x i8>, <16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-pack.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-pack.ll
index 70a3620d1757a..42d6142506842 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-pack.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-pack.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vpackev.b(<16 x i8>, <16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-pcnt.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-pcnt.ll
index 431b270ab0a14..177d732604af5 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-pcnt.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-pcnt.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vpcnt.b(<16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-permi-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-permi-invalid-imm.ll
index e439bbae6130d..f719c5cf30e71 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-permi-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-permi-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <4 x i32> @llvm.loongarch.lsx.vpermi.w(<4 x i32>, <4 x i32>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-permi-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-permi-non-imm.ll
index bdfc08ed680a9..e41d74ef2dae1 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-permi-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-permi-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <4 x i32> @llvm.loongarch.lsx.vpermi.w(<4 x i32>, <4 x i32>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-permi.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-permi.ll
index b8367d98caf66..ccad1b7a8250b 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-permi.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-permi.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <4 x i32> @llvm.loongarch.lsx.vpermi.w(<4 x i32>, <4 x i32>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-pick.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-pick.ll
index 4ebf29e1409c0..d75889965f394 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-pick.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-pick.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vpickev.b(<16 x i8>, <16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-pickve2gr-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-pickve2gr-non-imm.ll
index 6dd3c1f27a81e..7073346407710 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-pickve2gr-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-pickve2gr-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare i32 @llvm.loongarch.lsx.vpickve2gr.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-replve.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-replve.ll
index 3ba184dad052b..35fd8d6447006 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-replve.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-replve.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vreplve.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-replvei-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-replvei-invalid-imm.ll
index d625441122a66..7fdc8fe8c6905 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-replvei-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-replvei-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vreplvei.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-replvei-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-replvei-non-imm.ll
index 3d271bb2b3073..e7f8a0708ad15 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-replvei-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-replvei-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vreplvei.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-replvei.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-replvei.ll
index 9b8af1878cb83..216c2ae52844a 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-replvei.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-replvei.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vreplvei.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-rotr-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-rotr-invalid-imm.ll
index 3c53b36672ad3..6e0b6e6e4f3e6 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-rotr-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-rotr-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vrotri.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-rotr-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-rotr-non-imm.ll
index fd8ba3a1c633f..b7cc043385764 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-rotr-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-rotr-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vrotri.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-rotr.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-rotr.ll
index df8650677147b..5ee7b26429993 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-rotr.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-rotr.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vrotr.b(<16 x i8>, <16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sadd.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sadd.ll
index a54f955766dfe..82149a263bd79 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sadd.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sadd.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vsadd.b(<16 x i8>, <16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sat-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sat-invalid-imm.ll
index 45fa4e43be198..9b15c05382008 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sat-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sat-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vsat.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sat-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sat-non-imm.ll
index afdbe0c1ce0b9..ce99366ee5f88 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sat-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sat-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vsat.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sat.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sat.ll
index 4286842a63b98..3412b878eed44 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sat.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sat.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vsat.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-seq-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-seq-invalid-imm.ll
index 220398ff28cda..304894dbf4101 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-seq-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-seq-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vseqi.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-seq-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-seq-non-imm.ll
index 5fa1dd30475ce..82db51ada1c29 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-seq-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-seq-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vseqi.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-seq.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-seq.ll
index 3cb4acd824393..ac946cacc63a9 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-seq.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-seq.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vseq.b(<16 x i8>, <16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-shuf.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-shuf.ll
index f5d516521e45f..5deca45044cc0 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-shuf.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-shuf.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vshuf.b(<16 x i8>, <16 x i8>, <16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-shuf4i-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-shuf4i-invalid-imm.ll
index 4d6fadf08c26b..9d7f2729c0f24 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-shuf4i-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-shuf4i-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vshuf4i.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-shuf4i-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-shuf4i-non-imm.ll
index a7d138bcc00bb..b5518763975ee 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-shuf4i-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-shuf4i-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vshuf4i.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-shuf4i.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-shuf4i.ll
index 1ad5f2af5591e..3cb712fd07fab 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-shuf4i.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-shuf4i.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vshuf4i.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-signcov.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-signcov.ll
index 3997b0cc995c5..46f18670e0df4 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-signcov.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-signcov.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vsigncov.b(<16 x i8>, <16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sle-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sle-invalid-imm.ll
index 4c945e296711f..39787b3d0f5b7 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sle-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sle-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vslei.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sle-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sle-non-imm.ll
index 0fc137bf05498..0feb967068cb0 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sle-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sle-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vslei.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sle.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sle.ll
index 5a9d5f06e63f8..8a225a31f9da5 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sle.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sle.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vsle.b(<16 x i8>, <16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sll-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sll-invalid-imm.ll
index 75406f94887ca..6a5b11196cae5 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sll-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sll-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vslli.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sll-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sll-non-imm.ll
index 7474b5e297349..ce005d097fa7e 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sll-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sll-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vslli.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sll.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sll.ll
index 7bc20af41f17a..d1316e04efbb9 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sll.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sll.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64
declare <16 x i8> @llvm.loongarch.lsx.vsll.b(<16 x i8>, <16 x i8>)
@@ -40,10 +41,17 @@ entry:
declare <2 x i64> @llvm.loongarch.lsx.vsll.d(<2 x i64>, <2 x i64>)
define <2 x i64> @lsx_vsll_d(<2 x i64> %va, <2 x i64> %vb) nounwind {
-; CHECK-LABEL: lsx_vsll_d:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsll.d $vr0, $vr0, $vr1
-; CHECK-NEXT: ret
+; LA32-LABEL: lsx_vsll_d:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: vrepli.d $vr2, 63
+; LA32-NEXT: vand.v $vr1, $vr1, $vr2
+; LA32-NEXT: vsll.d $vr0, $vr0, $vr1
+; LA32-NEXT: ret
+;
+; LA64-LABEL: lsx_vsll_d:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: vsll.d $vr0, $vr0, $vr1
+; LA64-NEXT: ret
entry:
%res = call <2 x i64> @llvm.loongarch.lsx.vsll.d(<2 x i64> %va, <2 x i64> %vb)
ret <2 x i64> %res
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sllwil-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sllwil-invalid-imm.ll
index bda3523a0b5c0..74e65742cfa81 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sllwil-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sllwil-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <8 x i16> @llvm.loongarch.lsx.vsllwil.h.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sllwil-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sllwil-non-imm.ll
index a03656d5ca07a..51921e7e6b43d 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sllwil-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sllwil-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <8 x i16> @llvm.loongarch.lsx.vsllwil.h.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sllwil.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sllwil.ll
index 29ab70da1ceda..65f1f6b49c81b 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sllwil.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sllwil.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <8 x i16> @llvm.loongarch.lsx.vsllwil.h.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-slt-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-slt-invalid-imm.ll
index f6d014b19d6c7..e585f370b7f07 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-slt-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-slt-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vslti.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-slt-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-slt-non-imm.ll
index 9a8b757dab4e4..e42215291f255 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-slt-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-slt-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vslti.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-slt.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-slt.ll
index 18683e9dc46f6..a0eb870ba9ad4 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-slt.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-slt.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vslt.b(<16 x i8>, <16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sra-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sra-invalid-imm.ll
index 2a033a21b5651..cacb7d7c6448e 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sra-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sra-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vsrai.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sra-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sra-non-imm.ll
index c3b328145864f..f3bfe73911b48 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sra-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sra-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vsrai.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sra.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sra.ll
index e85c8464c18e1..14c3801a8040a 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sra.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sra.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64
declare <16 x i8> @llvm.loongarch.lsx.vsra.b(<16 x i8>, <16 x i8>)
@@ -40,10 +41,17 @@ entry:
declare <2 x i64> @llvm.loongarch.lsx.vsra.d(<2 x i64>, <2 x i64>)
define <2 x i64> @lsx_vsra_d(<2 x i64> %va, <2 x i64> %vb) nounwind {
-; CHECK-LABEL: lsx_vsra_d:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsra.d $vr0, $vr0, $vr1
-; CHECK-NEXT: ret
+; LA32-LABEL: lsx_vsra_d:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: vrepli.d $vr2, 63
+; LA32-NEXT: vand.v $vr1, $vr1, $vr2
+; LA32-NEXT: vsra.d $vr0, $vr0, $vr1
+; LA32-NEXT: ret
+;
+; LA64-LABEL: lsx_vsra_d:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: vsra.d $vr0, $vr0, $vr1
+; LA64-NEXT: ret
entry:
%res = call <2 x i64> @llvm.loongarch.lsx.vsra.d(<2 x i64> %va, <2 x i64> %vb)
ret <2 x i64> %res
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sran.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sran.ll
index 4ffe5a704c2c8..4cb38b4612f76 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sran.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sran.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vsran.b.h(<8 x i16>, <8 x i16>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srani-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srani-invalid-imm.ll
index d68064e9b9024..bd0cdb79d9187 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srani-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srani-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vsrani.b.h(<16 x i8>, <16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srani-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srani-non-imm.ll
index 38cfde214dc1c..8a501434b1d2f 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srani-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srani-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vsrani.b.h(<16 x i8>, <16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srani.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srani.ll
index 717c641616c8d..7e2a9e107f4a6 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srani.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srani.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vsrani.b.h(<16 x i8>, <16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srar-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srar-invalid-imm.ll
index b6c2d70cebbc0..a8f59a58a0c45 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srar-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srar-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vsrari.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srar-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srar-non-imm.ll
index 2ad8adcd823b6..f2122054ae4da 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srar-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srar-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vsrari.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srar.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srar.ll
index 8b52b7ac9631f..40aa39e89bf1a 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srar.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srar.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vsrar.b(<16 x i8>, <16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srarn.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srarn.ll
index d4cdfb5359eaa..c952fae877198 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srarn.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srarn.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vsrarn.b.h(<8 x i16>, <8 x i16>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srarni-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srarni-invalid-imm.ll
index d24cf92a03928..5e4d9f94b385f 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srarni-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srarni-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vsrarni.b.h(<16 x i8>, <16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srarni-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srarni-non-imm.ll
index 19de7445cba1c..15ac105abd76f 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srarni-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srarni-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vsrarni.b.h(<16 x i8>, <16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srarni.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srarni.ll
index 2253e88372fcb..af3ce7722e463 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srarni.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srarni.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vsrarni.b.h(<16 x i8>, <16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srl-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srl-invalid-imm.ll
index 3beff790afab6..0d1b8906e655b 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srl-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srl-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vsrli.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srl-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srl-non-imm.ll
index 98652aca0d628..9c32772c0aba6 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srl-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srl-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vsrli.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srl.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srl.ll
index 1cddd9622233a..9499a0ab445e5 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srl.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srl.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64
declare <16 x i8> @llvm.loongarch.lsx.vsrl.b(<16 x i8>, <16 x i8>)
@@ -40,10 +41,17 @@ entry:
declare <2 x i64> @llvm.loongarch.lsx.vsrl.d(<2 x i64>, <2 x i64>)
define <2 x i64> @lsx_vsrl_d(<2 x i64> %va, <2 x i64> %vb) nounwind {
-; CHECK-LABEL: lsx_vsrl_d:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vsrl.d $vr0, $vr0, $vr1
-; CHECK-NEXT: ret
+; LA32-LABEL: lsx_vsrl_d:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: vrepli.d $vr2, 63
+; LA32-NEXT: vand.v $vr1, $vr1, $vr2
+; LA32-NEXT: vsrl.d $vr0, $vr0, $vr1
+; LA32-NEXT: ret
+;
+; LA64-LABEL: lsx_vsrl_d:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: vsrl.d $vr0, $vr0, $vr1
+; LA64-NEXT: ret
entry:
%res = call <2 x i64> @llvm.loongarch.lsx.vsrl.d(<2 x i64> %va, <2 x i64> %vb)
ret <2 x i64> %res
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srln.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srln.ll
index 1c9b23243ffbd..7a86688e43f43 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srln.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srln.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vsrln.b.h(<8 x i16>, <8 x i16>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlni-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlni-invalid-imm.ll
index 054c4f393548f..366effc2e7c6f 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlni-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlni-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vsrlni.b.h(<16 x i8>, <16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlni-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlni-non-imm.ll
index 76341df197fdf..d3f5cc07966e0 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlni-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlni-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vsrlni.b.h(<16 x i8>, <16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlni.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlni.ll
index 6e523efa18240..e8d06e7e8bc64 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlni.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlni.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vsrlni.b.h(<16 x i8>, <16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlr-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlr-invalid-imm.ll
index bcbd38e26e5f5..6b557dfbada3e 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlr-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlr-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vsrlri.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlr-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlr-non-imm.ll
index 4862b1546ccf5..c0ba458cb2f5f 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlr-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlr-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vsrlri.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlr.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlr.ll
index 51638fa1a47f4..0d479951a57af 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlr.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlr.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vsrlr.b(<16 x i8>, <16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlrn.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlrn.ll
index 893e513962411..9563b94597885 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlrn.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlrn.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vsrlrn.b.h(<8 x i16>, <8 x i16>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlrni-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlrni-invalid-imm.ll
index 8988ae88f9ebf..e4085b52bbf80 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlrni-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlrni-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vsrlrni.b.h(<16 x i8>, <16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlrni-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlrni-non-imm.ll
index e5530db56fed9..51488926f92ca 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlrni-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlrni-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vsrlrni.b.h(<16 x i8>, <16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlrni.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlrni.ll
index d1ea450d2237d..3db7e3f3e5715 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlrni.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-srlrni.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vsrlrni.b.h(<16 x i8>, <16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssran.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssran.ll
index cecccbb730c95..96493d555da6d 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssran.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssran.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vssran.b.h(<8 x i16>, <8 x i16>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrani-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrani-invalid-imm.ll
index f7817921ebebc..bf185ae5d9748 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrani-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrani-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vssrani.b.h(<16 x i8>, <16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrani-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrani-non-imm.ll
index a80ede9c5243e..a4f0a4ed93198 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrani-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrani-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vssrani.b.h(<16 x i8>, <16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrani.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrani.ll
index 57b8eb1698666..75577dbafb1c9 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrani.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrani.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vssrani.b.h(<16 x i8>, <16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrarn.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrarn.ll
index c6b7d9ec8e1d6..5ad63f2bd0ab3 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrarn.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrarn.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vssrarn.b.h(<8 x i16>, <8 x i16>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrarni-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrarni-invalid-imm.ll
index 4edda8c0a24ad..f54bb71881c48 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrarni-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrarni-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vssrarni.b.h(<16 x i8>, <16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrarni-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrarni-non-imm.ll
index a77e6e764c9d4..00cfc60b43142 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrarni-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrarni-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vssrarni.b.h(<16 x i8>, <16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrarni.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrarni.ll
index 1a2e91962ac3b..af32b58b53f88 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrarni.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrarni.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vssrarni.b.h(<16 x i8>, <16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrln.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrln.ll
index 697ccc3962a81..6fb1a3b158602 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrln.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrln.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vssrln.b.h(<8 x i16>, <8 x i16>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlni-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlni-invalid-imm.ll
index 6218af1fa773f..4fb4b307a7061 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlni-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlni-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vssrlni.b.h(<16 x i8>, <16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlni-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlni-non-imm.ll
index 688be826f467f..2c8356ed0a600 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlni-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlni-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vssrlni.b.h(<16 x i8>, <16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlni.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlni.ll
index 8dd41e7abe873..deb1575bedcc8 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlni.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlni.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vssrlni.b.h(<16 x i8>, <16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlrn.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlrn.ll
index a8e76cbaa7fd1..a17ab94d02ca1 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlrn.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlrn.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vssrlrn.b.h(<8 x i16>, <8 x i16>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlrni-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlrni-invalid-imm.ll
index 98a0c5b3cd28a..61e85be08c0a4 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlrni-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlrni-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vssrlrni.b.h(<16 x i8>, <16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlrni-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlrni-non-imm.ll
index c389b4fd6023b..f4450f25274ec 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlrni-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlrni-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vssrlrni.b.h(<16 x i8>, <16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlrni.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlrni.ll
index 869e81b2b09d6..840fafc038fce 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlrni.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssrlrni.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vssrlrni.b.h(<16 x i8>, <16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssub.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssub.ll
index c594b426d6503..ac0ef538cdcb9 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssub.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-ssub.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vssub.b(<16 x i8>, <16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-st-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-st-invalid-imm.ll
index a72126cd15a66..079fba79b3501 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-st-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-st-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare void @llvm.loongarch.lsx.vst(<16 x i8>, ptr, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-st-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-st-non-imm.ll
index ba9f44c59c37d..aae751c17497c 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-st-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-st-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare void @llvm.loongarch.lsx.vst(<16 x i8>, ptr, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-stelm-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-stelm-invalid-imm.ll
index 82dba30ed1e7d..7f3c343dd5bf3 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-stelm-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-stelm-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare void @llvm.loongarch.lsx.vstelm.b(<16 x i8>, ptr, i32, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-stelm-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-stelm-non-imm.ll
index a8a74819c2049..feb8fbaf2952c 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-stelm-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-stelm-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare void @llvm.loongarch.lsx.vstelm.b(<16 x i8>, ptr, i32, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-stelm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-stelm.ll
index 4f8412be9579c..9b6af6fc1a965 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-stelm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-stelm.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare void @llvm.loongarch.lsx.vstelm.b(<16 x i8>, ptr, i32, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sub.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sub.ll
index 5c04a3d8de0df..8f1b441e92fee 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sub.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-sub.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vsub.b(<16 x i8>, <16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-subi-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-subi-invalid-imm.ll
index 96cc1241fbf3f..fc1c9e110876b 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-subi-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-subi-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vsubi.bu(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-subi-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-subi-non-imm.ll
index 162f9ad131c75..68b59ca9c02fe 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-subi-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-subi-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vsubi.bu(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-subi.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-subi.ll
index 304a4e4a78cc7..46642171aaa1a 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-subi.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-subi.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vsubi.bu(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-subw.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-subw.ll
index 48100db743344..f41a3a1b99fdb 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-subw.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-subw.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <8 x i16> @llvm.loongarch.lsx.vsubwev.h.b(<16 x i8>, <16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-xor.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-xor.ll
index 72a1fe93c2c01..5a49605f5fa54 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-xor.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-xor.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vxor.v(<16 x i8>, <16 x i8>)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-xori-invalid-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-xori-invalid-imm.ll
index 5f5613189ac81..a3e3fa9dfa037 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-xori-invalid-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-xori-invalid-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vxori.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-xori-non-imm.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-xori-non-imm.ll
index 4238d89120f1a..d0a6df6bc78a1 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-xori-non-imm.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-xori-non-imm.ll
@@ -1,3 +1,4 @@
+; RUN: not llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s 2>&1 | FileCheck %s
; RUN: not llc --mtriple=loongarch64 --mattr=+lsx < %s 2>&1 | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vxori.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-xori.ll b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-xori.ll
index 09669cd5ac14c..7241bfbfcedd0 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/intrinsic-xori.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/intrinsic-xori.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
declare <16 x i8> @llvm.loongarch.lsx.vxori.b(<16 x i8>, i32)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/absd.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/absd.ll
index f77a31b600761..6546719647f3a 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/absd.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/absd.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc -mtriple=loongarch64 -mattr=+lsx < %s | FileCheck %s
;; 1. trunc(abs(sub(sext(a),sext(b)))) -> abds(a,b) or abdu(a,b)
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/add.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/add.ll
index 485bd1df8d66e..41164b635983e 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/add.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/add.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
define void @add_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind {
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/and.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/and.ll
index d3e4efb1b1c27..2d6f0bea07122 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/and.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/and.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
define void @and_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind {
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/ashr.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/ashr.ll
index 2a31074470983..3a099cb18d379 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/ashr.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/ashr.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
define void @ashr_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind {
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/bitcast-extract-element.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/bitcast-extract-element.ll
index 9a40feb45671f..514a5527e8296 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/bitcast-extract-element.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/bitcast-extract-element.ll
@@ -1,11 +1,18 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefix=LA64
define i32 @bitcast_extract_v4f32(<4 x float> %a) nounwind {
-; CHECK-LABEL: bitcast_extract_v4f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vpickve2gr.w $a0, $vr0, 3
-; CHECK-NEXT: ret
+; LA32-LABEL: bitcast_extract_v4f32:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: vreplvei.w $vr0, $vr0, 3
+; LA32-NEXT: movfr2gr.s $a0, $fa0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: bitcast_extract_v4f32:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: vpickve2gr.w $a0, $vr0, 3
+; LA64-NEXT: ret
entry:
%b = extractelement <4 x float> %a, i32 3
%c = bitcast float %b to i32
@@ -13,10 +20,17 @@ entry:
}
define i64 @bitcast_extract_v2f64(<2 x double> %a) nounwind {
-; CHECK-LABEL: bitcast_extract_v2f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vpickve2gr.d $a0, $vr0, 1
-; CHECK-NEXT: ret
+; LA32-LABEL: bitcast_extract_v2f64:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: vreplvei.d $vr0, $vr0, 1
+; LA32-NEXT: movfr2gr.s $a0, $fa0
+; LA32-NEXT: movfrh2gr.s $a1, $fa0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: bitcast_extract_v2f64:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: vpickve2gr.d $a0, $vr0, 1
+; LA64-NEXT: ret
entry:
%b = extractelement <2 x double> %a, i32 1
%c = bitcast double %b to i64
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fadd.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fadd.ll
index 989ad10a44ffc..c0f010a936623 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fadd.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fadd.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
define void @fadd_v4f32(ptr %res, ptr %a0, ptr %a1) nounwind {
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fcmp.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fcmp.ll
index 95e46a4e71dab..9a1498f555823 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fcmp.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fcmp.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
;; TREU
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fdiv.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fdiv.ll
index 3b9642e31b02d..603bd21ab9af9 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fdiv.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fdiv.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
-; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64
define void @fdiv_v4f32(ptr %res, ptr %a0, ptr %a1) nounwind {
; CHECK-LABEL: fdiv_v4f32:
@@ -49,12 +50,21 @@ entry:
}
define void @one_fdiv_v2f64(ptr %res, ptr %a0) nounwind {
-; CHECK-LABEL: one_fdiv_v2f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vld $vr0, $a1, 0
-; CHECK-NEXT: vfrecip.d $vr0, $vr0
-; CHECK-NEXT: vst $vr0, $a0, 0
-; CHECK-NEXT: ret
+; LA32-LABEL: one_fdiv_v2f64:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: vld $vr0, $a1, 0
+; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI3_0)
+; LA32-NEXT: vld $vr1, $a1, %pc_lo12(.LCPI3_0)
+; LA32-NEXT: vfdiv.d $vr0, $vr1, $vr0
+; LA32-NEXT: vst $vr0, $a0, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: one_fdiv_v2f64:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: vld $vr0, $a1, 0
+; LA64-NEXT: vfrecip.d $vr0, $vr0
+; LA64-NEXT: vst $vr0, $a0, 0
+; LA64-NEXT: ret
entry:
%v0 = load <2 x double>, ptr %a0
%div = fdiv <2 x double> <double 1.0, double 1.0>, %v0
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fmul.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fmul.ll
index f604a8962958d..faf461c677816 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fmul.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fmul.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
define void @fmul_v4f32(ptr %res, ptr %a0, ptr %a1) nounwind {
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fneg.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fneg.ll
index 795c1ac8b3684..007634d28d17e 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fneg.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fneg.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
define void @fneg_v4f32(ptr %res, ptr %a0) nounwind {
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fptosi.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fptosi.ll
index c3008fe96e47d..7ea6d7431670e 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fptosi.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fptosi.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
define void @fptosi_v4f32_v4i32(ptr %res, ptr %in){
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fptoui.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fptoui.ll
index f0aeb0bd14e75..ec3a86713ed23 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fptoui.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fptoui.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
define void @fptoui_v4f32_v4i32(ptr %res, ptr %in){
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fsub.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fsub.ll
index 02350c0763bae..f7fe458f353f5 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fsub.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/fsub.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
define void @fsub_v4f32(ptr %res, ptr %a0, ptr %a1) nounwind {
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/icmp.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/icmp.ll
index 04b4831f1188c..7166469bf5cee 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/icmp.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/icmp.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
;; SETEQ
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insert-bitcast-element.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insert-bitcast-element.ll
index c42e3013c1131..e7e0a89a89583 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insert-bitcast-element.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insert-bitcast-element.ll
@@ -1,11 +1,18 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefix=LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefix=LA64
define <4 x float> @insert_bitcast_v4f32(<4 x float> %a, i32 %b) nounwind {
-; CHECK-LABEL: insert_bitcast_v4f32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vinsgr2vr.w $vr0, $a0, 1
-; CHECK-NEXT: ret
+; LA32-LABEL: insert_bitcast_v4f32:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: movgr2fr.w $fa1, $a0
+; LA32-NEXT: vextrins.w $vr0, $vr1, 16
+; LA32-NEXT: ret
+;
+; LA64-LABEL: insert_bitcast_v4f32:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA64-NEXT: ret
entry:
%c = bitcast i32 %b to float
%d = insertelement <4 x float> %a, float %c, i32 1
@@ -13,10 +20,17 @@ entry:
}
define <2 x double> @insert_bitcast_v2f64(<2 x double> %a, i64 %b) nounwind {
-; CHECK-LABEL: insert_bitcast_v2f64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 1
-; CHECK-NEXT: ret
+; LA32-LABEL: insert_bitcast_v2f64:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: movgr2fr.w $fa1, $a0
+; LA32-NEXT: movgr2frh.w $fa1, $a1
+; LA32-NEXT: vextrins.d $vr0, $vr1, 16
+; LA32-NEXT: ret
+;
+; LA64-LABEL: insert_bitcast_v2f64:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 1
+; LA64-NEXT: ret
entry:
%c = bitcast i64 %b to double
%d = insertelement <2 x double> %a, double %c, i32 1
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insert-extract-element.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insert-extract-element.ll
index e9a0c8a110452..65aff8071897d 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insert-extract-element.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insert-extract-element.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64
define <16 x i8> @insert_extract_v16i8(<16 x i8> %a) nounwind {
; CHECK-LABEL: insert_extract_v16i8:
@@ -46,10 +47,18 @@ entry:
}
define <2 x i64> @insert_extract_v2i64(<2 x i64> %a) nounwind {
-; CHECK-LABEL: insert_extract_v2i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: vextrins.d $vr0, $vr0, 1
-; CHECK-NEXT: ret
+; LA32-LABEL: insert_extract_v2i64:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: vori.b $vr1, $vr0, 0
+; LA32-NEXT: vextrins.w $vr1, $vr0, 2
+; LA32-NEXT: vextrins.w $vr1, $vr0, 19
+; LA32-NEXT: vori.b $vr0, $vr1, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: insert_extract_v2i64:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: vextrins.d $vr0, $vr0, 1
+; LA64-NEXT: ret
entry:
%b = extractelement <2 x i64> %a, i32 1
%c = insertelement <2 x i64> %a, i64 %b, i32 0
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/lshr.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/lshr.ll
index 2693310b4f508..584b202691c77 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/lshr.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/lshr.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
define void @lshr_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind {
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/mul.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/mul.ll
index f66cae6a18027..efe85fb13e69b 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/mul.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/mul.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
define void @mul_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind {
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/or.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/or.ll
index 89702e60c01f5..94a1294384578 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/or.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/or.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
define void @or_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind {
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sdiv.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sdiv.ll
index cdff58defdaea..c5dfe231b6860 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sdiv.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sdiv.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
define void @sdiv_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind {
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shl.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shl.ll
index 4b34c04f3374b..1d8ed9ec7e907 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shl.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shl.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
define void @shl_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind {
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vilv.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vilv.ll
index 31398c6081c0a..076395e56e812 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vilv.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vilv.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx %s -o - | FileCheck %s
;; vilvl.b
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vpack.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vpack.ll
index 171e68306cd11..4034773a8a1ff 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vpack.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vpack.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx %s -o - | FileCheck %s
;; vpackev.b
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vpick.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vpick.ll
index ca636d942b583..c6d6019517be0 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vpick.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/shuffle-as-vpick.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx %s -o - | FileCheck %s
;; vpickev.b
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sitofp.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sitofp.ll
index 1e820a37a2409..37eb9e7e8dc49 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sitofp.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sitofp.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
define void @sitofp_v4i32_v4f32(ptr %res, ptr %in){
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sub.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sub.ll
index 2813d9c97e680..ab135faa6ee36 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sub.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/sub.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
define void @sub_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind {
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/udiv.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/udiv.ll
index 32dac67d36a81..65a4075cf359c 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/udiv.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/udiv.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
define void @udiv_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind {
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/uitofp.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/uitofp.ll
index 3d4913f12e57e..3ae1119435eff 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/uitofp.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/uitofp.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
define void @uitofp_v4i32_v4f32(ptr %res, ptr %in){
diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/xor.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/xor.ll
index 482cecb1d7522..fd63b2122a8b7 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/xor.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/xor.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
define void @xor_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind {
diff --git a/llvm/test/CodeGen/LoongArch/lsx/mulh.ll b/llvm/test/CodeGen/LoongArch/lsx/mulh.ll
index b0ca556eeff36..687b3040f5e77 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/mulh.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/mulh.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
define void @mulhs_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind {
diff --git a/llvm/test/CodeGen/LoongArch/lsx/pr116008.ll b/llvm/test/CodeGen/LoongArch/lsx/pr116008.ll
index ba8ffc3493189..f359b44cec4a1 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/pr116008.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/pr116008.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
define <4 x i32> @xor_shl_splat_vec_one(i32 %x, <4 x i32> %y) nounwind {
diff --git a/llvm/test/CodeGen/LoongArch/lsx/scalar-to-vector.ll b/llvm/test/CodeGen/LoongArch/lsx/scalar-to-vector.ll
index 87b68ac591727..d2a506dd98547 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/scalar-to-vector.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/scalar-to-vector.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64
;; Test scalar_to_vector expansion.
@@ -31,10 +32,16 @@ define <4 x i32> @scalar_to_4xi32(i32 %val) {
}
define <2 x i64> @scalar_to_2xi64(i64 %val) {
-; CHECK-LABEL: scalar_to_2xi64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0
-; CHECK-NEXT: ret
+; LA32-LABEL: scalar_to_2xi64:
+; LA32: # %bb.0:
+; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a1, 1
+; LA32-NEXT: ret
+;
+; LA64-LABEL: scalar_to_2xi64:
+; LA64: # %bb.0:
+; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: ret
%ret = insertelement <2 x i64> poison, i64 %val, i32 0
ret <2 x i64> %ret
}
diff --git a/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-bit-shift.ll b/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-bit-shift.ll
index 48f18a35a38c4..efb6b8632f954 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-bit-shift.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-bit-shift.ll
@@ -1,4 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
define <16 x i8> @shuffle_to_vslli_h_8(<16 x i8> %a) nounwind {
diff --git a/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-sign-ext.ll b/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-sign-ext.ll
index 7e9f5b653d01a..5e0ff9a07585f 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-sign-ext.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/vec-shuffle-sign-ext.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64
define void @shuffle_sign_ext_2i8_to_2i64(ptr %ptr, ptr %dst) nounwind {
; CHECK-LABEL: shuffle_sign_ext_2i8_to_2i64:
@@ -37,14 +38,24 @@ define void @shuffle_sign_ext_2i16_to_2i64(ptr %ptr, ptr %dst) nounwind {
}
define void @shuffle_sign_ext_2i32_to_2i64(ptr %ptr, ptr %dst) nounwind {
-; CHECK-LABEL: shuffle_sign_ext_2i32_to_2i64:
-; CHECK: # %bb.0:
-; CHECK-NEXT: ld.d $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0
-; CHECK-NEXT: vrepli.b $vr1, 0
-; CHECK-NEXT: vilvl.w $vr0, $vr1, $vr0
-; CHECK-NEXT: vst $vr0, $a1, 0
-; CHECK-NEXT: ret
+; LA32-LABEL: shuffle_sign_ext_2i32_to_2i64:
+; LA32: # %bb.0:
+; LA32-NEXT: ld.w $a2, $a0, 0
+; LA32-NEXT: ld.w $a0, $a0, 4
+; LA32-NEXT: vrepli.b $vr0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 2
+; LA32-NEXT: vst $vr0, $a1, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: shuffle_sign_ext_2i32_to_2i64:
+; LA64: # %bb.0:
+; LA64-NEXT: ld.d $a0, $a0, 0
+; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: vrepli.b $vr1, 0
+; LA64-NEXT: vilvl.w $vr0, $vr1, $vr0
+; LA64-NEXT: vst $vr0, $a1, 0
+; LA64-NEXT: ret
%x = load <2 x i32>, ptr %ptr
%y = shufflevector <2 x i32> %x, <2 x i32> zeroinitializer, <4 x i32> <i32 0, i32 3, i32 1, i32 2>
%r = bitcast <4 x i32> %y to <2 x i64>
@@ -70,14 +81,25 @@ define void @shuffle_sign_ext_4i8_to_4i32(ptr %ptr, ptr %dst) nounwind {
}
define void @shuffle_sign_ext_4i16_to_4i32(ptr %ptr, ptr %dst) nounwind {
-; CHECK-LABEL: shuffle_sign_ext_4i16_to_4i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: ld.d $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0
-; CHECK-NEXT: vrepli.b $vr1, 0
-; CHECK-NEXT: vilvl.h $vr0, $vr1, $vr0
-; CHECK-NEXT: vst $vr0, $a1, 0
-; CHECK-NEXT: ret
+; LA32-LABEL: shuffle_sign_ext_4i16_to_4i32:
+; LA32: # %bb.0:
+; LA32-NEXT: ld.w $a2, $a0, 0
+; LA32-NEXT: ld.w $a0, $a0, 4
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: vrepli.b $vr1, 0
+; LA32-NEXT: vilvl.h $vr0, $vr1, $vr0
+; LA32-NEXT: vst $vr0, $a1, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: shuffle_sign_ext_4i16_to_4i32:
+; LA64: # %bb.0:
+; LA64-NEXT: ld.d $a0, $a0, 0
+; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: vrepli.b $vr1, 0
+; LA64-NEXT: vilvl.h $vr0, $vr1, $vr0
+; LA64-NEXT: vst $vr0, $a1, 0
+; LA64-NEXT: ret
%x = load <4 x i16>, ptr %ptr
%y = shufflevector <4 x i16> %x, <4 x i16> zeroinitializer, <8 x i32> <i32 0, i32 7, i32 1, i32 6, i32 2, i32 5, i32 3, i32 4>
%r = bitcast <8 x i16> %y to <4 x i32>
@@ -86,14 +108,25 @@ define void @shuffle_sign_ext_4i16_to_4i32(ptr %ptr, ptr %dst) nounwind {
}
define void @shuffle_sign_ext_8i8_to_8i16(ptr %ptr, ptr %dst) nounwind {
-; CHECK-LABEL: shuffle_sign_ext_8i8_to_8i16:
-; CHECK: # %bb.0:
-; CHECK-NEXT: ld.d $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0
-; CHECK-NEXT: vrepli.b $vr1, 0
-; CHECK-NEXT: vilvl.b $vr0, $vr1, $vr0
-; CHECK-NEXT: vst $vr0, $a1, 0
-; CHECK-NEXT: ret
+; LA32-LABEL: shuffle_sign_ext_8i8_to_8i16:
+; LA32: # %bb.0:
+; LA32-NEXT: ld.w $a2, $a0, 0
+; LA32-NEXT: ld.w $a0, $a0, 4
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: vrepli.b $vr1, 0
+; LA32-NEXT: vilvl.b $vr0, $vr1, $vr0
+; LA32-NEXT: vst $vr0, $a1, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: shuffle_sign_ext_8i8_to_8i16:
+; LA64: # %bb.0:
+; LA64-NEXT: ld.d $a0, $a0, 0
+; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: vrepli.b $vr1, 0
+; LA64-NEXT: vilvl.b $vr0, $vr1, $vr0
+; LA64-NEXT: vst $vr0, $a1, 0
+; LA64-NEXT: ret
%x = load <8 x i8>, ptr %ptr
%y = shufflevector <8 x i8> %x, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 15, i32 1, i32 14, i32 2, i32 13, i32 3, i32 12, i32 4, i32 11, i32 5, i32 10, i32 6, i32 9, i32 7, i32 8>
%r = bitcast <16 x i8> %y to <8 x i16>
diff --git a/llvm/test/CodeGen/LoongArch/lsx/vec-zext.ll b/llvm/test/CodeGen/LoongArch/lsx/vec-zext.ll
index bbcfbe1b07260..602c0f1a5a910 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/vec-zext.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/vec-zext.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc --mtriple=loongarch64 --mattr=+lsx %s -o - | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx %s -o - | FileCheck %s --check-prefixes=CHECK,LA64
define void @load_zext_2i8_to_2i64(ptr %ptr, ptr %dst) {
@@ -38,14 +39,25 @@ entry:
}
define void @load_zext_8i8_to_8i16(ptr %ptr, ptr %dst) {
-; CHECK-LABEL: load_zext_8i8_to_8i16:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: ld.d $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0
-; CHECK-NEXT: vrepli.b $vr1, 0
-; CHECK-NEXT: vilvl.b $vr0, $vr1, $vr0
-; CHECK-NEXT: vst $vr0, $a1, 0
-; CHECK-NEXT: ret
+; LA32-LABEL: load_zext_8i8_to_8i16:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: ld.w $a2, $a0, 0
+; LA32-NEXT: ld.w $a0, $a0, 4
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: vrepli.b $vr1, 0
+; LA32-NEXT: vilvl.b $vr0, $vr1, $vr0
+; LA32-NEXT: vst $vr0, $a1, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: load_zext_8i8_to_8i16:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: ld.d $a0, $a0, 0
+; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: vrepli.b $vr1, 0
+; LA64-NEXT: vilvl.b $vr0, $vr1, $vr0
+; LA64-NEXT: vst $vr0, $a1, 0
+; LA64-NEXT: ret
entry:
%A = load <8 x i8>, ptr %ptr
%B = zext <8 x i8> %A to <8 x i16>
@@ -71,14 +83,25 @@ entry:
}
define void @load_zext_4i16_to_4i32(ptr %ptr, ptr %dst) {
-; CHECK-LABEL: load_zext_4i16_to_4i32:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: ld.d $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0
-; CHECK-NEXT: vrepli.b $vr1, 0
-; CHECK-NEXT: vilvl.h $vr0, $vr1, $vr0
-; CHECK-NEXT: vst $vr0, $a1, 0
-; CHECK-NEXT: ret
+; LA32-LABEL: load_zext_4i16_to_4i32:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: ld.w $a2, $a0, 0
+; LA32-NEXT: ld.w $a0, $a0, 4
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 1
+; LA32-NEXT: vrepli.b $vr1, 0
+; LA32-NEXT: vilvl.h $vr0, $vr1, $vr0
+; LA32-NEXT: vst $vr0, $a1, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: load_zext_4i16_to_4i32:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: ld.d $a0, $a0, 0
+; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: vrepli.b $vr1, 0
+; LA64-NEXT: vilvl.h $vr0, $vr1, $vr0
+; LA64-NEXT: vst $vr0, $a1, 0
+; LA64-NEXT: ret
entry:
%A = load <4 x i16>, ptr %ptr
%B = zext <4 x i16> %A to <4 x i32>
@@ -87,14 +110,24 @@ entry:
}
define void @load_zext_2i32_to_2i64(ptr %ptr, ptr %dst) {
-; CHECK-LABEL: load_zext_2i32_to_2i64:
-; CHECK: # %bb.0: # %entry
-; CHECK-NEXT: ld.d $a0, $a0, 0
-; CHECK-NEXT: vinsgr2vr.d $vr0, $a0, 0
-; CHECK-NEXT: vrepli.b $vr1, 0
-; CHECK-NEXT: vilvl.w $vr0, $vr1, $vr0
-; CHECK-NEXT: vst $vr0, $a1, 0
-; CHECK-NEXT: ret
+; LA32-LABEL: load_zext_2i32_to_2i64:
+; LA32: # %bb.0: # %entry
+; LA32-NEXT: ld.w $a2, $a0, 0
+; LA32-NEXT: ld.w $a0, $a0, 4
+; LA32-NEXT: vrepli.b $vr0, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a2, 0
+; LA32-NEXT: vinsgr2vr.w $vr0, $a0, 2
+; LA32-NEXT: vst $vr0, $a1, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: load_zext_2i32_to_2i64:
+; LA64: # %bb.0: # %entry
+; LA64-NEXT: ld.d $a0, $a0, 0
+; LA64-NEXT: vinsgr2vr.d $vr0, $a0, 0
+; LA64-NEXT: vrepli.b $vr1, 0
+; LA64-NEXT: vilvl.w $vr0, $vr1, $vr0
+; LA64-NEXT: vst $vr0, $a1, 0
+; LA64-NEXT: ret
entry:
%A = load <2 x i32>, ptr %ptr
%B = zext <2 x i32> %A to <2 x i64>
diff --git a/llvm/test/CodeGen/LoongArch/lsx/vselect.ll b/llvm/test/CodeGen/LoongArch/lsx/vselect.ll
index 4d2ddeb2889bb..5dbff4a402b3d 100644
--- a/llvm/test/CodeGen/LoongArch/lsx/vselect.ll
+++ b/llvm/test/CodeGen/LoongArch/lsx/vselect.ll
@@ -1,5 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s
+; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA32
+; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s --check-prefixes=CHECK,LA64
define void @select_v16i8_imm(ptr %res, ptr %a0) nounwind {
; CHECK-LABEL: select_v16i8_imm:
@@ -49,16 +50,26 @@ define void @select_v8i16(ptr %res, ptr %a0, ptr %a1) nounwind {
}
define void @select_v4i32(ptr %res, ptr %a0, ptr %a1) nounwind {
-; CHECK-LABEL: select_v4i32:
-; CHECK: # %bb.0:
-; CHECK-NEXT: vld $vr0, $a1, 0
-; CHECK-NEXT: vld $vr1, $a2, 0
-; CHECK-NEXT: ori $a1, $zero, 0
-; CHECK-NEXT: lu32i.d $a1, -1
-; CHECK-NEXT: vreplgr2vr.d $vr2, $a1
-; CHECK-NEXT: vbitsel.v $vr0, $vr1, $vr0, $vr2
-; CHECK-NEXT: vst $vr0, $a0, 0
-; CHECK-NEXT: ret
+; LA32-LABEL: select_v4i32:
+; LA32: # %bb.0:
+; LA32-NEXT: vld $vr0, $a1, 0
+; LA32-NEXT: vld $vr1, $a2, 0
+; LA32-NEXT: pcalau12i $a1, %pc_hi20(.LCPI3_0)
+; LA32-NEXT: vld $vr2, $a1, %pc_lo12(.LCPI3_0)
+; LA32-NEXT: vbitsel.v $vr0, $vr1, $vr0, $vr2
+; LA32-NEXT: vst $vr0, $a0, 0
+; LA32-NEXT: ret
+;
+; LA64-LABEL: select_v4i32:
+; LA64: # %bb.0:
+; LA64-NEXT: vld $vr0, $a1, 0
+; LA64-NEXT: vld $vr1, $a2, 0
+; LA64-NEXT: ori $a1, $zero, 0
+; LA64-NEXT: lu32i.d $a1, -1
+; LA64-NEXT: vreplgr2vr.d $vr2, $a1
+; LA64-NEXT: vbitsel.v $vr0, $vr1, $vr0, $vr2
+; LA64-NEXT: vst $vr0, $a0, 0
+; LA64-NEXT: ret
%v0 = load <4 x i32>, ptr %a0
%v1 = load <4 x i32>, ptr %a1
%sel = select <4 x i1> <i1 false, i1 true, i1 false, i1 true>, <4 x i32> %v0, <4 x i32> %v1
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