[llvm] [InstCombine] Fold select pattern with sub and negation to abs intrinsic (PR #156246)
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Sun Aug 31 07:08:38 PDT 2025
https://github.com/AZero13 updated https://github.com/llvm/llvm-project/pull/156246
>From b75498308f49aca3af6e2dd6b6e7b4035cc2d97d Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Sun, 31 Aug 2025 09:57:35 -0400
Subject: [PATCH 1/2] Pre-commit test (NFC)
---
.../Transforms/InstCombine/abs-intrinsic.ll | 76 +++++++++++++++++++
1 file changed, 76 insertions(+)
diff --git a/llvm/test/Transforms/InstCombine/abs-intrinsic.ll b/llvm/test/Transforms/InstCombine/abs-intrinsic.ll
index 346111d892975..4f8fef17ac9a0 100644
--- a/llvm/test/Transforms/InstCombine/abs-intrinsic.ll
+++ b/llvm/test/Transforms/InstCombine/abs-intrinsic.ll
@@ -859,4 +859,80 @@ define i32 @abs_range_metadata(i32 %x) {
%b = and i32 %a, 15
ret i32 %b
}
+
!1 = !{i32 0, i32 16}
+
+define i32 @abs_diff(i32 %x, i32 %y) {
+; CHECK-LABEL: @abs_diff(
+; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X]], [[Y]]
+; CHECK-NEXT: [[SUB1:%.*]] = sub i32 0, [[SUB]]
+; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[SUB1]]
+; CHECK-NEXT: ret i32 [[COND]]
+;
+ %sub = sub nsw i32 %x, %y
+ %cmp = icmp sgt i32 %x, %y
+ %sub1 = sub i32 0, %sub
+ %cond = select i1 %cmp, i32 %sub, i32 %sub1
+ ret i32 %cond
+}
+
+define i32 @abs_diff_neg_no_nsw_neg(i32 %x, i32 %y) {
+; CHECK-LABEL: @abs_diff_neg_no_nsw_neg(
+; CHECK-NEXT: [[SUB:%.*]] = sub i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X]], [[Y]]
+; CHECK-NEXT: [[SUB1:%.*]] = sub i32 0, [[SUB]]
+; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[SUB1]]
+; CHECK-NEXT: ret i32 [[COND]]
+;
+ %sub = sub i32 %x, %y
+ %cmp = icmp sgt i32 %x, %y
+ %sub1 = sub i32 0, %sub
+ %cond = select i1 %cmp, i32 %sub, i32 %sub1
+ ret i32 %cond
+}
+
+define i32 @abs_diff_neg(i32 %x, i32 %y) {
+; CHECK-LABEL: @abs_diff_neg(
+; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[Y:%.*]], [[X:%.*]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X]], [[Y]]
+; CHECK-NEXT: [[SUB1:%.*]] = sub i32 0, [[SUB]]
+; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[SUB1]]
+; CHECK-NEXT: ret i32 [[COND]]
+;
+ %sub = sub nsw i32 %y, %x
+ %cmp = icmp sgt i32 %x, %y
+ %sub1 = sub i32 0, %sub
+ %cond = select i1 %cmp, i32 %sub, i32 %sub1
+ ret i32 %cond
+}
+
+define i32 @abs_diff_neg_no_nsw(i32 %x, i32 %y) {
+; CHECK-LABEL: @abs_diff_neg_no_nsw(
+; CHECK-NEXT: [[SUB:%.*]] = sub i32 [[Y:%.*]], [[X:%.*]]
+; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X]], [[Y]]
+; CHECK-NEXT: [[SUB1:%.*]] = sub i32 0, [[SUB]]
+; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[SUB1]]
+; CHECK-NEXT: ret i32 [[COND]]
+;
+ %sub = sub i32 %y, %x
+ %cmp = icmp sgt i32 %x, %y
+ %sub1 = sub i32 0, %sub
+ %cond = select i1 %cmp, i32 %sub, i32 %sub1
+ ret i32 %cond
+}
+
+define i32 @abs_diff_ge(i32 %x, i32 %y) {
+; CHECK-LABEL: @abs_diff_ge(
+; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp slt i32 [[X]], [[Y]]
+; CHECK-NEXT: [[SUB1:%.*]] = sub i32 0, [[SUB]]
+; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP_NOT]], i32 [[SUB1]], i32 [[SUB]]
+; CHECK-NEXT: ret i32 [[COND]]
+;
+ %sub = sub nsw i32 %x, %y
+ %cmp = icmp sge i32 %x, %y
+ %sub1 = sub i32 0, %sub
+ %cond = select i1 %cmp, i32 %sub, i32 %sub1
+ ret i32 %cond
+}
>From f9153be78050debe84f5ec79533c8d232c1176c3 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Sun, 31 Aug 2025 10:05:52 -0400
Subject: [PATCH 2/2] [InstCombine] Fold select pattern with sub and negation
to abs intrinsic
This patch adds a new fold in InstCombine to recognize and optimize a common absolute value pattern.
```llvm
%sub = sub nsw T %x, %y
%cmp = icmp sgt T %x, %y ; or sge
%neg = sub T 0, %sub
%abs = select i1 %cmp, T %sub, T %neg
```
becomes:|
```llvm
%sub = sub nsw T %x, %y
%abs = call T @llvm.abs.T(T %sub, i1 false)
```
---
llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp | 9 +++++++++
llvm/test/Transforms/InstCombine/abs-intrinsic.ll | 8 ++------
2 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
index eb4332fbc0959..d75e34f90d469 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
@@ -1153,6 +1153,15 @@ static Value *foldAbsDiff(ICmpInst *Cmp, Value *TVal, Value *FVal,
return Builder.CreateBinaryIntrinsic(Intrinsic::abs, TI, Builder.getTrue());
}
+ // Match: (A > B) ? (A - B) : (0 - (A - B)) --> abs(A - B)
+ // Recognize the pattern where we have sub, icmp, neg(sub), select
+ if (Pred == CmpInst::ICMP_SGT &&
+ match(TI, m_Sub(m_Specific(A), m_Specific(B))) &&
+ match(FI, m_Neg(m_Specific(TI))) &&
+ TI->hasNoSignedWrap()) {
+ return Builder.CreateBinaryIntrinsic(Intrinsic::abs, TI, Builder.getFalse());
+ }
+
return nullptr;
}
diff --git a/llvm/test/Transforms/InstCombine/abs-intrinsic.ll b/llvm/test/Transforms/InstCombine/abs-intrinsic.ll
index 4f8fef17ac9a0..689840eeef69a 100644
--- a/llvm/test/Transforms/InstCombine/abs-intrinsic.ll
+++ b/llvm/test/Transforms/InstCombine/abs-intrinsic.ll
@@ -865,9 +865,7 @@ define i32 @abs_range_metadata(i32 %x) {
define i32 @abs_diff(i32 %x, i32 %y) {
; CHECK-LABEL: @abs_diff(
; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[X]], [[Y]]
-; CHECK-NEXT: [[SUB1:%.*]] = sub i32 0, [[SUB]]
-; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP]], i32 [[SUB]], i32 [[SUB1]]
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.abs.i32(i32 [[SUB]], i1 false)
; CHECK-NEXT: ret i32 [[COND]]
;
%sub = sub nsw i32 %x, %y
@@ -925,9 +923,7 @@ define i32 @abs_diff_neg_no_nsw(i32 %x, i32 %y) {
define i32 @abs_diff_ge(i32 %x, i32 %y) {
; CHECK-LABEL: @abs_diff_ge(
; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 [[X:%.*]], [[Y:%.*]]
-; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp slt i32 [[X]], [[Y]]
-; CHECK-NEXT: [[SUB1:%.*]] = sub i32 0, [[SUB]]
-; CHECK-NEXT: [[COND:%.*]] = select i1 [[CMP_NOT]], i32 [[SUB1]], i32 [[SUB]]
+; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.abs.i32(i32 [[SUB]], i1 false)
; CHECK-NEXT: ret i32 [[COND]]
;
%sub = sub nsw i32 %x, %y
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