[llvm] [NFC][MC][ARM] Rearrange decoder functions 3/N (PR #156240)

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git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
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``````````diff
diff --git a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
index 11680095b..ad6b330e2 100644
--- a/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
+++ b/llvm/lib/Target/ARM/Disassembler/ARMDisassembler.cpp
@@ -6668,7 +6668,8 @@ void ARMDisassembler::AddThumb1SBit(MCInst &MI, bool InITBlock) const {
   const MCInstrDesc &MCID = MCII->get(MI.getOpcode());
   MCInst::iterator I = MI.begin();
   for (unsigned i = 0; i < MCID.NumOperands; ++i, ++I) {
-    if (I == MI.end()) break;
+    if (I == MI.end())
+      break;
     if (MCID.operands()[i].isOptionalDef() &&
         MCID.operands()[i].RegClass == ARM::CCRRegClassID) {
       if (i > 0 && MCID.operands()[i - 1].isPredicate())
@@ -6704,42 +6705,43 @@ ARMDisassembler::AddThumbPredicate(MCInst &MI) const {
   // A few instructions actually have predicates encoded in them.  Don't
   // try to overwrite it if we're seeing one of those.
   switch (MI.getOpcode()) {
-    case ARM::tBcc:
-    case ARM::t2Bcc:
-    case ARM::tCBZ:
-    case ARM::tCBNZ:
-    case ARM::tCPS:
-    case ARM::t2CPS3p:
-    case ARM::t2CPS2p:
-    case ARM::t2CPS1p:
-    case ARM::t2CSEL:
-    case ARM::t2CSINC:
-    case ARM::t2CSINV:
-    case ARM::t2CSNEG:
-    case ARM::tMOVSr:
-    case ARM::tSETEND:
-      // Some instructions (mostly conditional branches) are not
-      // allowed in IT blocks.
-      if (ITBlock.instrInITBlock())
-        S = SoftFail;
-      else
-        return Success;
-      break;
-    case ARM::t2HINT:
-      if (MI.getOperand(0).getImm() == 0x10 && (FeatureBits[ARM::FeatureRAS]) != 0)
-        S = SoftFail;
-      break;
-    case ARM::tB:
-    case ARM::t2B:
-    case ARM::t2TBB:
-    case ARM::t2TBH:
-      // Some instructions (mostly unconditional branches) can
-      // only appears at the end of, or outside of, an IT.
-      if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
-        S = SoftFail;
-      break;
-    default:
-      break;
+  case ARM::tBcc:
+  case ARM::t2Bcc:
+  case ARM::tCBZ:
+  case ARM::tCBNZ:
+  case ARM::tCPS:
+  case ARM::t2CPS3p:
+  case ARM::t2CPS2p:
+  case ARM::t2CPS1p:
+  case ARM::t2CSEL:
+  case ARM::t2CSINC:
+  case ARM::t2CSINV:
+  case ARM::t2CSNEG:
+  case ARM::tMOVSr:
+  case ARM::tSETEND:
+    // Some instructions (mostly conditional branches) are not
+    // allowed in IT blocks.
+    if (ITBlock.instrInITBlock())
+      S = SoftFail;
+    else
+      return Success;
+    break;
+  case ARM::t2HINT:
+    if (MI.getOperand(0).getImm() == 0x10 &&
+        (FeatureBits[ARM::FeatureRAS]) != 0)
+      S = SoftFail;
+    break;
+  case ARM::tB:
+  case ARM::t2B:
+  case ARM::t2TBB:
+  case ARM::t2TBH:
+    // Some instructions (mostly unconditional branches) can
+    // only appears at the end of, or outside of, an IT.
+    if (ITBlock.instrInITBlock() && !ITBlock.instrLastInITBlock())
+      S = SoftFail;
+    break;
+  default:
+    break;
   }
 
   // Warn on non-VPT predicable instruction in a VPT block and a VPT

``````````

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https://github.com/llvm/llvm-project/pull/156240