[llvm] [RISCV] add computeKnownBitsForTargetNode for RISCVISD::SRLW (PR #155995)

[Shreeyash Pandey via llvm-commits]

bojle wrote:

I've re-written this based on the output of 'llc'. The last part:
```
auto Py2 = DAG->getConstant(4294967295, Loc, Int64VT);
auto N3 = DAG->getNode(ISD::AND, Loc, Int64VT, N2, Py2);
```
is still redundant, but i've kept it for sake of imitating the generated DAG. 

https://github.com/llvm/llvm-project/pull/155995