[llvm] [RISCV] Use C.ADD when OR is not compressible due to register restriction (PR #156044)

[Sam Elliott via llvm-commits]

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@@ -1178,7 +1178,21 @@ bool RISCVAsmPrinter::lowerToMCInst(const MachineInstr *MI, MCInst &OutMI) {
   if (lowerRISCVVMachineInstrToMCInst(MI, OutMI, STI))
     return false;
 
-  OutMI.setOpcode(MI->getOpcode());
+  unsigned Opcode = MI->getOpcode();
+  // If we have a disjoint OR which isn't compressible as an c.or, we can
+  // convert it to a c.add which doesn't have the gprc register restriction.
+  if (STI->hasStdExtZca() && Opcode == RISCV::OR &&
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lenary wrote:

I'm not super happy with the choice to do this here, honestly. This is mostly a rote function, and I don't think users would expect changes to happen in it.

Given you're not changing register allocation, can we do it in one of two places:
- A CompressPat, with `isCompressOnly=true`. I realise we might not be able to control the priority of the two patterns, but I think right now the system uses file order?
- RISCVMakeCompressible - where we're sort-of expecting optimisations like this.

https://github.com/llvm/llvm-project/pull/156044