[llvm] [RISCV] Eagerly optimize scalar packing for buildvector lowering (PR #156062)
Philip Reames via llvm-commits
llvm-commits at lists.llvm.org
Sat Aug 30 18:59:29 PDT 2025
https://github.com/preames updated https://github.com/llvm/llvm-project/pull/156062
>From 482102c02639acd6d46b6a9c4fa6fb2ed901e468 Mon Sep 17 00:00:00 2001
From: Philip Reames <preames at rivosinc.com>
Date: Fri, 29 Aug 2025 10:02:14 -0700
Subject: [PATCH 1/4] [RISCV] Eagerly optimize scalar packing for buildvector
lowering
Instead of relying on DAG to cleanup the redundant ANDs, go ahead
actively try to prove them redundant at construction.
I noticed this because SimplifyDemandedBits was dropping the
disjoint on the OR, but there's at least one other codegen diff
in the tests as well.
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 7 +++++--
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll | 2 +-
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 4c39bcf8494a4..80083f843f9af 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -4257,6 +4257,7 @@ static SDValue lowerBuildVectorViaPacking(SDValue Op, SelectionDAG &DAG,
MVT XLenVT = Subtarget.getXLenVT();
SDValue Mask = DAG.getConstant(
APInt::getLowBitsSet(XLenVT.getSizeInBits(), ElemSizeInBits), DL, XLenVT);
+ unsigned ZeroPrefix = XLenVT.getSizeInBits() - ElemSizeInBits;
auto pack = [&](SDValue A, SDValue B) {
// Bias the scheduling of the inserted operations to near the
// definition of the element - this tends to reduce register
@@ -4270,8 +4271,10 @@ static SDValue lowerBuildVectorViaPacking(SDValue Op, SelectionDAG &DAG,
ElemDL, XLenVT, A, B),
0);
- A = DAG.getNode(ISD::AND, SDLoc(A), XLenVT, A, Mask);
- B = DAG.getNode(ISD::AND, SDLoc(B), XLenVT, B, Mask);
+ if (DAG.computeKnownBits(A).countMinLeadingZeros() < ZeroPrefix)
+ A = DAG.getNode(ISD::AND, SDLoc(A), XLenVT, A, Mask);
+ if (DAG.computeKnownBits(B).countMinLeadingZeros() < ZeroPrefix)
+ B = DAG.getNode(ISD::AND, SDLoc(B), XLenVT, B, Mask);
SDValue ShtAmt = DAG.getConstant(ElemSizeInBits, ElemDL, XLenVT);
return DAG.getNode(ISD::OR, ElemDL, XLenVT, A,
DAG.getNode(ISD::SHL, ElemDL, XLenVT, B, ShtAmt),
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
index d9bb007a10f71..8aaffd41cbd16 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-buildvec.ll
@@ -2629,7 +2629,7 @@ define <16 x i8> @buildvec_v16i8_undef_edges(ptr %p) {
; RVA22U64-NEXT: or a0, a0, a4
; RVA22U64-NEXT: slli a6, a6, 24
; RVA22U64-NEXT: or a1, a1, a2
-; RVA22U64-NEXT: add.uw a1, a6, a1
+; RVA22U64-NEXT: or a1, a6, a1
; RVA22U64-NEXT: or a0, a0, a3
; RVA22U64-NEXT: vsetivli zero, 2, e64, m1, ta, ma
; RVA22U64-NEXT: vmv.v.x v8, a1
>From 1fef56edae697f51dd3f03d207d2f1df34c272f4 Mon Sep 17 00:00:00 2001
From: Philip Reames <preames at rivosinc.com>
Date: Fri, 29 Aug 2025 10:15:35 -0700
Subject: [PATCH 2/4] Missing comment
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 80083f843f9af..efd0d779680d4 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -4271,6 +4271,8 @@ static SDValue lowerBuildVectorViaPacking(SDValue Op, SelectionDAG &DAG,
ElemDL, XLenVT, A, B),
0);
+ // Manually optimize away the ANDs if we can, DAGCombiner will
+ // sometimes end of perturbing codegen if we don't.
if (DAG.computeKnownBits(A).countMinLeadingZeros() < ZeroPrefix)
A = DAG.getNode(ISD::AND, SDLoc(A), XLenVT, A, Mask);
if (DAG.computeKnownBits(B).countMinLeadingZeros() < ZeroPrefix)
>From 00d1907b55cf9ede90bae25a33a3a9902be304f3 Mon Sep 17 00:00:00 2001
From: Philip Reames <preames at rivosinc.com>
Date: Sat, 30 Aug 2025 18:51:10 -0700
Subject: [PATCH 3/4] Update llvm/lib/Target/RISCV/RISCVISelLowering.cpp
Co-authored-by: Craig Topper <craig.topper at sifive.com>
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index efd0d779680d4..34fce5da829e9 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -4272,7 +4272,7 @@ static SDValue lowerBuildVectorViaPacking(SDValue Op, SelectionDAG &DAG,
0);
// Manually optimize away the ANDs if we can, DAGCombiner will
- // sometimes end of perturbing codegen if we don't.
+ // sometimes end up perturbing codegen if we don't.
if (DAG.computeKnownBits(A).countMinLeadingZeros() < ZeroPrefix)
A = DAG.getNode(ISD::AND, SDLoc(A), XLenVT, A, Mask);
if (DAG.computeKnownBits(B).countMinLeadingZeros() < ZeroPrefix)
>From bd98ff06fda7632313818cb744cede44c73d5b8b Mon Sep 17 00:00:00 2001
From: Philip Reames <preames at rivosinc.com>
Date: Sat, 30 Aug 2025 18:53:59 -0700
Subject: [PATCH 4/4] Address review comment
---
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 34fce5da829e9..d44d8bc289c8d 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -4257,7 +4257,6 @@ static SDValue lowerBuildVectorViaPacking(SDValue Op, SelectionDAG &DAG,
MVT XLenVT = Subtarget.getXLenVT();
SDValue Mask = DAG.getConstant(
APInt::getLowBitsSet(XLenVT.getSizeInBits(), ElemSizeInBits), DL, XLenVT);
- unsigned ZeroPrefix = XLenVT.getSizeInBits() - ElemSizeInBits;
auto pack = [&](SDValue A, SDValue B) {
// Bias the scheduling of the inserted operations to near the
// definition of the element - this tends to reduce register
@@ -4273,9 +4272,9 @@ static SDValue lowerBuildVectorViaPacking(SDValue Op, SelectionDAG &DAG,
// Manually optimize away the ANDs if we can, DAGCombiner will
// sometimes end up perturbing codegen if we don't.
- if (DAG.computeKnownBits(A).countMinLeadingZeros() < ZeroPrefix)
+ if (DAG.computeKnownBits(A).countMaxActiveBits() > ElemSizeInBits)
A = DAG.getNode(ISD::AND, SDLoc(A), XLenVT, A, Mask);
- if (DAG.computeKnownBits(B).countMinLeadingZeros() < ZeroPrefix)
+ if (DAG.computeKnownBits(B).countMaxActiveBits() > ElemSizeInBits)
B = DAG.getNode(ISD::AND, SDLoc(B), XLenVT, B, Mask);
SDValue ShtAmt = DAG.getConstant(ElemSizeInBits, ElemDL, XLenVT);
return DAG.getNode(ISD::OR, ElemDL, XLenVT, A,
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