[llvm] 31c9198 - [RISCV] Add test coverage for reassociation with poison generating flags

Philip Reames via llvm-commits llvm-commits at lists.llvm.org
Sat Aug 30 18:18:26 PDT 2025


Author: Philip Reames
Date: 2025-08-30T18:18:10-07:00
New Revision: 31c9198ea0f9651b8d18548d4a4bff252680f804

URL: https://github.com/llvm/llvm-project/commit/31c9198ea0f9651b8d18548d4a4bff252680f804
DIFF: https://github.com/llvm/llvm-project/commit/31c9198ea0f9651b8d18548d4a4bff252680f804.diff

LOG: [RISCV] Add test coverage for reassociation with poison generating flags

The 'add' case is correct, the 'or' case is coverage for an upcoming
change to fix a bug w.r.t flag preservation.

Added: 
    

Modified: 
    llvm/test/CodeGen/RISCV/machine-combiner-mir.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/CodeGen/RISCV/machine-combiner-mir.ll b/llvm/test/CodeGen/RISCV/machine-combiner-mir.ll
index 1a78419f56a67..a74dc57a46c82 100644
--- a/llvm/test/CodeGen/RISCV/machine-combiner-mir.ll
+++ b/llvm/test/CodeGen/RISCV/machine-combiner-mir.ll
@@ -104,3 +104,45 @@ define double @test_fmadd(double %a0, double %a1, double %a2) {
   %t2 = fdiv double %t1, %t0
   ret double %t2
 }
+
+
+define i64 @test_or_flags(i64 %a0, i64 %a1, i64 %a2, i64 %a3) {
+  ; CHECK-LABEL: name: test_or_flags
+  ; CHECK: bb.0 (%ir-block.0):
+  ; CHECK-NEXT:   liveins: $x10, $x11, $x12, $x13
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $x13
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x12
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr = COPY $x11
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gpr = COPY $x10
+  ; CHECK-NEXT:   [[OR:%[0-9]+]]:gpr = OR [[COPY3]], [[COPY2]]
+  ; CHECK-NEXT:   [[OR1:%[0-9]+]]:gpr = disjoint OR [[COPY1]], [[COPY]]
+  ; CHECK-NEXT:   [[OR2:%[0-9]+]]:gpr = disjoint OR killed [[OR]], killed [[OR1]]
+  ; CHECK-NEXT:   $x10 = COPY [[OR2]]
+  ; CHECK-NEXT:   PseudoRET implicit $x10
+  %t0 = or i64 %a0, %a1
+  %t1 = or disjoint i64 %t0, %a2
+  %t2 = or disjoint i64 %t1, %a3
+  ret i64 %t2
+}
+
+define i64 @test_add_flags(i64 %a0, i64 %a1, i64 %a2, i64 %a3) {
+  ; CHECK-LABEL: name: test_add_flags
+  ; CHECK: bb.0 (%ir-block.0):
+  ; CHECK-NEXT:   liveins: $x10, $x11, $x12, $x13
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr = COPY $x13
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr = COPY $x12
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr = COPY $x11
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gpr = COPY $x10
+  ; CHECK-NEXT:   [[ADD:%[0-9]+]]:gpr = ADD [[COPY3]], [[COPY2]]
+  ; CHECK-NEXT:   [[ADD1:%[0-9]+]]:gpr = ADD [[COPY1]], [[COPY]]
+  ; CHECK-NEXT:   [[ADD2:%[0-9]+]]:gpr = ADD killed [[ADD]], killed [[ADD1]]
+  ; CHECK-NEXT:   $x10 = COPY [[ADD2]]
+  ; CHECK-NEXT:   PseudoRET implicit $x10
+  %t0 = add i64 %a0, %a1
+  %t1 = add nsw i64 %t0, %a2
+  %t2 = add nuw i64 %t1, %a3
+  ret i64 %t2
+}
+


        


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