[llvm] [TargetLowering] Only freeze LHS and RHS if they are used multiple times (PR #156193)

[via llvm-commits]

https://github.com/AZero13 updated https://github.com/llvm/llvm-project/pull/156193

>From 5d5b4fa42b984cd7c02962a3d0bb092e05a1fe87 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Sat, 30 Aug 2025 13:43:13 -0400
Subject: [PATCH] [TargetLowering] Only freeze LHS and RHS if they are used
 multiple times

---
 llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 13 ++++++++++---
 llvm/test/CodeGen/Thumb2/abds-crash.ll           | 12 ++++++------
 2 files changed, 16 insertions(+), 9 deletions(-)

diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 402a012e8e555..bd436f7d3e536 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -9740,8 +9740,8 @@ SDValue TargetLowering::expandABS(SDNode *N, SelectionDAG &DAG,
 SDValue TargetLowering::expandABD(SDNode *N, SelectionDAG &DAG) const {
   SDLoc dl(N);
   EVT VT = N->getValueType(0);
-  SDValue LHS = DAG.getFreeze(N->getOperand(0));
-  SDValue RHS = DAG.getFreeze(N->getOperand(1));
+  SDValue LHS = N->getOperand(0);
+  SDValue RHS = N->getOperand(1);
   bool IsSigned = N->getOpcode() == ISD::ABDS;
 
   // abds(lhs, rhs) -> sub(smax(lhs,rhs), smin(lhs,rhs))
@@ -9749,16 +9749,21 @@ SDValue TargetLowering::expandABD(SDNode *N, SelectionDAG &DAG) const {
   unsigned MaxOpc = IsSigned ? ISD::SMAX : ISD::UMAX;
   unsigned MinOpc = IsSigned ? ISD::SMIN : ISD::UMIN;
   if (isOperationLegal(MaxOpc, VT) && isOperationLegal(MinOpc, VT)) {
+    LHS = DAG.getFreeze(LHS);
+    RHS = DAG.getFreeze(RHS);
     SDValue Max = DAG.getNode(MaxOpc, dl, VT, LHS, RHS);
     SDValue Min = DAG.getNode(MinOpc, dl, VT, LHS, RHS);
     return DAG.getNode(ISD::SUB, dl, VT, Max, Min);
   }
 
   // abdu(lhs, rhs) -> or(usubsat(lhs,rhs), usubsat(rhs,lhs))
-  if (!IsSigned && isOperationLegal(ISD::USUBSAT, VT))
+  if (!IsSigned && isOperationLegal(ISD::USUBSAT, VT)) {
+    LHS = DAG.getFreeze(LHS);
+    RHS = DAG.getFreeze(RHS);
     return DAG.getNode(ISD::OR, dl, VT,
                        DAG.getNode(ISD::USUBSAT, dl, VT, LHS, RHS),
                        DAG.getNode(ISD::USUBSAT, dl, VT, RHS, LHS));
+  }
 
   // If the subtract doesn't overflow then just use abs(sub())
   // NOTE: don't use frozen operands for value tracking.
@@ -9777,6 +9782,8 @@ SDValue TargetLowering::expandABD(SDNode *N, SelectionDAG &DAG) const {
 
   EVT CCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
   ISD::CondCode CC = IsSigned ? ISD::CondCode::SETGT : ISD::CondCode::SETUGT;
+  LHS = DAG.getFreeze(LHS);
+  RHS = DAG.getFreeze(RHS);
   SDValue Cmp = DAG.getSetCC(dl, CCVT, LHS, RHS, CC);
 
   // Branchless expansion iff cmp result is allbits:
diff --git a/llvm/test/CodeGen/Thumb2/abds-crash.ll b/llvm/test/CodeGen/Thumb2/abds-crash.ll
index 52dda72dffa0e..2c872df178e97 100644
--- a/llvm/test/CodeGen/Thumb2/abds-crash.ll
+++ b/llvm/test/CodeGen/Thumb2/abds-crash.ll
@@ -9,13 +9,13 @@ define void @vp8_rd_pick_inter_mode() {
 ; CHECK-NEXT:    push {r4, lr}
 ; CHECK-NEXT:    movs r4, #0
 ; CHECK-NEXT:    ldr r0, [r0]
-; CHECK-NEXT:    ldr r1, [r4]
-; CHECK-NEXT:    movs r2, #180
-; CHECK-NEXT:    str r0, [r2]
-; CHECK-NEXT:    movs r2, #188
+; CHECK-NEXT:    ldr r2, [r4]
+; CHECK-NEXT:    movs r1, #180
+; CHECK-NEXT:    str r0, [r1]
+; CHECK-NEXT:    movs r1, #188
 ; CHECK-NEXT:    sxth r0, r0
-; CHECK-NEXT:    str r1, [r2]
-; CHECK-NEXT:    sxth r1, r1
+; CHECK-NEXT:    str r2, [r1]
+; CHECK-NEXT:    sxth r1, r2
 ; CHECK-NEXT:    subs r0, r0, r1
 ; CHECK-NEXT:    it mi
 ; CHECK-NEXT:    rsbmi r0, r0, #0