[llvm] [TargetLowering] Only freeze LHS and RHS if they are used multiple times (PR #156193)
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Sat Aug 30 10:46:26 PDT 2025
https://github.com/AZero13 updated https://github.com/llvm/llvm-project/pull/156193
>From 831149232b9ad8a1ca706521371d8da1fcd224b2 Mon Sep 17 00:00:00 2001
From: AZero13 <gfunni234 at gmail.com>
Date: Sat, 30 Aug 2025 13:43:13 -0400
Subject: [PATCH] [TargetLowering] Only freeze LHS and RHS if they are used
multiple times
---
.../CodeGen/SelectionDAG/TargetLowering.cpp | 13 +++--
llvm/test/CodeGen/X86/abdu-neg.ll | 54 +++++++++----------
2 files changed, 37 insertions(+), 30 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 402a012e8e555..bd436f7d3e536 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -9740,8 +9740,8 @@ SDValue TargetLowering::expandABS(SDNode *N, SelectionDAG &DAG,
SDValue TargetLowering::expandABD(SDNode *N, SelectionDAG &DAG) const {
SDLoc dl(N);
EVT VT = N->getValueType(0);
- SDValue LHS = DAG.getFreeze(N->getOperand(0));
- SDValue RHS = DAG.getFreeze(N->getOperand(1));
+ SDValue LHS = N->getOperand(0);
+ SDValue RHS = N->getOperand(1);
bool IsSigned = N->getOpcode() == ISD::ABDS;
// abds(lhs, rhs) -> sub(smax(lhs,rhs), smin(lhs,rhs))
@@ -9749,16 +9749,21 @@ SDValue TargetLowering::expandABD(SDNode *N, SelectionDAG &DAG) const {
unsigned MaxOpc = IsSigned ? ISD::SMAX : ISD::UMAX;
unsigned MinOpc = IsSigned ? ISD::SMIN : ISD::UMIN;
if (isOperationLegal(MaxOpc, VT) && isOperationLegal(MinOpc, VT)) {
+ LHS = DAG.getFreeze(LHS);
+ RHS = DAG.getFreeze(RHS);
SDValue Max = DAG.getNode(MaxOpc, dl, VT, LHS, RHS);
SDValue Min = DAG.getNode(MinOpc, dl, VT, LHS, RHS);
return DAG.getNode(ISD::SUB, dl, VT, Max, Min);
}
// abdu(lhs, rhs) -> or(usubsat(lhs,rhs), usubsat(rhs,lhs))
- if (!IsSigned && isOperationLegal(ISD::USUBSAT, VT))
+ if (!IsSigned && isOperationLegal(ISD::USUBSAT, VT)) {
+ LHS = DAG.getFreeze(LHS);
+ RHS = DAG.getFreeze(RHS);
return DAG.getNode(ISD::OR, dl, VT,
DAG.getNode(ISD::USUBSAT, dl, VT, LHS, RHS),
DAG.getNode(ISD::USUBSAT, dl, VT, RHS, LHS));
+ }
// If the subtract doesn't overflow then just use abs(sub())
// NOTE: don't use frozen operands for value tracking.
@@ -9777,6 +9782,8 @@ SDValue TargetLowering::expandABD(SDNode *N, SelectionDAG &DAG) const {
EVT CCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT);
ISD::CondCode CC = IsSigned ? ISD::CondCode::SETGT : ISD::CondCode::SETUGT;
+ LHS = DAG.getFreeze(LHS);
+ RHS = DAG.getFreeze(RHS);
SDValue Cmp = DAG.getSetCC(dl, CCVT, LHS, RHS, CC);
// Branchless expansion iff cmp result is allbits:
diff --git a/llvm/test/CodeGen/X86/abdu-neg.ll b/llvm/test/CodeGen/X86/abdu-neg.ll
index b7c34070f1af6..b6483c3acc77c 100644
--- a/llvm/test/CodeGen/X86/abdu-neg.ll
+++ b/llvm/test/CodeGen/X86/abdu-neg.ll
@@ -363,10 +363,10 @@ define i128 @abd_ext_i128(i128 %a, i128 %b) nounwind {
; X86-NEXT: subl $16, %esp
; X86-NEXT: movl 32(%ebp), %esi
; X86-NEXT: movl 36(%ebp), %eax
-; X86-NEXT: movl 24(%ebp), %ecx
+; X86-NEXT: movl 24(%ebp), %edx
; X86-NEXT: movl 28(%ebp), %edi
-; X86-NEXT: xorl %edx, %edx
-; X86-NEXT: subl 40(%ebp), %ecx
+; X86-NEXT: xorl %ecx, %ecx
+; X86-NEXT: subl 40(%ebp), %edx
; X86-NEXT: sbbl 44(%ebp), %edi
; X86-NEXT: sbbl 48(%ebp), %esi
; X86-NEXT: sbbl 52(%ebp), %eax
@@ -375,22 +375,22 @@ define i128 @abd_ext_i128(i128 %a, i128 %b) nounwind {
; X86-NEXT: xorl %ebx, %eax
; X86-NEXT: xorl %ebx, %esi
; X86-NEXT: xorl %ebx, %edi
-; X86-NEXT: xorl %ebx, %ecx
-; X86-NEXT: subl %ebx, %ecx
+; X86-NEXT: xorl %ebx, %edx
+; X86-NEXT: subl %ebx, %edx
; X86-NEXT: sbbl %ebx, %edi
; X86-NEXT: sbbl %ebx, %esi
; X86-NEXT: sbbl %ebx, %eax
-; X86-NEXT: negl %ecx
+; X86-NEXT: negl %edx
; X86-NEXT: movl $0, %ebx
; X86-NEXT: sbbl %edi, %ebx
; X86-NEXT: movl $0, %edi
; X86-NEXT: sbbl %esi, %edi
-; X86-NEXT: sbbl %eax, %edx
+; X86-NEXT: sbbl %eax, %ecx
; X86-NEXT: movl 8(%ebp), %eax
-; X86-NEXT: movl %ecx, (%eax)
+; X86-NEXT: movl %edx, (%eax)
; X86-NEXT: movl %ebx, 4(%eax)
; X86-NEXT: movl %edi, 8(%eax)
-; X86-NEXT: movl %edx, 12(%eax)
+; X86-NEXT: movl %ecx, 12(%eax)
; X86-NEXT: leal -12(%ebp), %esp
; X86-NEXT: popl %esi
; X86-NEXT: popl %edi
@@ -435,10 +435,10 @@ define i128 @abd_ext_i128_undef(i128 %a, i128 %b) nounwind {
; X86-NEXT: subl $16, %esp
; X86-NEXT: movl 32(%ebp), %esi
; X86-NEXT: movl 36(%ebp), %eax
-; X86-NEXT: movl 24(%ebp), %ecx
+; X86-NEXT: movl 24(%ebp), %edx
; X86-NEXT: movl 28(%ebp), %edi
-; X86-NEXT: xorl %edx, %edx
-; X86-NEXT: subl 40(%ebp), %ecx
+; X86-NEXT: xorl %ecx, %ecx
+; X86-NEXT: subl 40(%ebp), %edx
; X86-NEXT: sbbl 44(%ebp), %edi
; X86-NEXT: sbbl 48(%ebp), %esi
; X86-NEXT: sbbl 52(%ebp), %eax
@@ -447,22 +447,22 @@ define i128 @abd_ext_i128_undef(i128 %a, i128 %b) nounwind {
; X86-NEXT: xorl %ebx, %eax
; X86-NEXT: xorl %ebx, %esi
; X86-NEXT: xorl %ebx, %edi
-; X86-NEXT: xorl %ebx, %ecx
-; X86-NEXT: subl %ebx, %ecx
+; X86-NEXT: xorl %ebx, %edx
+; X86-NEXT: subl %ebx, %edx
; X86-NEXT: sbbl %ebx, %edi
; X86-NEXT: sbbl %ebx, %esi
; X86-NEXT: sbbl %ebx, %eax
-; X86-NEXT: negl %ecx
+; X86-NEXT: negl %edx
; X86-NEXT: movl $0, %ebx
; X86-NEXT: sbbl %edi, %ebx
; X86-NEXT: movl $0, %edi
; X86-NEXT: sbbl %esi, %edi
-; X86-NEXT: sbbl %eax, %edx
+; X86-NEXT: sbbl %eax, %ecx
; X86-NEXT: movl 8(%ebp), %eax
-; X86-NEXT: movl %ecx, (%eax)
+; X86-NEXT: movl %edx, (%eax)
; X86-NEXT: movl %ebx, 4(%eax)
; X86-NEXT: movl %edi, 8(%eax)
-; X86-NEXT: movl %edx, 12(%eax)
+; X86-NEXT: movl %ecx, 12(%eax)
; X86-NEXT: leal -12(%ebp), %esp
; X86-NEXT: popl %esi
; X86-NEXT: popl %edi
@@ -847,10 +847,10 @@ define i128 @abd_cmp_i128(i128 %a, i128 %b) nounwind {
; X86-NEXT: subl $16, %esp
; X86-NEXT: movl 32(%ebp), %esi
; X86-NEXT: movl 36(%ebp), %eax
-; X86-NEXT: movl 24(%ebp), %ecx
+; X86-NEXT: movl 24(%ebp), %edx
; X86-NEXT: movl 28(%ebp), %edi
-; X86-NEXT: xorl %edx, %edx
-; X86-NEXT: subl 40(%ebp), %ecx
+; X86-NEXT: xorl %ecx, %ecx
+; X86-NEXT: subl 40(%ebp), %edx
; X86-NEXT: sbbl 44(%ebp), %edi
; X86-NEXT: sbbl 48(%ebp), %esi
; X86-NEXT: sbbl 52(%ebp), %eax
@@ -859,22 +859,22 @@ define i128 @abd_cmp_i128(i128 %a, i128 %b) nounwind {
; X86-NEXT: xorl %ebx, %eax
; X86-NEXT: xorl %ebx, %esi
; X86-NEXT: xorl %ebx, %edi
-; X86-NEXT: xorl %ebx, %ecx
-; X86-NEXT: subl %ebx, %ecx
+; X86-NEXT: xorl %ebx, %edx
+; X86-NEXT: subl %ebx, %edx
; X86-NEXT: sbbl %ebx, %edi
; X86-NEXT: sbbl %ebx, %esi
; X86-NEXT: sbbl %ebx, %eax
-; X86-NEXT: negl %ecx
+; X86-NEXT: negl %edx
; X86-NEXT: movl $0, %ebx
; X86-NEXT: sbbl %edi, %ebx
; X86-NEXT: movl $0, %edi
; X86-NEXT: sbbl %esi, %edi
-; X86-NEXT: sbbl %eax, %edx
+; X86-NEXT: sbbl %eax, %ecx
; X86-NEXT: movl 8(%ebp), %eax
-; X86-NEXT: movl %ecx, (%eax)
+; X86-NEXT: movl %edx, (%eax)
; X86-NEXT: movl %ebx, 4(%eax)
; X86-NEXT: movl %edi, 8(%eax)
-; X86-NEXT: movl %edx, 12(%eax)
+; X86-NEXT: movl %ecx, 12(%eax)
; X86-NEXT: leal -12(%ebp), %esp
; X86-NEXT: popl %esi
; X86-NEXT: popl %edi
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