[llvm] [AArch64][SDAG] Add f16 -> i16 rounding NEON conversion intrinsics (PR #155851)

[Kajetan Puchalski via llvm-commits]

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@@ -22189,6 +22189,17 @@ static SDValue combineSVEReductionOrderedFP(SDNode *N, unsigned Opc,
                      Zero);
 }
 
+static SDValue tryCombineNeonFcvtFP16ToI16(SDNode *N, unsigned Opcode,
+                                           SelectionDAG &DAG) {
+  if (N->getValueType(0).getScalarType() != MVT::i16)
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mrkajetanp wrote:

Oh good point. It seems like we did not test those, so I added some along with the fix. Thanks!

https://github.com/llvm/llvm-project/pull/155851