[llvm] [SelectionDAG] Add computeKnownBits for ISD::ROTL/ROTR. (PR #156142)

[Sergei Barannikov via llvm-commits]

================
@@ -3850,6 +3850,22 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts,
     Known = KnownBits::ashr(Known, Known2, /*ShAmtNonZero=*/false,
                             Op->getFlags().hasExact());
     break;
+  case ISD::ROTL:
+  case ISD::ROTR:
+    if (ConstantSDNode *C =
+            isConstOrConstSplat(Op.getOperand(1), DemandedElts)) {
+      unsigned Amt = C->getAPIntValue().urem(BitWidth);
----------------
s-barannikov wrote:

Should BitWidth be the width of getShiftAmountTy()?

https://github.com/llvm/llvm-project/pull/156142