[llvm] wasm: recognize `any_true` and `all_true` (PR #155885)

[Jasmine Tang via llvm-commits]

badumbatish wrote:

hi @folkertdev, I didn't quite spend much time on the PR but it seems like you're failing at isel stage because it cant find the pattern of  `(i32( reduce_and (v8i16 V128)))`. So if you add these to the tablegen file it shouldn't fail anymore

```td
def : Pat<(i32 (vecreduce_or(v8i16 V128:$vec))), (ANYTRUE V128:$vec)>;
def : Pat<(i32 (vecreduce_or(v16i8 V128:$vec))), (ANYTRUE V128:$vec)>;
def : Pat<(i32 (vecreduce_or(v4i32 V128:$vec))), (ANYTRUE V128:$vec)>;
def : Pat<(i32 (vecreduce_or(v2i64 V128:$vec))), (ANYTRUE V128:$vec)>;

def : Pat<(i32 (vecreduce_and(v8i16 V128:$vec))), (ALLTRUE_I8x16 V128:$vec)>;
def : Pat<(i32 (vecreduce_and(v16i8 V128:$vec))), (ALLTRUE_I16x8 V128:$vec)>;
def : Pat<(i32 (vecreduce_and(v4i32 V128:$vec))), (ALLTRUE_I32x4 V128:$vec)>;
def : Pat<(i32 (vecreduce_and(v2i64 V128:$vec))), (ALLTRUE_I64x2 V128:$vec)>;
```


However you should be careful about these works, idk where in the codebase this happens yet but if you run following command to reproduce, you'll find that t3, t4, t5 is being turned into t8 uncaringly between `optimized lowered` and `type legalized` stage
```
build/bin/llc -verify-machineinstrs -disable-wasm-fallthrough-return-opt -wasm-disable-explicit-locals -wasm-keep-registers -mattr=+simd128 llvm/test/CodeGen/WebAssembly/simd-vecreduce-bool.ll -debug-only=dagcomb
ine,isel -o - &> test.txt
```

```=== test_any_v8i1

Initial selection DAG: %bb.0 'test_any_v8i1:'
SelectionDAG has 7 nodes:
    t0: ch,glue = EntryToken
          t2: v8i16 = WebAssemblyISD::ARGUMENT TargetConstant:i32<0>
        t3: v8i1 = truncate t2
      t4: i1 = vecreduce_or t3
    t5: i32 = any_extend t4
  t6: ch = WebAssemblyISD::RETURN t0, t5



Combining: t6: ch = WebAssemblyISD::RETURN t0, t5

Combining: t5: i32 = any_extend t4

Combining: t4: i1 = vecreduce_or t3

Combining: t3: v8i1 = truncate t2

Combining: t2: v8i16 = WebAssemblyISD::ARGUMENT TargetConstant:i32<0>

Combining: t1: i32 = TargetConstant<0>

Combining: t0: ch,glue = EntryToken

Optimized lowered selection DAG: %bb.0 'test_any_v8i1:'
SelectionDAG has 7 nodes:
    t0: ch,glue = EntryToken
          t2: v8i16 = WebAssemblyISD::ARGUMENT TargetConstant:i32<0>
        t3: v8i1 = truncate t2
      t4: i1 = vecreduce_or t3
    t5: i32 = any_extend t4
  t6: ch = WebAssemblyISD::RETURN t0, t5



Type-legalized selection DAG: %bb.0 'test_any_v8i1:'
SelectionDAG has 5 nodes:
    t0: ch,glue = EntryToken
      t2: v8i16 = WebAssemblyISD::ARGUMENT TargetConstant:i32<0>
    t8: i32 = vecreduce_or t2
  t6: ch = WebAssemblyISD::RETURN t0, t8
```

we haven't proved that the other bits besides LSB bit in t2 is 0 yet before doing so, so if these transform were to go through while some bits other than LSB is 1 and LSB is 0, this will result in the wrong result

https://github.com/llvm/llvm-project/pull/155885