[llvm] [RISCV][NFC] Precommit a test for SLP behavior... (PR #156110)
Mikhail Gudim via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 29 14:36:53 PDT 2025
https://github.com/mgudim created https://github.com/llvm/llvm-project/pull/156110
when the subtarget has unaligned-vector-mem feature.
>From 18d07db485a38a85e404cd0b2260fe7e9a04ad0e Mon Sep 17 00:00:00 2001
From: Mikhail Gudim <mgudim at ventanamicro.com>
Date: Fri, 29 Aug 2025 14:33:43 -0700
Subject: [PATCH] [RISCV][NFC] Precommit a test for SLP behavior...
when the subtarget has unaligned-vector-mem feature.
---
.../SLPVectorizer/RISCV/complex-loads.ll | 135 ++++++++++++++++++
1 file changed, 135 insertions(+)
diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/complex-loads.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/complex-loads.ll
index 5ee9f3ca46ca8..027968296d003 100644
--- a/llvm/test/Transforms/SLPVectorizer/RISCV/complex-loads.ll
+++ b/llvm/test/Transforms/SLPVectorizer/RISCV/complex-loads.ll
@@ -1,6 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 3
; RUN: opt -S -mtriple riscv64-unknown-linux-gnu < %s --passes=slp-vectorizer -mattr=+v | FileCheck %s
; RUN: opt -S -mtriple riscv64-unknown-linux-gnu < %s --passes=slp-vectorizer -mattr=+v -slp-threshold=-15 | FileCheck %s --check-prefix=THR15
+; RUN: opt -S -mtriple riscv64-unknown-linux-gnu < %s --passes=slp-vectorizer -mattr=+v,+unaligned-vector-mem | FileCheck %s --check-prefix=UNALIGNED_VEC_MEM
define i32 @test(ptr %pix1, ptr %pix2, i64 %idx.ext, i64 %idx.ext63, ptr %add.ptr, ptr %add.ptr64) {
; CHECK-LABEL: define i32 @test(
@@ -271,6 +272,140 @@ define i32 @test(ptr %pix1, ptr %pix2, i64 %idx.ext, i64 %idx.ext63, ptr %add.pt
; THR15-NEXT: [[TMP114:%.*]] = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP113]])
; THR15-NEXT: ret i32 [[TMP114]]
;
+; UNALIGNED_VEC_MEM-LABEL: define i32 @test(
+; UNALIGNED_VEC_MEM-SAME: ptr [[PIX1:%.*]], ptr [[PIX2:%.*]], i64 [[IDX_EXT:%.*]], i64 [[IDX_EXT63:%.*]], ptr [[ADD_PTR:%.*]], ptr [[ADD_PTR64:%.*]]) #[[ATTR0:[0-9]+]] {
+; UNALIGNED_VEC_MEM-NEXT: entry:
+; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX3:%.*]] = getelementptr i8, ptr [[PIX1]], i64 4
+; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX5:%.*]] = getelementptr i8, ptr [[PIX2]], i64 4
+; UNALIGNED_VEC_MEM-NEXT: [[ADD_PTR3:%.*]] = getelementptr i8, ptr [[PIX1]], i64 [[IDX_EXT]]
+; UNALIGNED_VEC_MEM-NEXT: [[ADD_PTR644:%.*]] = getelementptr i8, ptr [[PIX2]], i64 [[IDX_EXT63]]
+; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX3_1:%.*]] = getelementptr i8, ptr [[ADD_PTR3]], i64 4
+; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX5_1:%.*]] = getelementptr i8, ptr [[ADD_PTR644]], i64 4
+; UNALIGNED_VEC_MEM-NEXT: [[ADD_PTR_1:%.*]] = getelementptr i8, ptr [[ADD_PTR]], i64 [[IDX_EXT]]
+; UNALIGNED_VEC_MEM-NEXT: [[ADD_PTR64_1:%.*]] = getelementptr i8, ptr [[ADD_PTR64]], i64 [[IDX_EXT63]]
+; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX3_2:%.*]] = getelementptr i8, ptr [[ADD_PTR_1]], i64 4
+; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX5_2:%.*]] = getelementptr i8, ptr [[ADD_PTR64_1]], i64 4
+; UNALIGNED_VEC_MEM-NEXT: [[ARRAYIDX5_3:%.*]] = getelementptr i8, ptr null, i64 4
+; UNALIGNED_VEC_MEM-NEXT: [[TMP0:%.*]] = load i8, ptr null, align 1
+; UNALIGNED_VEC_MEM-NEXT: [[TMP1:%.*]] = load i8, ptr null, align 1
+; UNALIGNED_VEC_MEM-NEXT: [[TMP2:%.*]] = load <4 x i8>, ptr [[PIX1]], align 1
+; UNALIGNED_VEC_MEM-NEXT: [[TMP3:%.*]] = zext <4 x i8> [[TMP2]] to <4 x i32>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP4:%.*]] = load <4 x i8>, ptr [[PIX2]], align 1
+; UNALIGNED_VEC_MEM-NEXT: [[TMP5:%.*]] = zext <4 x i8> [[TMP4]] to <4 x i32>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP6:%.*]] = sub <4 x i32> [[TMP3]], [[TMP5]]
+; UNALIGNED_VEC_MEM-NEXT: [[TMP7:%.*]] = load <4 x i8>, ptr [[ARRAYIDX3]], align 1
+; UNALIGNED_VEC_MEM-NEXT: [[TMP8:%.*]] = zext <4 x i8> [[TMP7]] to <4 x i32>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP9:%.*]] = load <4 x i8>, ptr [[ARRAYIDX5]], align 1
+; UNALIGNED_VEC_MEM-NEXT: [[TMP10:%.*]] = zext <4 x i8> [[TMP9]] to <4 x i32>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP11:%.*]] = sub <4 x i32> [[TMP8]], [[TMP10]]
+; UNALIGNED_VEC_MEM-NEXT: [[TMP12:%.*]] = shl <4 x i32> [[TMP11]], splat (i32 16)
+; UNALIGNED_VEC_MEM-NEXT: [[TMP13:%.*]] = add <4 x i32> [[TMP12]], [[TMP6]]
+; UNALIGNED_VEC_MEM-NEXT: [[TMP14:%.*]] = shufflevector <4 x i32> [[TMP13]], <4 x i32> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP15:%.*]] = add <4 x i32> [[TMP14]], [[TMP13]]
+; UNALIGNED_VEC_MEM-NEXT: [[TMP16:%.*]] = sub <4 x i32> [[TMP14]], [[TMP13]]
+; UNALIGNED_VEC_MEM-NEXT: [[TMP17:%.*]] = shufflevector <4 x i32> [[TMP15]], <4 x i32> [[TMP16]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP18:%.*]] = shufflevector <4 x i32> [[TMP17]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 0, i32 1>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP19:%.*]] = add <4 x i32> [[TMP17]], [[TMP18]]
+; UNALIGNED_VEC_MEM-NEXT: [[TMP20:%.*]] = sub <4 x i32> [[TMP17]], [[TMP18]]
+; UNALIGNED_VEC_MEM-NEXT: [[TMP21:%.*]] = shufflevector <4 x i32> [[TMP19]], <4 x i32> [[TMP20]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP22:%.*]] = load <4 x i8>, ptr [[ADD_PTR3]], align 1
+; UNALIGNED_VEC_MEM-NEXT: [[TMP23:%.*]] = zext <4 x i8> [[TMP22]] to <4 x i32>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP24:%.*]] = load <4 x i8>, ptr [[ADD_PTR644]], align 1
+; UNALIGNED_VEC_MEM-NEXT: [[TMP25:%.*]] = zext <4 x i8> [[TMP24]] to <4 x i32>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP26:%.*]] = sub <4 x i32> [[TMP23]], [[TMP25]]
+; UNALIGNED_VEC_MEM-NEXT: [[TMP27:%.*]] = load <4 x i8>, ptr [[ARRAYIDX3_1]], align 1
+; UNALIGNED_VEC_MEM-NEXT: [[TMP28:%.*]] = zext <4 x i8> [[TMP27]] to <4 x i32>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP29:%.*]] = load <4 x i8>, ptr [[ARRAYIDX5_1]], align 1
+; UNALIGNED_VEC_MEM-NEXT: [[TMP30:%.*]] = zext <4 x i8> [[TMP29]] to <4 x i32>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP31:%.*]] = sub <4 x i32> [[TMP28]], [[TMP30]]
+; UNALIGNED_VEC_MEM-NEXT: [[TMP32:%.*]] = shl <4 x i32> [[TMP31]], splat (i32 16)
+; UNALIGNED_VEC_MEM-NEXT: [[TMP33:%.*]] = add <4 x i32> [[TMP32]], [[TMP26]]
+; UNALIGNED_VEC_MEM-NEXT: [[TMP34:%.*]] = shufflevector <4 x i32> [[TMP33]], <4 x i32> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP35:%.*]] = add <4 x i32> [[TMP34]], [[TMP33]]
+; UNALIGNED_VEC_MEM-NEXT: [[TMP36:%.*]] = sub <4 x i32> [[TMP34]], [[TMP33]]
+; UNALIGNED_VEC_MEM-NEXT: [[TMP37:%.*]] = shufflevector <4 x i32> [[TMP35]], <4 x i32> [[TMP36]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP38:%.*]] = shufflevector <4 x i32> [[TMP37]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 0, i32 1>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP39:%.*]] = add <4 x i32> [[TMP37]], [[TMP38]]
+; UNALIGNED_VEC_MEM-NEXT: [[TMP40:%.*]] = sub <4 x i32> [[TMP37]], [[TMP38]]
+; UNALIGNED_VEC_MEM-NEXT: [[TMP41:%.*]] = shufflevector <4 x i32> [[TMP39]], <4 x i32> [[TMP40]], <4 x i32> <i32 4, i32 5, i32 2, i32 3>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP42:%.*]] = load <4 x i8>, ptr [[ADD_PTR_1]], align 1
+; UNALIGNED_VEC_MEM-NEXT: [[TMP43:%.*]] = zext <4 x i8> [[TMP42]] to <4 x i32>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP44:%.*]] = load <4 x i8>, ptr [[ADD_PTR64_1]], align 1
+; UNALIGNED_VEC_MEM-NEXT: [[TMP45:%.*]] = zext <4 x i8> [[TMP44]] to <4 x i32>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP46:%.*]] = sub <4 x i32> [[TMP43]], [[TMP45]]
+; UNALIGNED_VEC_MEM-NEXT: [[TMP47:%.*]] = load <4 x i8>, ptr [[ARRAYIDX3_2]], align 1
+; UNALIGNED_VEC_MEM-NEXT: [[TMP48:%.*]] = zext <4 x i8> [[TMP47]] to <4 x i32>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP49:%.*]] = load <4 x i8>, ptr [[ARRAYIDX5_2]], align 1
+; UNALIGNED_VEC_MEM-NEXT: [[TMP50:%.*]] = zext <4 x i8> [[TMP49]] to <4 x i32>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP51:%.*]] = sub <4 x i32> [[TMP48]], [[TMP50]]
+; UNALIGNED_VEC_MEM-NEXT: [[TMP52:%.*]] = shl <4 x i32> [[TMP51]], splat (i32 16)
+; UNALIGNED_VEC_MEM-NEXT: [[TMP53:%.*]] = add <4 x i32> [[TMP52]], [[TMP46]]
+; UNALIGNED_VEC_MEM-NEXT: [[TMP54:%.*]] = shufflevector <4 x i32> [[TMP53]], <4 x i32> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP55:%.*]] = add <4 x i32> [[TMP54]], [[TMP53]]
+; UNALIGNED_VEC_MEM-NEXT: [[TMP56:%.*]] = sub <4 x i32> [[TMP54]], [[TMP53]]
+; UNALIGNED_VEC_MEM-NEXT: [[TMP57:%.*]] = shufflevector <4 x i32> [[TMP55]], <4 x i32> [[TMP56]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP58:%.*]] = shufflevector <4 x i32> [[TMP57]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 0, i32 1>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP59:%.*]] = add <4 x i32> [[TMP57]], [[TMP58]]
+; UNALIGNED_VEC_MEM-NEXT: [[TMP60:%.*]] = sub <4 x i32> [[TMP57]], [[TMP58]]
+; UNALIGNED_VEC_MEM-NEXT: [[TMP61:%.*]] = shufflevector <4 x i32> [[TMP59]], <4 x i32> [[TMP60]], <4 x i32> <i32 2, i32 3, i32 4, i32 5>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP62:%.*]] = call <2 x i8> @llvm.experimental.vp.strided.load.v2i8.p0.i64(ptr align 1 null, i64 4, <2 x i1> splat (i1 true), i32 2)
+; UNALIGNED_VEC_MEM-NEXT: [[TMP63:%.*]] = load <4 x i8>, ptr null, align 1
+; UNALIGNED_VEC_MEM-NEXT: [[TMP64:%.*]] = zext <4 x i8> [[TMP63]] to <4 x i32>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP65:%.*]] = load <4 x i8>, ptr null, align 1
+; UNALIGNED_VEC_MEM-NEXT: [[TMP66:%.*]] = zext <4 x i8> [[TMP65]] to <4 x i32>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP67:%.*]] = sub <4 x i32> [[TMP64]], [[TMP66]]
+; UNALIGNED_VEC_MEM-NEXT: [[TMP68:%.*]] = shufflevector <4 x i32> [[TMP67]], <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP69:%.*]] = insertelement <4 x i8> poison, i8 [[TMP1]], i32 0
+; UNALIGNED_VEC_MEM-NEXT: [[TMP70:%.*]] = insertelement <4 x i8> [[TMP69]], i8 [[TMP0]], i32 1
+; UNALIGNED_VEC_MEM-NEXT: [[TMP71:%.*]] = shufflevector <2 x i8> [[TMP62]], <2 x i8> poison, <4 x i32> <i32 0, i32 1, i32 poison, i32 poison>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP72:%.*]] = shufflevector <4 x i8> [[TMP70]], <4 x i8> [[TMP71]], <4 x i32> <i32 0, i32 1, i32 4, i32 5>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP73:%.*]] = zext <4 x i8> [[TMP72]] to <4 x i32>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP74:%.*]] = load <4 x i8>, ptr [[ARRAYIDX5_3]], align 1
+; UNALIGNED_VEC_MEM-NEXT: [[TMP75:%.*]] = zext <4 x i8> [[TMP74]] to <4 x i32>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP76:%.*]] = shufflevector <4 x i32> [[TMP75]], <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP77:%.*]] = sub <4 x i32> [[TMP73]], [[TMP76]]
+; UNALIGNED_VEC_MEM-NEXT: [[TMP78:%.*]] = shl <4 x i32> [[TMP77]], splat (i32 16)
+; UNALIGNED_VEC_MEM-NEXT: [[TMP79:%.*]] = add <4 x i32> [[TMP78]], [[TMP68]]
+; UNALIGNED_VEC_MEM-NEXT: [[TMP80:%.*]] = shufflevector <4 x i32> [[TMP79]], <4 x i32> poison, <4 x i32> <i32 1, i32 0, i32 3, i32 2>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP81:%.*]] = add <4 x i32> [[TMP79]], [[TMP80]]
+; UNALIGNED_VEC_MEM-NEXT: [[TMP82:%.*]] = sub <4 x i32> [[TMP79]], [[TMP80]]
+; UNALIGNED_VEC_MEM-NEXT: [[TMP83:%.*]] = shufflevector <4 x i32> [[TMP81]], <4 x i32> [[TMP82]], <4 x i32> <i32 0, i32 5, i32 2, i32 7>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP84:%.*]] = shufflevector <4 x i32> [[TMP83]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 0, i32 1>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP85:%.*]] = add <4 x i32> [[TMP83]], [[TMP84]]
+; UNALIGNED_VEC_MEM-NEXT: [[TMP86:%.*]] = sub <4 x i32> [[TMP83]], [[TMP84]]
+; UNALIGNED_VEC_MEM-NEXT: [[TMP87:%.*]] = shufflevector <4 x i32> [[TMP85]], <4 x i32> [[TMP86]], <4 x i32> <i32 0, i32 1, i32 6, i32 7>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP88:%.*]] = shufflevector <4 x i32> [[TMP41]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 0, i32 1>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP89:%.*]] = shufflevector <4 x i32> [[TMP21]], <4 x i32> poison, <4 x i32> <i32 2, i32 3, i32 0, i32 1>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP90:%.*]] = add <4 x i32> [[TMP88]], [[TMP89]]
+; UNALIGNED_VEC_MEM-NEXT: [[TMP91:%.*]] = sub <4 x i32> [[TMP21]], [[TMP41]]
+; UNALIGNED_VEC_MEM-NEXT: [[TMP92:%.*]] = shufflevector <4 x i32> [[TMP91]], <4 x i32> [[TMP90]], <8 x i32> <i32 2, i32 3, i32 0, i32 1, i32 4, i32 5, i32 6, i32 7>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP93:%.*]] = add <4 x i32> [[TMP87]], [[TMP61]]
+; UNALIGNED_VEC_MEM-NEXT: [[TMP94:%.*]] = sub <4 x i32> [[TMP61]], [[TMP87]]
+; UNALIGNED_VEC_MEM-NEXT: [[TMP95:%.*]] = shufflevector <4 x i32> [[TMP94]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP96:%.*]] = shufflevector <4 x i32> [[TMP93]], <4 x i32> poison, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP97:%.*]] = shufflevector <8 x i32> [[TMP95]], <8 x i32> [[TMP96]], <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 8, i32 9, i32 10, i32 11>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP98:%.*]] = add <8 x i32> [[TMP97]], [[TMP92]]
+; UNALIGNED_VEC_MEM-NEXT: [[TMP99:%.*]] = sub <8 x i32> [[TMP92]], [[TMP97]]
+; UNALIGNED_VEC_MEM-NEXT: [[TMP100:%.*]] = shufflevector <8 x i32> [[TMP98]], <8 x i32> [[TMP99]], <16 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7, i32 12, i32 8, i32 13, i32 9, i32 14, i32 10, i32 15, i32 11>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP101:%.*]] = shufflevector <4 x i32> [[TMP57]], <4 x i32> [[TMP64]], <16 x i32> <i32 2, i32 4, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP102:%.*]] = shufflevector <4 x i32> [[TMP43]], <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP103:%.*]] = shufflevector <16 x i32> [[TMP101]], <16 x i32> [[TMP102]], <16 x i32> <i32 0, i32 1, i32 16, i32 17, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP104:%.*]] = shufflevector <4 x i32> [[TMP23]], <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP105:%.*]] = shufflevector <16 x i32> [[TMP103]], <16 x i32> [[TMP104]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 16, i32 17, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 18, i32 poison, i32 poison, i32 poison>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP106:%.*]] = shufflevector <4 x i32> [[TMP3]], <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP107:%.*]] = shufflevector <16 x i32> [[TMP105]], <16 x i32> [[TMP106]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 16, i32 17, i32 poison, i32 poison, i32 poison, i32 poison, i32 12, i32 poison, i32 18, i32 19>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP108:%.*]] = shufflevector <4 x i32> [[TMP37]], <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP109:%.*]] = shufflevector <16 x i32> [[TMP107]], <16 x i32> [[TMP108]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 18, i32 poison, i32 19, i32 poison, i32 12, i32 poison, i32 14, i32 15>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP110:%.*]] = shufflevector <4 x i32> [[TMP17]], <4 x i32> poison, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison, i32 poison>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP111:%.*]] = shufflevector <16 x i32> [[TMP109]], <16 x i32> [[TMP110]], <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 18, i32 10, i32 19, i32 12, i32 16, i32 14, i32 15>
+; UNALIGNED_VEC_MEM-NEXT: [[TMP112:%.*]] = lshr <16 x i32> [[TMP111]], splat (i32 15)
+; UNALIGNED_VEC_MEM-NEXT: [[TMP113:%.*]] = and <16 x i32> [[TMP112]], splat (i32 65537)
+; UNALIGNED_VEC_MEM-NEXT: [[TMP114:%.*]] = mul <16 x i32> [[TMP113]], splat (i32 65535)
+; UNALIGNED_VEC_MEM-NEXT: [[TMP115:%.*]] = add <16 x i32> [[TMP114]], [[TMP100]]
+; UNALIGNED_VEC_MEM-NEXT: [[TMP116:%.*]] = xor <16 x i32> [[TMP115]], [[TMP111]]
+; UNALIGNED_VEC_MEM-NEXT: [[TMP117:%.*]] = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP116]])
+; UNALIGNED_VEC_MEM-NEXT: ret i32 [[TMP117]]
+;
entry:
%0 = load i8, ptr %pix1, align 1
%conv = zext i8 %0 to i32
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