[llvm] [RISCV] Eagerly optimize scalar packing for buildvector lowering (PR #156062)

[Craig Topper via llvm-commits]

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@@ -4270,8 +4271,12 @@ static SDValue lowerBuildVectorViaPacking(SDValue Op, SelectionDAG &DAG,
                              ElemDL, XLenVT, A, B),
           0);
 
-    A = DAG.getNode(ISD::AND, SDLoc(A), XLenVT, A, Mask);
-    B = DAG.getNode(ISD::AND, SDLoc(B), XLenVT, B, Mask);
+    // Manually optimize away the ANDs if we can, DAGCombiner will
+    // sometimes end of perturbing codegen if we don't.
+    if (DAG.computeKnownBits(A).countMinLeadingZeros() < ZeroPrefix)
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topperc wrote:

Could do `DAG.computeKnownBits(A).countMaxActiveBits() > ElemSizeInBits`.

I was also thought about using MaskedValueIsZero, but you'd have to invert the Mask.

https://github.com/llvm/llvm-project/pull/156062