[llvm] [TableGen][CodeGen] Remove DisableEncoding field of Instruction class (PR #156098)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Aug 29 13:23:01 PDT 2025
llvmbot wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-systemz
Author: Sergei Barannikov (s-barannikov)
<details>
<summary>Changes</summary>
I believe it became no-op with the removal of the "positionally encoded operands" functionality (b87dc356 is the last commit in the series).
There are no changes in the generated files.
---
Patch is 141.44 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/156098.diff
31 Files Affected:
- (modified) llvm/docs/CodeGenerator.rst (+1-1)
- (modified) llvm/include/llvm/Target/Target.td (-4)
- (modified) llvm/lib/Target/AMDGPU/BUFInstructions.td (-4)
- (modified) llvm/lib/Target/AMDGPU/DSInstructions.td (-3)
- (modified) llvm/lib/Target/AMDGPU/EvergreenInstructions.td (+1-2)
- (modified) llvm/lib/Target/AMDGPU/FLATInstructions.td (-3)
- (modified) llvm/lib/Target/AMDGPU/R600Instructions.td (+3-6)
- (modified) llvm/lib/Target/AMDGPU/SIInstructions.td (+2-2)
- (modified) llvm/lib/Target/AMDGPU/SMInstructions.td (-3)
- (modified) llvm/lib/Target/AMDGPU/SOPInstructions.td (+3-6)
- (modified) llvm/lib/Target/AMDGPU/VOP1Instructions.td (-6)
- (modified) llvm/lib/Target/AMDGPU/VOP2Instructions.td (+5-12)
- (modified) llvm/lib/Target/AMDGPU/VOP3Instructions.td (+12-12)
- (modified) llvm/lib/Target/AMDGPU/VOP3PInstructions.td (+1-3)
- (modified) llvm/lib/Target/AMDGPU/VOPCInstructions.td (-2)
- (modified) llvm/lib/Target/AMDGPU/VOPDInstructions.td (-4)
- (modified) llvm/lib/Target/AMDGPU/VOPInstructions.td (-10)
- (modified) llvm/lib/Target/PowerPC/PPCInstr64Bit.td (+17-33)
- (modified) llvm/lib/Target/PowerPC/PPCInstrAltivec.td (+4-4)
- (modified) llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td (+23-23)
- (modified) llvm/lib/Target/PowerPC/PPCInstrInfo.td (+18-37)
- (modified) llvm/lib/Target/PowerPC/PPCInstrMMA.td (+54-54)
- (modified) llvm/lib/Target/PowerPC/PPCInstrP10.td (+8-8)
- (modified) llvm/lib/Target/PowerPC/PPCInstrVSX.td (+36-36)
- (modified) llvm/lib/Target/PowerPC/README_P9.txt (+9-9)
- (modified) llvm/lib/Target/SystemZ/SystemZInstrFormats.td (+1-59)
- (modified) llvm/lib/Target/VE/VEInstrInfo.td (+6-6)
- (modified) llvm/lib/Target/VE/VEInstrVec.td (+33-55)
- (modified) llvm/utils/TableGen/CodeEmitterGen.cpp (-6)
- (modified) llvm/utils/TableGen/Common/CodeGenInstruction.cpp (-20)
- (modified) llvm/utils/TableGen/Common/CodeGenInstruction.h (+1-17)
``````````diff
diff --git a/llvm/docs/CodeGenerator.rst b/llvm/docs/CodeGenerator.rst
index 8260b5c173422..eda8bf6489bda 100644
--- a/llvm/docs/CodeGenerator.rst
+++ b/llvm/docs/CodeGenerator.rst
@@ -1129,7 +1129,7 @@ for your target. It has the following strengths:
def STWU : DForm_1<37, (outs ptr_rc:$ea_res), (ins GPRC:$rS, memri:$dst),
"stwu $rS, $dst", LdStStoreUpd, []>,
- RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">;
+ RegConstraint<"$dst.reg = $ea_res">;
def : Pat<(pre_store GPRC:$rS, ptr_rc:$ptrreg, iaddroff:$ptroff),
(STWU GPRC:$rS, iaddroff:$ptroff, ptr_rc:$ptrreg)>;
diff --git a/llvm/include/llvm/Target/Target.td b/llvm/include/llvm/Target/Target.td
index 495b59ee916cf..38c3b6064d267 100644
--- a/llvm/include/llvm/Target/Target.td
+++ b/llvm/include/llvm/Target/Target.td
@@ -735,10 +735,6 @@ class Instruction : InstructionEncoding {
/// discussion of inline assembly constraint strings.
string Constraints = "";
- /// DisableEncoding - List of operand names (e.g. "$op1,$op2") that should not
- /// be encoded into the output machineinstr.
- string DisableEncoding = "";
-
string PostEncoderMethod = "";
/// Target-specific flags. This becomes the TSFlags field in TargetInstrDesc.
diff --git a/llvm/lib/Target/AMDGPU/BUFInstructions.td b/llvm/lib/Target/AMDGPU/BUFInstructions.td
index 1956a15c57d67..1fa8730032124 100644
--- a/llvm/lib/Target/AMDGPU/BUFInstructions.td
+++ b/llvm/lib/Target/AMDGPU/BUFInstructions.td
@@ -132,7 +132,6 @@ class MTBUF_Real <MTBUF_Pseudo ps, string real_name = ps.Mnemonic> :
let OtherPredicates = ps.OtherPredicates;
let AsmMatchConverter = ps.AsmMatchConverter;
let Constraints = ps.Constraints;
- let DisableEncoding = ps.DisableEncoding;
let TSFlags = ps.TSFlags;
let SchedRW = ps.SchedRW;
let mayLoad = ps.mayLoad;
@@ -346,7 +345,6 @@ class MUBUF_Real <MUBUF_Pseudo ps, string real_name = ps.Mnemonic> :
let AsmMatchConverter = ps.AsmMatchConverter;
let OtherPredicates = ps.OtherPredicates;
let Constraints = ps.Constraints;
- let DisableEncoding = ps.DisableEncoding;
let TSFlags = ps.TSFlags;
let UseNamedOperandTable = ps.UseNamedOperandTable;
let SchedRW = ps.SchedRW;
@@ -769,7 +767,6 @@ class MUBUF_AtomicRet_Pseudo<string opName, int addrKind,
let sccb_value = 0;
let IsAtomicRet = 1;
let Constraints = "$vdata = $vdata_in";
- let DisableEncoding = "$vdata_in";
}
multiclass MUBUF_Pseudo_Atomics_NO_RTN <string opName,
@@ -2414,7 +2411,6 @@ class VBUFFER_Real <bits<8> op, BUF_Pseudo ps, string real_name> :
let AsmMatchConverter = ps.AsmMatchConverter;
let OtherPredicates = ps.OtherPredicates;
let Constraints = ps.Constraints;
- let DisableEncoding = ps.DisableEncoding;
let TSFlags = ps.TSFlags;
let UseNamedOperandTable = ps.UseNamedOperandTable;
let SchedRW = ps.SchedRW;
diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td b/llvm/lib/Target/AMDGPU/DSInstructions.td
index 3ff675d6e5e97..3703133126b0f 100644
--- a/llvm/lib/Target/AMDGPU/DSInstructions.td
+++ b/llvm/lib/Target/AMDGPU/DSInstructions.td
@@ -76,7 +76,6 @@ class DS_Real <DS_Pseudo ps, string opName = ps.Mnemonic> :
let isConvergent = ps.isConvergent;
let Constraints = ps.Constraints;
- let DisableEncoding = ps.DisableEncoding;
// encoding fields
bits<10> vdst;
@@ -276,7 +275,6 @@ class DS_BVH_STACK<string opName,
data1_rc:$data1, Offset:$offset),
" $vdst, $addr, $data0, $data1$offset"> {
let Constraints = "$addr = $addr_in";
- let DisableEncoding = "$addr_in";
let has_gds = 0;
let gdsValue = 0;
// TODO: Use MMOs in the LDS address space instead of hasSideEffects = 1.
@@ -293,7 +291,6 @@ class DS_1A_RET<string opName, RegisterClass rc = VGPR_32, bit HasTiedOutput = 0
(ins VGPR_32:$addr, ofs:$offset, gds:$gds)),
" $vdst, $addr$offset$gds"> {
let Constraints = !if(HasTiedOutput, "$vdst = $vdst_in", "");
- let DisableEncoding = !if(HasTiedOutput, "$vdst_in", "");
let has_data0 = 0;
let has_data1 = 0;
}
diff --git a/llvm/lib/Target/AMDGPU/EvergreenInstructions.td b/llvm/lib/Target/AMDGPU/EvergreenInstructions.td
index 280def5440c81..622045832552e 100644
--- a/llvm/lib/Target/AMDGPU/EvergreenInstructions.td
+++ b/llvm/lib/Target/AMDGPU/EvergreenInstructions.td
@@ -626,7 +626,6 @@ class R600_LDS_1A <bits<6> lds_op, string name, list<dag> pattern> : R600_LDS <
let usesCustomInserter = 1;
let LDS_1A = 1;
- let DisableEncoding = "$dst";
}
class R600_LDS_1A1D <bits<6> lds_op, dag outs, string name, list<dag> pattern,
@@ -646,6 +645,7 @@ class R600_LDS_1A1D <bits<6> lds_op, dag outs, string name, list<dag> pattern,
let src2 = 0;
let src2_rel = 0;
let LDS_1A1D = 1;
+ string DisableEncoding = "";
}
class R600_LDS_1A1D_NORET <bits<6> lds_op, string name, list<dag> pattern> :
@@ -688,7 +688,6 @@ class R600_LDS_1A2D_RET <bits<6> lds_op, string name, list<dag> pattern> :
let BaseOp = name;
let usesCustomInserter = 1;
- let DisableEncoding = "$dst";
}
def LDS_ADD : R600_LDS_1A1D_NORET <0x0, "LDS_ADD", [] >;
diff --git a/llvm/lib/Target/AMDGPU/FLATInstructions.td b/llvm/lib/Target/AMDGPU/FLATInstructions.td
index f5d438436b299..80f0d504ea30c 100644
--- a/llvm/lib/Target/AMDGPU/FLATInstructions.td
+++ b/llvm/lib/Target/AMDGPU/FLATInstructions.td
@@ -239,7 +239,6 @@ class FLAT_Load_Pseudo<
let enabled_saddr = EnableSaddr;
let Constraints = !if(HasTiedOutput, "$vdst = $vdst_in", "");
- let DisableEncoding = !if(HasTiedOutput, "$vdst_in", "");
}
multiclass FLAT_Flat_Load_Pseudo<string opName, RegisterClass regClass, bit HasTiedInput = 0> {
@@ -335,7 +334,6 @@ class FLAT_Global_Load_AddTid_Pseudo <string opName, RegisterClass regClass,
let enabled_saddr = EnableSaddr;
let Constraints = !if(HasTiedOutput, "$vdst = $vdst_in", "");
- let DisableEncoding = !if(HasTiedOutput, "$vdst_in", "");
}
multiclass FLAT_Global_Load_AddTid_Pseudo<string opName, RegisterClass regClass,
@@ -568,7 +566,6 @@ class FLAT_Scratch_Load_Pseudo <string opName, RegisterClass regClass,
let sve = EnableVaddr;
let Constraints = !if(HasTiedOutput, "$vdst = $vdst_in", "");
- let DisableEncoding = !if(HasTiedOutput, "$vdst_in", "");
}
class FLAT_Scratch_Store_Pseudo <string opName, RegisterClass vdataClass, bit EnableSaddr = 0,
diff --git a/llvm/lib/Target/AMDGPU/R600Instructions.td b/llvm/lib/Target/AMDGPU/R600Instructions.td
index f82bd55beccc0..dda0cf6a32182 100644
--- a/llvm/lib/Target/AMDGPU/R600Instructions.td
+++ b/llvm/lib/Target/AMDGPU/R600Instructions.td
@@ -123,7 +123,6 @@ class R600_1OP <bits<11> inst, string opName, list<dag> pattern,
let HasNativeOperands = 1;
let Op1 = 1;
let ALUInst = 1;
- let DisableEncoding = "$literal";
let UseNamedOperandTable = 1;
let Inst{31-0} = Word0;
@@ -161,7 +160,6 @@ class R600_2OP <bits<11> inst, string opName, list<dag> pattern,
let HasNativeOperands = 1;
let Op2 = 1;
let ALUInst = 1;
- let DisableEncoding = "$literal";
let UseNamedOperandTable = 1;
let Inst{31-0} = Word0;
@@ -201,7 +199,6 @@ class R600_3OP <bits<5> inst, string opName, list<dag> pattern,
R600ALU_Word1_OP3<inst>{
let HasNativeOperands = 1;
- let DisableEncoding = "$literal";
let Op3 = 1;
let UseNamedOperandTable = 1;
let ALUInst = 1;
@@ -1783,7 +1780,7 @@ def : DwordAddrPat <i32, R600_Reg32>;
def getLDSNoRetOp : InstrMapping {
let FilterClass = "R600_LDS_1A1D";
let RowFields = ["BaseOp"];
- let ColFields = ["DisableEncoding"];
- let KeyCol = ["$dst"];
- let ValueCols = [[""""]];
+ let ColFields = ["usesCustomInserter"];
+ let KeyCol = ["1"];
+ let ValueCols = [["0"]];
}
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index e8b4501226732..fc46db9317ce6 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -66,7 +66,7 @@ defm V_INTERP_P1_F32_16bank : V_INTERP_P1_F32_m;
// Constraints = "@earlyclobber $vdst", isAsmParserOnly=1
let OtherPredicates = [isNotGFX90APlus] in {
-let DisableEncoding = "$src0", Constraints = "$src0 = $vdst" in {
+let Constraints = "$src0 = $vdst" in {
defm V_INTERP_P2_F32 : VINTRP_m <
0x00000001,
@@ -77,7 +77,7 @@ defm V_INTERP_P2_F32 : VINTRP_m <
[(set f32:$vdst, (int_amdgcn_interp_p2 f32:$src0, f32:$vsrc,
(i32 timm:$attrchan), (i32 timm:$attr), M0))]>;
-} // End DisableEncoding = "$src0", Constraints = "$src0 = $vdst"
+} // End Constraints = "$src0 = $vdst"
defm V_INTERP_MOV_F32 : VINTRP_m <
0x00000002,
diff --git a/llvm/lib/Target/AMDGPU/SMInstructions.td b/llvm/lib/Target/AMDGPU/SMInstructions.td
index 4bda51d1e9597..781c61b073db7 100644
--- a/llvm/lib/Target/AMDGPU/SMInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SMInstructions.td
@@ -295,7 +295,6 @@ class SM_Pseudo_Atomic<string opName,
let has_soffset = offsets.HasSOffset;
let Constraints = !if(isRet, "$sdst = $sdata", "");
- let DisableEncoding = !if(isRet, "$sdata", "");
}
multiclass SM_Pseudo_Atomics<RegisterClass baseClass,
@@ -678,7 +677,6 @@ class SMEM_Atomic_Real_vi <bits<8> op, SM_Atomic_Pseudo ps>
bits<7> sdata;
let Constraints = ps.Constraints;
- let DisableEncoding = ps.DisableEncoding;
let cpol{CPolBit.GLC} = ps.glc;
let Inst{12-6} = !if(ps.glc, sdst{6-0}, sdata{6-0});
@@ -1295,7 +1293,6 @@ class SMEM_Atomic_Real_gfx10 <bits<8> op, SM_Atomic_Pseudo ps>
bits<7> sdata;
let Constraints = ps.Constraints;
- let DisableEncoding = ps.DisableEncoding;
let cpol{CPolBit.GLC} = ps.glc;
diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td
index a003a46191a87..3097409eff12d 100644
--- a/llvm/lib/Target/AMDGPU/SOPInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td
@@ -583,7 +583,6 @@ class SOP2_Real<SOP_Pseudo ps, string name = ps.Mnemonic> :
let mayLoad = ps.mayLoad;
let mayStore = ps.mayStore;
let Constraints = ps.Constraints;
- let DisableEncoding = ps.DisableEncoding;
let Uses = ps.Uses;
let Defs = ps.Defs;
let isConvergent = ps.isConvergent;
@@ -934,7 +933,7 @@ let SubtargetPredicate = HasSALUFloatInsts, mayRaiseFPException = 1,
>;
} // End isReMaterializable = 1
- let Constraints = "$sdst = $src2", DisableEncoding="$src2",
+ let Constraints = "$sdst = $src2",
isCommutable = 1, AddedComplexity = 20 in {
def S_FMAC_F32 : SOP2_Pseudo<
"s_fmac_f32", (outs SReg_32:$sdst),
@@ -949,7 +948,7 @@ let SubtargetPredicate = HasSALUFloatInsts, mayRaiseFPException = 1,
"$sdst, $src0, $src1",
[(set f16:$sdst, (UniformTernaryFrag<any_fma> SSrc_f16:$src0, SSrc_f16:$src1, SReg_32:$src2))]
>;
- } // End Constraints = "$sdst = $src2", DisableEncoding="$src2",
+ } // End Constraints = "$sdst = $src2",
// isCommutable = 1, AddedComplexity = 20
} // End SubtargetPredicate = HasSALUFloatInsts, mayRaiseFPException = 1,
// Uses = [MODE], SchedRW = [WriteSFPU]
@@ -994,7 +993,6 @@ class SOPK_Real<SOPK_Pseudo ps, string name = ps.Mnemonic> :
// copy relevant pseudo op flags
let SubtargetPredicate = ps.SubtargetPredicate;
let AsmMatchConverter = ps.AsmMatchConverter;
- let DisableEncoding = ps.DisableEncoding;
let Constraints = ps.Constraints;
let SchedRW = ps.SchedRW;
let mayLoad = ps.mayLoad;
@@ -1116,8 +1114,7 @@ def S_CMPK_LT_U32 : SOPK_SCC <"s_cmpk_lt_u32", "s_cmp_lt_u32", 0>;
def S_CMPK_LE_U32 : SOPK_SCC <"s_cmpk_le_u32", "s_cmp_le_u32", 0>;
} // End isCompare = 1
-let isCommutable = 1, DisableEncoding = "$src0",
- Constraints = "$sdst = $src0" in {
+let isCommutable = 1, Constraints = "$sdst = $src0" in {
let Defs = [SCC] in
def S_ADDK_I32 : SOPK_32TIE <"s_addk_i32">;
def S_MULK_I32 : SOPK_32TIE <"s_mulk_i32">;
diff --git a/llvm/lib/Target/AMDGPU/VOP1Instructions.td b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
index 11c72751dde58..f816d7de27ee4 100644
--- a/llvm/lib/Target/AMDGPU/VOP1Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP1Instructions.td
@@ -71,7 +71,6 @@ class VOP1_Real <VOP1_Pseudo ps, int EncodingFamily, string real_name = ps.Mnemo
let isCodeGenOnly = 0;
let Constraints = ps.Constraints;
- let DisableEncoding = ps.DisableEncoding;
// copy relevant pseudo op flags
let SubtargetPredicate = ps.SubtargetPredicate;
@@ -80,7 +79,6 @@ class VOP1_Real <VOP1_Pseudo ps, int EncodingFamily, string real_name = ps.Mnemo
let AsmMatchConverter = ps.AsmMatchConverter;
let AsmVariantName = ps.AsmVariantName;
let Constraints = ps.Constraints;
- let DisableEncoding = ps.DisableEncoding;
let TSFlags = ps.TSFlags;
let UseNamedOperandTable = ps.UseNamedOperandTable;
let Uses = ps.Uses;
@@ -584,7 +582,6 @@ def VOP_SWAP_I32 : VOPProfile<[i32, i32, untyped, untyped]> {
let SubtargetPredicate = isGFX9Plus in {
def V_SWAP_B32 : VOP1_Pseudo<"v_swap_b32", VOP_SWAP_I32, [], 1> {
let Constraints = "$vdst = $src1, $vdst1 = $src0";
- let DisableEncoding = "$vdst1,$src1";
let SchedRW = [Write64Bit, Write64Bit];
}
@@ -802,7 +799,6 @@ let SubtargetPredicate = isGFX10Plus in {
def V_SWAPREL_B32 : VOP1_Pseudo<"v_swaprel_b32", VOP_SWAP_I32, [], 1> {
let Constraints = "$vdst = $src1, $vdst1 = $src0";
- let DisableEncoding = "$vdst1,$src1";
let SchedRW = [Write64Bit, Write64Bit];
}
} // End Uses = [M0]
@@ -831,7 +827,6 @@ def VOP_SWAP_I16 : VOPProfile_True16<VOP_I16_I16> {
let SubtargetPredicate = isGFX11Plus in {
def V_SWAP_B16 : VOP1_Pseudo<"v_swap_b16", VOP_SWAP_I16, [], /* VOP1Only= */true> {
let Constraints = "$vdst = $src1, $vdst1 = $src0";
- let DisableEncoding = "$vdst1, $src1";
let SchedRW = [Write64Bit, Write64Bit];
let True16Predicate = UseRealTrue16Insts;
}
@@ -849,7 +844,6 @@ let SubtargetPredicate = HasPrngInst in
defm V_PRNG_B32 : VOP1Inst <"v_prng_b32", VOP_I32_I32, int_amdgcn_prng_b32>;
let Constraints = "$vdst = $vdst_in, $src0_out = $src0",
- DisableEncoding="$vdst_in,$src0_out",
SchedRW = [Write32Bit, Write32Bit],
isConvergent = 1 in {
let SubtargetPredicate = HasPermlane16Swap in {
diff --git a/llvm/lib/Target/AMDGPU/VOP2Instructions.td b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
index 9de7d6d009fe1..4f6b7c5923397 100644
--- a/llvm/lib/Target/AMDGPU/VOP2Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP2Instructions.td
@@ -105,7 +105,6 @@ class VOP2_Real <VOP2_Pseudo ps, int EncodingFamily, string real_name = ps.Mnemo
let isCodeGenOnly = 0;
let Constraints = ps.Constraints;
- let DisableEncoding = ps.DisableEncoding;
// copy relevant pseudo op flags
let SubtargetPredicate = ps.SubtargetPredicate;
@@ -114,7 +113,6 @@ class VOP2_Real <VOP2_Pseudo ps, int EncodingFamily, string real_name = ps.Mnemo
let AsmMatchConverter = ps.AsmMatchConverter;
let AsmVariantName = ps.AsmVariantName;
let Constraints = ps.Constraints;
- let DisableEncoding = ps.DisableEncoding;
let TSFlags = ps.TSFlags;
let UseNamedOperandTable = ps.UseNamedOperandTable;
let Uses = ps.Uses;
@@ -889,13 +887,13 @@ defm V_XOR_B32 : VOP2Inst <"v_xor_b32", VOP_PAT_GEN<VOP_I32_I32_I32>, xor>;
let mayRaiseFPException = 0 in {
let OtherPredicates = [HasMadMacF32Insts] in {
-let Constraints = "$vdst = $src2", DisableEncoding="$src2",
+let Constraints = "$vdst = $src2",
isConvertibleToThreeAddress = 1 in {
defm V_MAC_F32 : VOP2Inst <"v_mac_f32", VOP_MAC_F32>;
let SubtargetPredicate = isGFX6GFX7GFX10 in
defm V_MAC_LEGACY_F32 : VOP2Inst <"v_mac_legacy_f32", VOP_MAC_LEGACY_F32>;
-} // End Constraints = "$vdst = $src2", DisableEncoding="$src2",
+} // End Constraints = "$vdst = $src2",
// isConvertibleToThreeAddress = 1
let isReMaterializable = 1 in
@@ -941,9 +939,9 @@ defm V_MUL_U64 : VOP2Inst <"v_mul_u64", VOP_I64_I64_I64, DivergentBinFrag<mul>>;
// These are special and do not read the exec mask.
let isConvergent = 1, Uses = []<Register> in {
def V_READLANE_B32 : VOP2_Pseudo<"v_readlane_b32", VOP_READLANE, []>;
-let IsNeverUniform = 1, Constraints = "$vdst = $vdst_in", DisableEncoding="$vdst_in" in {
+let IsNeverUniform = 1, Constraints = "$vdst = $vdst_in" in {
def V_WRITELANE_B32 : VOP2_Pseudo<"v_writelane_b32", VOP_WRITELANE, []>;
-} // End IsNeverUniform, $vdst = $vdst_in, DisableEncoding $vdst_in
+} // End IsNeverUniform, $vdst = $vdst_in
} // End isConvergent = 1
foreach vt = Reg32Types.types in {
@@ -1175,7 +1173,6 @@ let True16Predicate = UseFakeTrue16Insts in {
} // End FPDPRounding = 1, isReMaterializable = 1, FixedSize = 1
let Constraints = "$vdst = $src2",
- DisableEncoding="$src2",
isConvertibleToThreeAddress = 1,
isCommutable = 1 in {
let SubtargetPredicate = isGFX10Plus in {
@@ -1209,7 +1206,7 @@ let SubtargetPredicate = isGFX8GFX9 in {
} // End isReMaterializable = 1
// FIXME: Missing FPDPRounding
-let Constraints = "$vdst = $src2", DisableEncoding="$src2",
+let Constraints = "$vdst = $src2",
isConvertibleToThreeAddress = 1, isCommutable = 1 in {
defm V_MAC_F16 : VOP2Inst <"v_mac_f16", VOP_MAC_F16>;
}
@@ -1252,7 +1249,6 @@ def : GCNPat<
>;
let Constraints = "$vdst = $src2",
- DisableEncoding = "$src2",
isConvertibleToThreeAddress = 1,
isCommutable = 1 in
defm V_FMAC_F32 : VOP2Inst_VOPD <"v_fmac_f32", VOP_MAC_F32, 0x0, "v_fmac_f32">;
@@ -1261,7 +1257,6 @@ defm V_FMAC_F32 : VOP2Inst_VOPD <"v_fmac_f32", VOP_MAC_F32, 0x0, "v_fmac_f32">;
let SubtargetPredicate = HasFmaLegacy32 in {
let Constraints = "$vdst = $src2",
- DisableEncoding = "$src2",
isConvertibleToThreeAddress = 1,
isCommutable = 1 in
defm V_FMAC_LEGACY_F32 : VOP2Inst <"v_fmac_legacy_f32", VOP_MAC_LEGACY_F32>;
@@ -1270,14 +1265,12 @@ defm V_FMAC_LEGACY_F32 : VOP2Inst <"v_fmac_legacy_f32", VOP_MAC_LEGACY_F32>;
let SubtargetPredicate = HasFmacF64Inst,
Constraints = "$vdst = $src2",
- DisableEncoding="$src2",
isConvertibleToThreeAddress = 1,
isCommutable = 1,
SchedRW = [WriteDoubleAdd] in
defm V_FMAC_F64 : VOP2Inst <"v_fmac_f64", VOP_MAC_F64>;
let Constraints = "$vdst = $src2",
- DisableEncoding="$src2",
isConvertibleToThreeAddress = 1,
isCommutable = 1,
IsDOT = 1 in {
diff --git a/llvm/lib/Target/AMDGPU/VOP3Instructions.td b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
index 329d003cf2506..19eabb46752bf 100644
--- a/llvm/lib/Target/AMDGPU/VOP3Instructions.td
+++ b/llvm/lib/Target/AMDGPU/VOP3Instructions.td
@@ -782,7 +782,7 @@ defm V_LSHL_ADD_U64 : VOP3Inst <"v_lshl_add_u64", V_LSHL_ADD_U64_PROF>;
let OtherPredicates = [HasFP8ConversionInsts], mayRaiseFPException = 0,
SchedRW = [WriteFloatCvt] in {
- let Constraints = "$vdst = $vdst_in", DisableEncoding = "$vdst_in" in {
+ let Constraints = "$vdst = $vdst_in" in {
let OtherPredicates = [HasFP8ConversionInsts, NotHasFP8E5M3Insts] in
defm V_CVT_PK_FP8_F32 : VOP3Inst_t16_with_profiles<"v_cvt_pk_fp8_f32", VOP3_CVT_PK_F8_F32_Profile<>,
VOP3_CVT_PK_F8_F32_Profile_t16<>,
@@ -807,7 +807,7 @@ let OtherPredicates = [HasFP8ConversionInsts], mayRaiseFPException = 0,
// These instructions have non-standard use of op_sel. In particular they are
// using op_sel bits 2 and 3 while only having two sources. Therefore dummy
// src2 is used to hold the op_sel value.
- let Constraints = "$vdst = $src2", DisableEncoding = "$src2", SubtargetPredicate = isGFX940Plus in {
+ let Constraints = "$vdst = $src2", SubtargetPredicate = isGFX940Plus in {
defm V_CVT_SR_FP8_F32 : VOP3Inst<"v_cvt_sr_fp8_f32", VOP3_CVT_SR_F8_F32_Profile>;
defm V_CVT_SR_BF8_F32 : VOP3Inst<"v_cvt_sr_bf8_f32", VOP3_CVT_SR_F8_F32_Profile>;
}
@@ -1309,7 +1309,7 @@ class VOP3_CVT_SCALEF32_PK_F864_Profile<VOPProfile P> : VOP3_Profile<P> {
}
let SubtargetPredicate = HasFP8ConversionScaleInsts, mayRaiseFPException = 0 in {
- let Constraints = "$vdst = $vdst_in", DisableEncoding="$vdst_in" in {
+ let Constraints = "$vdst = $vdst_in" in {
defm V_CVT_SCALEF32_SR_FP8_BF16 : VOP3Inst...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/156098
More information about the llvm-commits
mailing list