[llvm] [NVPTX] Remove unsupported 'seq_cst' test (PR #156088)

[Alex MacLean via llvm-commits]

https://github.com/AlexMaclean created https://github.com/llvm/llvm-project/pull/156088

The NVPTX backend does not currently support correctly lowering `atomicrmw` with `seq_cst` of any size. Remove a test which erroneously hit this case and add logic to appropriately error out when this ordering is encountered, instead of emitting invalid PTX.  

In the long term, we should use `fence.sc`, similar to other atomic operations, to support this ordering.

>From 99d31347ba7af41ab5d9cbc3a3a8f8bc340fd044 Mon Sep 17 00:00:00 2001
From: Alex Maclean <amaclean at nvidia.com>
Date: Fri, 29 Aug 2025 19:32:18 +0000
Subject: [PATCH] [NVPTX] Remove unsupported 'seq_cst' test

---
 llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp | 2 +-
 llvm/test/CodeGen/NVPTX/atomics-b128.ll                 | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp b/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
index ee1ca4538554b..09bb01b0df172 100644
--- a/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
+++ b/llvm/lib/Target/NVPTX/MCTargetDesc/NVPTXInstPrinter.cpp
@@ -290,7 +290,7 @@ void NVPTXInstPrinter::printAtomicCode(const MCInst *MI, int OpNum,
       O << ".acq_rel";
       return;
     case NVPTX::Ordering::SequentiallyConsistent:
-      O << ".seq_cst";
+      report_fatal_error("NVPTX AtomicCode Printer does not support \"seq_cst\" ordering.");
       return;
     case NVPTX::Ordering::Volatile:
       O << ".volatile";
diff --git a/llvm/test/CodeGen/NVPTX/atomics-b128.ll b/llvm/test/CodeGen/NVPTX/atomics-b128.ll
index a6aa97a614151..02dfb4685dd16 100644
--- a/llvm/test/CodeGen/NVPTX/atomics-b128.ll
+++ b/llvm/test/CodeGen/NVPTX/atomics-b128.ll
@@ -1024,10 +1024,10 @@ define void @test_atomicrmw_xchg_const() {
 ; CHECK-NEXT:    {
 ; CHECK-NEXT:    .reg .b128 amt, dst;
 ; CHECK-NEXT:    mov.b128 amt, {%rd2, %rd1};
-; CHECK-NEXT:    atom.seq_cst.sys.shared.exch.b128 dst, [si128], amt;
+; CHECK-NEXT:    atom.relaxed.sys.shared.exch.b128 dst, [si128], amt;
 ; CHECK-NEXT:    mov.b128 {%rd3, %rd4}, dst;
 ; CHECK-NEXT:    }
 ; CHECK-NEXT:    ret;
-	%res = atomicrmw xchg ptr addrspace(3) @si128, i128 23 seq_cst
+  %res = atomicrmw xchg ptr addrspace(3) @si128, i128 23 monotonic
   ret void
 }