[llvm] [RISCV] Loosen the requirement of shadow stack codegen to Zimop (PR #152251)

[Craig Topper via llvm-commits]

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@@ -106,8 +106,14 @@ static void emitSCSPrologue(MachineFunction &MF, MachineBasicBlock &MBB,
                             MachineBasicBlock::iterator MI,
                             const DebugLoc &DL) {
   const auto &STI = MF.getSubtarget<RISCVSubtarget>();
+  // We check Zimop instead of Zimop || Zcmop to determine whether HW shadow
+  // stack is available despite the fact that sspush/sspopchk both have a
+  // compressed form because if only Zcmop is available, we would need to
+  // reserve X5 due to c.sspopchk only takes X5 and we currently doesn't
+  // support using X5 as the return address regsister.
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topperc wrote:

```suggestion
  // support using X5 as the return address register.
```

https://github.com/llvm/llvm-project/pull/152251