[llvm] [RISCV] Use C.ADD when OR is not compressible due to register restriction (PR #156044)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp -- llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
``````````

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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
index f10d2a1cc..f0e4631e5 100644
--- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -1186,10 +1186,9 @@ bool RISCVAsmPrinter::lowerToMCInst(const MachineInstr *MI, MCInst &OutMI) {
     Register Rd = MI->getOperand(0).getReg();
     Register Rs1 = MI->getOperand(1).getReg();
     Register Rs2 = MI->getOperand(2).getReg();
-    if ((Rd == Rs1 || Rd == Rs2) &&
-        !(RISCV::GPRCRegClass.contains(Rd) &&
-          RISCV::GPRCRegClass.contains(Rs1) &&
-          RISCV::GPRCRegClass.contains(Rs2)))
+    if ((Rd == Rs1 || Rd == Rs2) && !(RISCV::GPRCRegClass.contains(Rd) &&
+                                      RISCV::GPRCRegClass.contains(Rs1) &&
+                                      RISCV::GPRCRegClass.contains(Rs2)))
       Opcode = RISCV::ADD;
   }
   OutMI.setOpcode(Opcode);

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https://github.com/llvm/llvm-project/pull/156044