[llvm] 19464d9 - [NFC] #155740 post cleanup (#155966)
via llvm-commits
llvm-commits at lists.llvm.org
Thu Aug 28 21:45:42 PDT 2025
Author: paperchalice
Date: 2025-08-29T12:45:38+08:00
New Revision: 19464d951a93f48fad7332d59ec1e2f1d853c777
URL: https://github.com/llvm/llvm-project/commit/19464d951a93f48fad7332d59ec1e2f1d853c777
DIFF: https://github.com/llvm/llvm-project/commit/19464d951a93f48fad7332d59ec1e2f1d853c777.diff
LOG: [NFC] #155740 post cleanup (#155966)
Remove all "approx-func-fp-math" in tests.
Added:
Modified:
llvm/test/CodeGen/AMDGPU/fsqrt.f64.ll
llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
llvm/test/CodeGen/AMDGPU/llvm.log2.ll
llvm/test/CodeGen/DirectX/ForwardHandleAccesses/cbuffer-access.ll
llvm/test/CodeGen/DirectX/ShaderFlags/disable-opt-cs.ll
llvm/test/CodeGen/DirectX/ShaderFlags/disable-opt-lib.ll
llvm/test/CodeGen/DirectX/ShaderFlags/lib-entry-attr-error.ll
llvm/test/CodeGen/Hexagon/loopIdiom.ll
llvm/test/CodeGen/PowerPC/lower-scalar-mass-afn.ll
llvm/test/CodeGen/PowerPC/pow-025-075-intrinsic-scalar-mass-fast.ll
llvm/test/CodeGen/PowerPC/pow-025-075-nointrinsic-scalar-mass-fast.ll
llvm/test/CodeGen/SPIRV/hlsl-resources/StructuredBuffer.ll
llvm/test/CodeGen/SPIRV/hlsl-resources/spirv.layout.type.ll
llvm/test/Transforms/PhaseOrdering/AArch64/reduce_muladd.ll
llvm/test/Transforms/PhaseOrdering/AArch64/reduce_submuladd.ll
llvm/test/Transforms/PhaseOrdering/AArch64/slpordering.ll
llvm/test/Transforms/PhaseOrdering/ARM/arm_mean_q7.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/fsqrt.f64.ll b/llvm/test/CodeGen/AMDGPU/fsqrt.f64.ll
index cffa287dd91f5..76e15eed08cc2 100644
--- a/llvm/test/CodeGen/AMDGPU/fsqrt.f64.ll
+++ b/llvm/test/CodeGen/AMDGPU/fsqrt.f64.ll
@@ -2762,122 +2762,6 @@ define double @v_sqrt_f64_afn_nnan_ninf_nsz(double %x) {
ret double %result
}
-define double @v_sqrt_f64__approx_func_fp_math(double %x) #2 {
-; GFX6-SDAG-LABEL: v_sqrt_f64__approx_func_fp_math:
-; GFX6-SDAG: ; %bb.0:
-; GFX6-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-SDAG-NEXT: s_mov_b32 s4, 0
-; GFX6-SDAG-NEXT: s_brev_b32 s5, 8
-; GFX6-SDAG-NEXT: v_cmp_gt_f64_e32 vcc, s[4:5], v[0:1]
-; GFX6-SDAG-NEXT: v_mov_b32_e32 v2, 0x100
-; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX6-SDAG-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2
-; GFX6-SDAG-NEXT: v_rsq_f64_e32 v[2:3], v[0:1]
-; GFX6-SDAG-NEXT: v_mul_f64 v[4:5], v[0:1], v[2:3]
-; GFX6-SDAG-NEXT: v_mul_f64 v[2:3], v[2:3], 0.5
-; GFX6-SDAG-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 0.5
-; GFX6-SDAG-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
-; GFX6-SDAG-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]
-; GFX6-SDAG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
-; GFX6-SDAG-NEXT: v_fma_f64 v[4:5], v[6:7], v[2:3], v[4:5]
-; GFX6-SDAG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
-; GFX6-SDAG-NEXT: v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
-; GFX6-SDAG-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; GFX6-SDAG-NEXT: v_mov_b32_e32 v5, 0x260
-; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX6-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
-; GFX6-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
-; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; GFX6-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
-; GFX6-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-SDAG-LABEL: v_sqrt_f64__approx_func_fp_math:
-; GFX8-SDAG: ; %bb.0:
-; GFX8-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-SDAG-NEXT: s_mov_b32 s4, 0
-; GFX8-SDAG-NEXT: s_brev_b32 s5, 8
-; GFX8-SDAG-NEXT: v_cmp_gt_f64_e32 vcc, s[4:5], v[0:1]
-; GFX8-SDAG-NEXT: v_mov_b32_e32 v2, 0x100
-; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX8-SDAG-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2
-; GFX8-SDAG-NEXT: v_rsq_f64_e32 v[2:3], v[0:1]
-; GFX8-SDAG-NEXT: v_mul_f64 v[4:5], v[0:1], v[2:3]
-; GFX8-SDAG-NEXT: v_mul_f64 v[2:3], v[2:3], 0.5
-; GFX8-SDAG-NEXT: v_fma_f64 v[6:7], -v[2:3], v[4:5], 0.5
-; GFX8-SDAG-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
-; GFX8-SDAG-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]
-; GFX8-SDAG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
-; GFX8-SDAG-NEXT: v_fma_f64 v[4:5], v[6:7], v[2:3], v[4:5]
-; GFX8-SDAG-NEXT: v_fma_f64 v[6:7], -v[4:5], v[4:5], v[0:1]
-; GFX8-SDAG-NEXT: v_fma_f64 v[2:3], v[6:7], v[2:3], v[4:5]
-; GFX8-SDAG-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; GFX8-SDAG-NEXT: v_mov_b32_e32 v5, 0x260
-; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX8-SDAG-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
-; GFX8-SDAG-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
-; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; GFX8-SDAG-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
-; GFX8-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX6-GISEL-LABEL: v_sqrt_f64__approx_func_fp_math:
-; GFX6-GISEL: ; %bb.0:
-; GFX6-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; GFX6-GISEL-NEXT: v_bfrev_b32_e32 v3, 8
-; GFX6-GISEL-NEXT: v_cmp_lt_f64_e32 vcc, v[0:1], v[2:3]
-; GFX6-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; GFX6-GISEL-NEXT: v_lshlrev_b32_e32 v2, 8, v2
-; GFX6-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2
-; GFX6-GISEL-NEXT: v_rsq_f64_e32 v[2:3], v[0:1]
-; GFX6-GISEL-NEXT: v_mul_f64 v[4:5], v[2:3], 0.5
-; GFX6-GISEL-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
-; GFX6-GISEL-NEXT: v_fma_f64 v[6:7], -v[4:5], v[2:3], 0.5
-; GFX6-GISEL-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]
-; GFX6-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
-; GFX6-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
-; GFX6-GISEL-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
-; GFX6-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
-; GFX6-GISEL-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
-; GFX6-GISEL-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; GFX6-GISEL-NEXT: v_mov_b32_e32 v5, 0x260
-; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX6-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
-; GFX6-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
-; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; GFX6-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
-; GFX6-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX8-GISEL-LABEL: v_sqrt_f64__approx_func_fp_math:
-; GFX8-GISEL: ; %bb.0:
-; GFX8-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX8-GISEL-NEXT: v_mov_b32_e32 v2, 0
-; GFX8-GISEL-NEXT: v_bfrev_b32_e32 v3, 8
-; GFX8-GISEL-NEXT: v_cmp_lt_f64_e32 vcc, v[0:1], v[2:3]
-; GFX8-GISEL-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
-; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v2, 8, v2
-; GFX8-GISEL-NEXT: v_ldexp_f64 v[0:1], v[0:1], v2
-; GFX8-GISEL-NEXT: v_rsq_f64_e32 v[2:3], v[0:1]
-; GFX8-GISEL-NEXT: v_mul_f64 v[4:5], v[2:3], 0.5
-; GFX8-GISEL-NEXT: v_mul_f64 v[2:3], v[0:1], v[2:3]
-; GFX8-GISEL-NEXT: v_fma_f64 v[6:7], -v[4:5], v[2:3], 0.5
-; GFX8-GISEL-NEXT: v_fma_f64 v[2:3], v[2:3], v[6:7], v[2:3]
-; GFX8-GISEL-NEXT: v_fma_f64 v[4:5], v[4:5], v[6:7], v[4:5]
-; GFX8-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
-; GFX8-GISEL-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
-; GFX8-GISEL-NEXT: v_fma_f64 v[6:7], -v[2:3], v[2:3], v[0:1]
-; GFX8-GISEL-NEXT: v_fma_f64 v[2:3], v[6:7], v[4:5], v[2:3]
-; GFX8-GISEL-NEXT: v_mov_b32_e32 v4, 0xffffff80
-; GFX8-GISEL-NEXT: v_mov_b32_e32 v5, 0x260
-; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v4, 0, v4, vcc
-; GFX8-GISEL-NEXT: v_cmp_class_f64_e32 vcc, v[0:1], v5
-; GFX8-GISEL-NEXT: v_ldexp_f64 v[2:3], v[2:3], v4
-; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
-; GFX8-GISEL-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
-; GFX8-GISEL-NEXT: s_setpc_b64 s[30:31]
- %result = call nsz double @llvm.sqrt.f64(double %x)
- ret double %result
-}
-
define double @v_sqrt_f64__enough_unsafe_attrs(double %x) #3 {
; GFX6-SDAG-LABEL: v_sqrt_f64__enough_unsafe_attrs:
; GFX6-SDAG: ; %bb.0:
@@ -3580,8 +3464,7 @@ declare i32 @llvm.amdgcn.readfirstlane(i32) #1
attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
attributes #1 = { convergent nounwind willreturn memory(none) }
-attributes #2 = { "approx-func-fp-math"="true" }
-attributes #3 = { "approx-func-fp-math"="true" "no-nans-fp-math"="true" "no-infs-fp-math"="true" }
+attributes #3 = { "no-nans-fp-math"="true" "no-infs-fp-math"="true" }
attributes #4 = { "unsafe-fp-math"="true" }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GFX6: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.exp2.ll b/llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
index e71ea505caea1..883db20a867b3 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.exp2.ll
@@ -1583,104 +1583,6 @@ define float @v_exp2_f32_unsafe_math_attr(float %in) "unsafe-fp-math"="true" {
ret float %result
}
-define float @v_exp2_f32_approx_fn_attr(float %in) "approx-func-fp-math"="true" {
-; SI-SDAG-LABEL: v_exp2_f32_approx_fn_attr:
-; SI-SDAG: ; %bb.0:
-; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
-; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; SI-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
-; SI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; SI-SDAG-NEXT: v_add_f32_e32 v0, v0, v2
-; SI-SDAG-NEXT: v_exp_f32_e32 v0, v0
-; SI-SDAG-NEXT: v_not_b32_e32 v1, 63
-; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v1
-; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; SI-GISEL-LABEL: v_exp2_f32_approx_fn_attr:
-; SI-GISEL: ; %bb.0:
-; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
-; SI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
-; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
-; SI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
-; SI-GISEL-NEXT: v_exp_f32_e32 v0, v0
-; SI-GISEL-NEXT: v_not_b32_e32 v1, 63
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
-; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-SDAG-LABEL: v_exp2_f32_approx_fn_attr:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
-; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; VI-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
-; VI-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; VI-SDAG-NEXT: v_add_f32_e32 v0, v0, v2
-; VI-SDAG-NEXT: v_exp_f32_e32 v0, v0
-; VI-SDAG-NEXT: v_not_b32_e32 v1, 63
-; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
-; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-GISEL-LABEL: v_exp2_f32_approx_fn_attr:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
-; VI-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
-; VI-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
-; VI-GISEL-NEXT: v_exp_f32_e32 v0, v0
-; VI-GISEL-NEXT: v_not_b32_e32 v1, 63
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
-; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX900-SDAG-LABEL: v_exp2_f32_approx_fn_attr:
-; GFX900-SDAG: ; %bb.0:
-; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-SDAG-NEXT: s_mov_b32 s4, 0xc2fc0000
-; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX900-SDAG-NEXT: v_mov_b32_e32 v2, 0x42800000
-; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v2, 0, v2, vcc
-; GFX900-SDAG-NEXT: v_add_f32_e32 v0, v0, v2
-; GFX900-SDAG-NEXT: v_exp_f32_e32 v0, v0
-; GFX900-SDAG-NEXT: v_not_b32_e32 v1, 63
-; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX900-GISEL-LABEL: v_exp2_f32_approx_fn_attr:
-; GFX900-GISEL: ; %bb.0:
-; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0xc2fc0000
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v2, 0x42800000
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v2, vcc
-; GFX900-GISEL-NEXT: v_add_f32_e32 v0, v0, v1
-; GFX900-GISEL-NEXT: v_exp_f32_e32 v0, v0
-; GFX900-GISEL-NEXT: v_not_b32_e32 v1, 63
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; R600-LABEL: v_exp2_f32_approx_fn_attr:
-; R600: ; %bb.0:
-; R600-NEXT: CF_END
-; R600-NEXT: PAD
-;
-; CM-LABEL: v_exp2_f32_approx_fn_attr:
-; CM: ; %bb.0:
-; CM-NEXT: CF_END
-; CM-NEXT: PAD
- %result = call float @llvm.exp2.f32(float %in)
- ret float %result
-}
-
define float @v_exp2_f32_ninf(float %in) {
; SI-SDAG-LABEL: v_exp2_f32_ninf:
; SI-SDAG: ; %bb.0:
diff --git a/llvm/test/CodeGen/AMDGPU/llvm.log2.ll b/llvm/test/CodeGen/AMDGPU/llvm.log2.ll
index 4ca612aa32e84..0854134be6f46 100644
--- a/llvm/test/CodeGen/AMDGPU/llvm.log2.ll
+++ b/llvm/test/CodeGen/AMDGPU/llvm.log2.ll
@@ -2030,129 +2030,6 @@ define float @v_log2_f32_unsafe_math_attr(float %in) "unsafe-fp-math"="true" {
ret float %result
}
-define float @v_log2_f32_approx_fn_attr(float %in) "approx-func-fp-math"="true" {
-; SI-SDAG-LABEL: v_log2_f32_approx_fn_attr:
-; SI-SDAG: ; %bb.0:
-; SI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-SDAG-NEXT: s_mov_b32 s4, 0x800000
-; SI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; SI-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; SI-SDAG-NEXT: v_ldexp_f32_e32 v0, v0, v2
-; SI-SDAG-NEXT: v_log_f32_e32 v0, v0
-; SI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
-; SI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; SI-GISEL-LABEL: v_log2_f32_approx_fn_attr:
-; SI-GISEL: ; %bb.0:
-; SI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
-; SI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; SI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; SI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
-; SI-GISEL-NEXT: v_ldexp_f32_e32 v0, v0, v1
-; SI-GISEL-NEXT: v_log_f32_e32 v0, v0
-; SI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
-; SI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; SI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
-; SI-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-SDAG-LABEL: v_log2_f32_approx_fn_attr:
-; VI-SDAG: ; %bb.0:
-; VI-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-SDAG-NEXT: s_mov_b32 s4, 0x800000
-; VI-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; VI-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; VI-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
-; VI-SDAG-NEXT: v_log_f32_e32 v0, v0
-; VI-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
-; VI-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; VI-GISEL-LABEL: v_log2_f32_approx_fn_attr:
-; VI-GISEL: ; %bb.0:
-; VI-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
-; VI-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; VI-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; VI-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
-; VI-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
-; VI-GISEL-NEXT: v_log_f32_e32 v0, v0
-; VI-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
-; VI-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; VI-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
-; VI-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX900-SDAG-LABEL: v_log2_f32_approx_fn_attr:
-; GFX900-SDAG: ; %bb.0:
-; GFX900-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-SDAG-NEXT: s_mov_b32 s4, 0x800000
-; GFX900-SDAG-NEXT: v_cmp_gt_f32_e32 vcc, s4, v0
-; GFX900-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc
-; GFX900-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX900-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX900-SDAG-NEXT: v_mov_b32_e32 v1, 0x42000000
-; GFX900-SDAG-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX900-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX900-GISEL-LABEL: v_log2_f32_approx_fn_attr:
-; GFX900-GISEL: ; %bb.0:
-; GFX900-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x800000
-; GFX900-GISEL-NEXT: v_cmp_lt_f32_e32 vcc, v0, v1
-; GFX900-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
-; GFX900-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
-; GFX900-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX900-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX900-GISEL-NEXT: v_mov_b32_e32 v1, 0x42000000
-; GFX900-GISEL-NEXT: v_cndmask_b32_e32 v1, 0, v1, vcc
-; GFX900-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX900-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1100-SDAG-LABEL: v_log2_f32_approx_fn_attr:
-; GFX1100-SDAG: ; %bb.0:
-; GFX1100-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-SDAG-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v2, 0, 32, vcc_lo
-; GFX1100-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
-; GFX1100-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-SDAG-NEXT: v_ldexp_f32 v0, v0, v2
-; GFX1100-SDAG-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-SDAG-NEXT: s_waitcnt_depctr 0xfff
-; GFX1100-SDAG-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-SDAG-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX1100-GISEL-LABEL: v_log2_f32_approx_fn_attr:
-; GFX1100-GISEL: ; %bb.0:
-; GFX1100-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX1100-GISEL-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0x800000, v0
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1100-GISEL-NEXT: v_lshlrev_b32_e32 v1, 5, v1
-; GFX1100-GISEL-NEXT: v_ldexp_f32 v0, v0, v1
-; GFX1100-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 0x42000000, vcc_lo
-; GFX1100-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1100-GISEL-NEXT: v_log_f32_e32 v0, v0
-; GFX1100-GISEL-NEXT: s_waitcnt_depctr 0xfff
-; GFX1100-GISEL-NEXT: v_sub_f32_e32 v0, v0, v1
-; GFX1100-GISEL-NEXT: s_setpc_b64 s[30:31]
-;
-; R600-LABEL: v_log2_f32_approx_fn_attr:
-; R600: ; %bb.0:
-; R600-NEXT: CF_END
-; R600-NEXT: PAD
-;
-; CM-LABEL: v_log2_f32_approx_fn_attr:
-; CM: ; %bb.0:
-; CM-NEXT: CF_END
-; CM-NEXT: PAD
- %result = call float @llvm.log2.f32(float %in)
- ret float %result
-}
-
define float @v_log2_f32_ninf(float %in) {
; SI-SDAG-LABEL: v_log2_f32_ninf:
; SI-SDAG: ; %bb.0:
diff --git a/llvm/test/CodeGen/DirectX/ForwardHandleAccesses/cbuffer-access.ll b/llvm/test/CodeGen/DirectX/ForwardHandleAccesses/cbuffer-access.ll
index ca3c9427617a6..26b157f35a3e4 100644
--- a/llvm/test/CodeGen/DirectX/ForwardHandleAccesses/cbuffer-access.ll
+++ b/llvm/test/CodeGen/DirectX/ForwardHandleAccesses/cbuffer-access.ll
@@ -29,4 +29,4 @@ entry:
ret void
}
-attributes #0 = { mustprogress nofree noinline norecurse nosync nounwind willreturn memory(readwrite, argmem: write, inaccessiblemem: none) "approx-func-fp-math"="false" "frame-pointer"="all" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
+attributes #0 = { mustprogress nofree noinline norecurse nosync nounwind willreturn memory(readwrite, argmem: write, inaccessiblemem: none) "frame-pointer"="all" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
diff --git a/llvm/test/CodeGen/DirectX/ShaderFlags/disable-opt-cs.ll b/llvm/test/CodeGen/DirectX/ShaderFlags/disable-opt-cs.ll
index 3f2ec9a85b2a0..4bdb7ec50f6f4 100644
--- a/llvm/test/CodeGen/DirectX/ShaderFlags/disable-opt-cs.ll
+++ b/llvm/test/CodeGen/DirectX/ShaderFlags/disable-opt-cs.ll
@@ -30,5 +30,5 @@ entry:
ret i32 0
}
-attributes #0 = { convergent noinline norecurse optnone "approx-func-fp-math"="true" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
-attributes #1 = { alwaysinline convergent mustprogress norecurse nounwind "approx-func-fp-math"="true" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
+attributes #0 = { convergent noinline norecurse optnone "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
+attributes #1 = { alwaysinline convergent mustprogress norecurse nounwind "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
diff --git a/llvm/test/CodeGen/DirectX/ShaderFlags/disable-opt-lib.ll b/llvm/test/CodeGen/DirectX/ShaderFlags/disable-opt-lib.ll
index c6e3cc9e96478..03756710adc3a 100644
--- a/llvm/test/CodeGen/DirectX/ShaderFlags/disable-opt-lib.ll
+++ b/llvm/test/CodeGen/DirectX/ShaderFlags/disable-opt-lib.ll
@@ -40,5 +40,5 @@ entry:
ret i32 0
}
-attributes #0 = { convergent mustprogress noinline norecurse nounwind optnone "approx-func-fp-math"="true" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
-attributes #1 = { convergent noinline norecurse optnone "approx-func-fp-math"="true" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
+attributes #0 = { convergent mustprogress noinline norecurse nounwind optnone "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
+attributes #1 = { convergent noinline norecurse optnone "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
diff --git a/llvm/test/CodeGen/DirectX/ShaderFlags/lib-entry-attr-error.ll b/llvm/test/CodeGen/DirectX/ShaderFlags/lib-entry-attr-error.ll
index 74d5fd093ded6..ce35c03d6bcfa 100644
--- a/llvm/test/CodeGen/DirectX/ShaderFlags/lib-entry-attr-error.ll
+++ b/llvm/test/CodeGen/DirectX/ShaderFlags/lib-entry-attr-error.ll
@@ -19,8 +19,8 @@ entry:
ret void
}
-attributes #0 = { convergent noinline norecurse optnone "approx-func-fp-math"="true" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
-attributes #1 = { convergent noinline norecurse "approx-func-fp-math"="true" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
+attributes #0 = { convergent noinline norecurse optnone "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
+attributes #1 = { convergent noinline norecurse "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
!llvm.module.flags = !{!0, !1}
!dx.valver = !{!2}
diff --git a/llvm/test/CodeGen/Hexagon/loopIdiom.ll b/llvm/test/CodeGen/Hexagon/loopIdiom.ll
index 9c3df674a4937..31f346943f32f 100644
--- a/llvm/test/CodeGen/Hexagon/loopIdiom.ll
+++ b/llvm/test/CodeGen/Hexagon/loopIdiom.ll
@@ -61,7 +61,7 @@ if.end: ; preds = %for.end7, %entry
ret void
}
-attributes #0 = { noinline nounwind "approx-func-fp-math"="true" "frame-pointer"="all" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv79" "target-features"="+v79,-long-calls" "unsafe-fp-math"="true" }
+attributes #0 = { noinline nounwind "frame-pointer"="all" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv79" "target-features"="+v79,-long-calls" "unsafe-fp-math"="true" }
!llvm.module.flags = !{!0, !1}
!llvm.ident = !{!2}
diff --git a/llvm/test/CodeGen/PowerPC/lower-scalar-mass-afn.ll b/llvm/test/CodeGen/PowerPC/lower-scalar-mass-afn.ll
index 018fbe99ce499..f3085ccc85c88 100644
--- a/llvm/test/CodeGen/PowerPC/lower-scalar-mass-afn.ll
+++ b/llvm/test/CodeGen/PowerPC/lower-scalar-mass-afn.ll
@@ -81,7 +81,7 @@ declare double @__log10_finite (double);
declare double @__pow_finite (double, double);
declare double @__sinh_finite (double);
-define float @acosf_f32(float %a) #0 {
+define float @acosf_f32(float %a) {
; CHECK-LABEL: acosf_f32
; CHECK: __xl_acosf
; CHECK: blr
@@ -90,7 +90,7 @@ entry:
ret float %call
}
-define float @acoshf_f32(float %a) #0 {
+define float @acoshf_f32(float %a) {
; CHECK-LABEL: acoshf_f32
; CHECK: __xl_acoshf
; CHECK: blr
@@ -99,7 +99,7 @@ entry:
ret float %call
}
-define float @asinf_f32(float %a) #0 {
+define float @asinf_f32(float %a) {
; CHECK-LABEL: asinf_f32
; CHECK: __xl_asinf
; CHECK: blr
@@ -108,7 +108,7 @@ entry:
ret float %call
}
-define float @asinhf_f32(float %a) #0 {
+define float @asinhf_f32(float %a) {
; CHECK-LABEL: asinhf_f32
; CHECK: __xl_asinhf
; CHECK: blr
@@ -117,7 +117,7 @@ entry:
ret float %call
}
-define float @atan2f_f32(float %a, float %b) #0 {
+define float @atan2f_f32(float %a, float %b) {
; CHECK-LABEL: atan2f_f32
; CHECK: __xl_atan2f
; CHECK: blr
@@ -126,7 +126,7 @@ entry:
ret float %call
}
-define float @atanf_f32(float %a) #0 {
+define float @atanf_f32(float %a) {
; CHECK-LABEL: atanf_f32
; CHECK: __xl_atanf
; CHECK: blr
@@ -135,7 +135,7 @@ entry:
ret float %call
}
-define float @atanhf_f32(float %a) #0 {
+define float @atanhf_f32(float %a) {
; CHECK-LABEL: atanhf_f32
; CHECK: __xl_atanhf
; CHECK: blr
@@ -144,7 +144,7 @@ entry:
ret float %call
}
-define float @cbrtf_f32(float %a) #0 {
+define float @cbrtf_f32(float %a) {
; CHECK-LABEL: cbrtf_f32
; CHECK: __xl_cbrtf
; CHECK: blr
@@ -153,7 +153,7 @@ entry:
ret float %call
}
-define float @copysignf_f32(float %a, float %b) #0 {
+define float @copysignf_f32(float %a, float %b) {
; CHECK-LABEL: copysignf_f32
; CHECK: copysignf
; CHECK: blr
@@ -162,7 +162,7 @@ entry:
ret float %call
}
-define float @cosf_f32(float %a) #0 {
+define float @cosf_f32(float %a) {
; CHECK-LABEL: cosf_f32
; CHECK: __xl_cosf
; CHECK: blr
@@ -171,7 +171,7 @@ entry:
ret float %call
}
-define float @coshf_f32(float %a) #0 {
+define float @coshf_f32(float %a) {
; CHECK-LABEL: coshf_f32
; CHECK: __xl_coshf
; CHECK: blr
@@ -180,7 +180,7 @@ entry:
ret float %call
}
-define float @erfcf_f32(float %a) #0 {
+define float @erfcf_f32(float %a) {
; CHECK-LABEL: erfcf_f32
; CHECK: __xl_erfcf
; CHECK: blr
@@ -189,7 +189,7 @@ entry:
ret float %call
}
-define float @erff_f32(float %a) #0 {
+define float @erff_f32(float %a) {
; CHECK-LABEL: erff_f32
; CHECK: __xl_erff
; CHECK: blr
@@ -198,7 +198,7 @@ entry:
ret float %call
}
-define float @expf_f32(float %a) #0 {
+define float @expf_f32(float %a) {
; CHECK-LABEL: expf_f32
; CHECK: __xl_expf
; CHECK: blr
@@ -207,7 +207,7 @@ entry:
ret float %call
}
-define float @expm1f_f32(float %a) #0 {
+define float @expm1f_f32(float %a) {
; CHECK-LABEL: expm1f_f32
; CHECK: __xl_expm1f
; CHECK: blr
@@ -216,7 +216,7 @@ entry:
ret float %call
}
-define float @hypotf_f32(float %a, float %b) #0 {
+define float @hypotf_f32(float %a, float %b) {
; CHECK-LABEL: hypotf_f32
; CHECK: __xl_hypotf
; CHECK: blr
@@ -225,7 +225,7 @@ entry:
ret float %call
}
-define float @lgammaf_f32(float %a) #0 {
+define float @lgammaf_f32(float %a) {
; CHECK-LABEL: lgammaf_f32
; CHECK: __xl_lgammaf
; CHECK: blr
@@ -234,7 +234,7 @@ entry:
ret float %call
}
-define float @log10f_f32(float %a) #0 {
+define float @log10f_f32(float %a) {
; CHECK-LABEL: log10f_f32
; CHECK: __xl_log10f
; CHECK: blr
@@ -243,7 +243,7 @@ entry:
ret float %call
}
-define float @log1pf_f32(float %a) #0 {
+define float @log1pf_f32(float %a) {
; CHECK-LABEL: log1pf_f32
; CHECK: __xl_log1pf
; CHECK: blr
@@ -252,7 +252,7 @@ entry:
ret float %call
}
-define float @logf_f32(float %a) #0 {
+define float @logf_f32(float %a) {
; CHECK-LABEL: logf_f32
; CHECK: __xl_logf
; CHECK: blr
@@ -261,7 +261,7 @@ entry:
ret float %call
}
-define float @powf_f32(float %a, float %b) #0 {
+define float @powf_f32(float %a, float %b) {
; CHECK-LABEL: powf_f32
; CHECK: __xl_powf
; CHECK: blr
@@ -270,7 +270,7 @@ entry:
ret float %call
}
-define float @rintf_f32(float %a) #0 {
+define float @rintf_f32(float %a) {
; CHECK-LABEL: rintf_f32
; CHECK-NOT: __xl_rintf
; CHECK: blr
@@ -279,7 +279,7 @@ entry:
ret float %call
}
-define float @sinf_f32(float %a) #0 {
+define float @sinf_f32(float %a) {
; CHECK-LABEL: sinf_f32
; CHECK: __xl_sinf
; CHECK: blr
@@ -288,7 +288,7 @@ entry:
ret float %call
}
-define float @sinhf_f32(float %a) #0 {
+define float @sinhf_f32(float %a) {
; CHECK-LABEL: sinhf_f32
; CHECK: __xl_sinhf
; CHECK: blr
@@ -297,7 +297,7 @@ entry:
ret float %call
}
-define float @tanf_f32(float %a) #0 {
+define float @tanf_f32(float %a) {
; CHECK-LABEL: tanf_f32
; CHECK: __xl_tanf
; CHECK: blr
@@ -306,7 +306,7 @@ entry:
ret float %call
}
-define float @tanhf_f32(float %a) #0 {
+define float @tanhf_f32(float %a) {
; CHECK-LABEL: tanhf_f32
; CHECK: __xl_tanhf
; CHECK: blr
@@ -315,7 +315,7 @@ entry:
ret float %call
}
-define double @acos_f64(double %a) #0 {
+define double @acos_f64(double %a) {
; CHECK-LABEL: acos_f64
; CHECK: __xl_acos
; CHECK: blr
@@ -324,7 +324,7 @@ entry:
ret double %call
}
-define double @acosh_f64(double %a) #0 {
+define double @acosh_f64(double %a) {
; CHECK-LABEL: acosh_f64
; CHECK: __xl_acosh
; CHECK: blr
@@ -333,7 +333,7 @@ entry:
ret double %call
}
-define double @anint_f64(double %a) #0 {
+define double @anint_f64(double %a) {
; CHECK-LABEL: anint_f64
; CHECK-NOT: __xl_anint
; CHECK: blr
@@ -342,7 +342,7 @@ entry:
ret double %call
}
-define double @asin_f64(double %a) #0 {
+define double @asin_f64(double %a) {
; CHECK-LABEL: asin_f64
; CHECK: __xl_asin
; CHECK: blr
@@ -351,7 +351,7 @@ entry:
ret double %call
}
-define double @asinh_f64(double %a) #0 {
+define double @asinh_f64(double %a) {
; CHECK-LABEL: asinh_f64
; CHECK: __xl_asinh
; CHECK: blr
@@ -360,7 +360,7 @@ entry:
ret double %call
}
-define double @atan_f64(double %a) #0 {
+define double @atan_f64(double %a) {
; CHECK-LABEL: atan_f64
; CHECK: __xl_atan
; CHECK: blr
@@ -369,7 +369,7 @@ entry:
ret double %call
}
-define double @atan2_f64(double %a, double %b) #0 {
+define double @atan2_f64(double %a, double %b) {
; CHECK-LABEL: atan2_f64
; CHECK: __xl_atan2
; CHECK: blr
@@ -378,7 +378,7 @@ entry:
ret double %call
}
-define double @atanh_f64(double %a) #0 {
+define double @atanh_f64(double %a) {
; CHECK-LABEL: atanh_f64
; CHECK: __xl_atanh
; CHECK: blr
@@ -387,7 +387,7 @@ entry:
ret double %call
}
-define double @cbrt_f64(double %a) #0 {
+define double @cbrt_f64(double %a) {
; CHECK-LABEL: cbrt_f64
; CHECK: __xl_cbrt
; CHECK: blr
@@ -396,7 +396,7 @@ entry:
ret double %call
}
-define double @copysign_f64(double %a, double %b) #0 {
+define double @copysign_f64(double %a, double %b) {
; CHECK-LABEL: copysign_f64
; CHECK: copysign
; CHECK: blr
@@ -405,7 +405,7 @@ entry:
ret double %call
}
-define double @cos_f64(double %a) #0 {
+define double @cos_f64(double %a) {
; CHECK-LABEL: cos_f64
; CHECK: __xl_cos
; CHECK: blr
@@ -414,7 +414,7 @@ entry:
ret double %call
}
-define double @cosh_f64(double %a) #0 {
+define double @cosh_f64(double %a) {
; CHECK-LABEL: cosh_f64
; CHECK: __xl_cosh
; CHECK: blr
@@ -423,7 +423,7 @@ entry:
ret double %call
}
-define double @cosisin_f64(double %a) #0 {
+define double @cosisin_f64(double %a) {
; CHECK-LABEL: cosisin_f64
; CHECK-NOT: __xl_cosisin
; CHECK: blr
@@ -432,7 +432,7 @@ entry:
ret double %call
}
-define double @dnint_f64(double %a) #0 {
+define double @dnint_f64(double %a) {
; CHECK-LABEL: dnint_f64
; CHECK-NOT: __xl_dnint
; CHECK: blr
@@ -441,7 +441,7 @@ entry:
ret double %call
}
-define double @erf_f64(double %a) #0 {
+define double @erf_f64(double %a) {
; CHECK-LABEL: erf_f64
; CHECK: __xl_erf
; CHECK: blr
@@ -450,7 +450,7 @@ entry:
ret double %call
}
-define double @erfc_f64(double %a) #0 {
+define double @erfc_f64(double %a) {
; CHECK-LABEL: erfc_f64
; CHECK: __xl_erfc
; CHECK: blr
@@ -459,7 +459,7 @@ entry:
ret double %call
}
-define double @exp_f64(double %a) #0 {
+define double @exp_f64(double %a) {
; CHECK-LABEL: exp_f64
; CHECK: __xl_exp
; CHECK: blr
@@ -468,7 +468,7 @@ entry:
ret double %call
}
-define double @expm1_f64(double %a) #0 {
+define double @expm1_f64(double %a) {
; CHECK-LABEL: expm1_f64
; CHECK: __xl_expm1
; CHECK: blr
@@ -477,7 +477,7 @@ entry:
ret double %call
}
-define double @hypot_f64(double %a, double %b) #0 {
+define double @hypot_f64(double %a, double %b) {
; CHECK-LABEL: hypot_f64
; CHECK: __xl_hypot
; CHECK: blr
@@ -486,7 +486,7 @@ entry:
ret double %call
}
-define double @lgamma_f64(double %a) #0 {
+define double @lgamma_f64(double %a) {
; CHECK-LABEL: lgamma_f64
; CHECK: __xl_lgamma
; CHECK: blr
@@ -495,7 +495,7 @@ entry:
ret double %call
}
-define double @log_f64(double %a) #0 {
+define double @log_f64(double %a) {
; CHECK-LABEL: log_f64
; CHECK: __xl_log
; CHECK: blr
@@ -504,7 +504,7 @@ entry:
ret double %call
}
-define double @log10_f64(double %a) #0 {
+define double @log10_f64(double %a) {
; CHECK-LABEL: log10_f64
; CHECK: __xl_log10
; CHECK: blr
@@ -513,7 +513,7 @@ entry:
ret double %call
}
-define double @log1p_f64(double %a) #0 {
+define double @log1p_f64(double %a) {
; CHECK-LABEL: log1p_f64
; CHECK: __xl_log1p
; CHECK: blr
@@ -522,7 +522,7 @@ entry:
ret double %call
}
-define double @pow_f64(double %a, double %b) #0 {
+define double @pow_f64(double %a, double %b) {
; CHECK-LABEL: pow_f64
; CHECK: __xl_pow
; CHECK: blr
@@ -531,7 +531,7 @@ entry:
ret double %call
}
-define double @rsqrt_f64(double %a) #0 {
+define double @rsqrt_f64(double %a) {
; CHECK-LABEL: rsqrt_f64
; CHECK: __xl_rsqrt
; CHECK: blr
@@ -540,7 +540,7 @@ entry:
ret double %call
}
-define double @sin_f64(double %a) #0 {
+define double @sin_f64(double %a) {
; CHECK-LABEL: sin_f64
; CHECK: __xl_sin
; CHECK: blr
@@ -549,7 +549,7 @@ entry:
ret double %call
}
-define double @sincos_f64(double %a) #0 {
+define double @sincos_f64(double %a) {
; CHECK-LABEL: sincos_f64
; CHECK-NOT: __xl_sincos
; CHECK: blr
@@ -558,7 +558,7 @@ entry:
ret double %call
}
-define double @sinh_f64(double %a) #0 {
+define double @sinh_f64(double %a) {
; CHECK-LABEL: sinh_f64
; CHECK: __xl_sinh
; CHECK: blr
@@ -567,7 +567,7 @@ entry:
ret double %call
}
-define double @sqrt_f64(double %a) #0 {
+define double @sqrt_f64(double %a) {
; CHECK-LABEL: sqrt_f64
; CHECK: __xl_sqrt
; CHECK: blr
@@ -576,7 +576,7 @@ entry:
ret double %call
}
-define double @tan_f64(double %a) #0 {
+define double @tan_f64(double %a) {
; CHECK-LABEL: tan_f64
; CHECK: __xl_tan
; CHECK: blr
@@ -585,7 +585,7 @@ entry:
ret double %call
}
-define double @tanh_f64(double %a) #0 {
+define double @tanh_f64(double %a) {
; CHECK-LABEL: tanh_f64
; CHECK: __xl_tanh
; CHECK: blr
@@ -594,7 +594,7 @@ entry:
ret double %call
}
-define float @__acosf_finite_f32(float %a) #0 {
+define float @__acosf_finite_f32(float %a) {
; CHECK-LABEL: __acosf_finite_f32
; CHECK: __xl_acosf
; CHECK: blr
@@ -603,7 +603,7 @@ entry:
ret float %call
}
-define float @__acoshf_finite_f32(float %a) #0 {
+define float @__acoshf_finite_f32(float %a) {
; CHECK-LABEL: __acoshf_finite_f32
; CHECK: __xl_acoshf
; CHECK: blr
@@ -612,7 +612,7 @@ entry:
ret float %call
}
-define float @__asinf_finite_f32(float %a) #0 {
+define float @__asinf_finite_f32(float %a) {
; CHECK-LABEL: __asinf_finite_f32
; CHECK: __xl_asinf
; CHECK: blr
@@ -621,7 +621,7 @@ entry:
ret float %call
}
-define float @__atan2f_finite_f32(float %a, float %b) #0 {
+define float @__atan2f_finite_f32(float %a, float %b) {
; CHECK-LABEL: __atan2f_finite_f32
; CHECK: __xl_atan2f
; CHECK: blr
@@ -630,7 +630,7 @@ entry:
ret float %call
}
-define float @__atanhf_finite_f32(float %a) #0 {
+define float @__atanhf_finite_f32(float %a) {
; CHECK-LABEL: __atanhf_finite_f32
; CHECK: __xl_atanhf
; CHECK: blr
@@ -639,7 +639,7 @@ entry:
ret float %call
}
-define float @__coshf_finite_f32(float %a) #0 {
+define float @__coshf_finite_f32(float %a) {
; CHECK-LABEL: __coshf_finite_f32
; CHECK: __xl_coshf
; CHECK: blr
@@ -647,7 +647,7 @@ entry:
%call = tail call afn float @__coshf_finite(float %a)
ret float %call
}
-define float @__expf_finite_f32(float %a) #0 {
+define float @__expf_finite_f32(float %a) {
; CHECK-LABEL: __expf_finite_f32
; CHECK: __xl_expf
; CHECK: blr
@@ -655,7 +655,7 @@ entry:
%call = tail call afn float @__expf_finite(float %a)
ret float %call
}
-define float @__logf_finite_f32(float %a) #0 {
+define float @__logf_finite_f32(float %a) {
; CHECK-LABEL: __logf_finite_f32
; CHECK: __xl_logf
; CHECK: blr
@@ -663,7 +663,7 @@ entry:
%call = tail call afn float @__logf_finite(float %a)
ret float %call
}
-define float @__log10f_finite_f32(float %a) #0 {
+define float @__log10f_finite_f32(float %a) {
; CHECK-LABEL: __log10f_finite_f32
; CHECK: __xl_log10f
; CHECK: blr
@@ -671,7 +671,7 @@ entry:
%call = tail call afn float @__log10f_finite(float %a)
ret float %call
}
-define float @__powf_finite_f32(float %a, float %b) #0 {
+define float @__powf_finite_f32(float %a, float %b) {
; CHECK-LABEL: __powf_finite_f32
; CHECK: __xl_powf
; CHECK: blr
@@ -679,7 +679,7 @@ entry:
%call = tail call afn float @__powf_finite(float %a, float %b)
ret float %call
}
-define float @__sinhf_finite_f32(float %a) #0 {
+define float @__sinhf_finite_f32(float %a) {
; CHECK-LABEL: __sinhf_finite_f32
; CHECK: __xl_sinhf
; CHECK: blr
@@ -688,7 +688,7 @@ entry:
ret float %call
}
-define double @__acos_finite_f64(double %a) #0 {
+define double @__acos_finite_f64(double %a) {
; CHECK-LABEL: __acos_finite_f64
; CHECK: __xl_acos
; CHECK: blr
@@ -697,7 +697,7 @@ entry:
ret double %call
}
-define double @__acosh_finite_f64(double %a) #0 {
+define double @__acosh_finite_f64(double %a) {
; CHECK-LABEL: __acosh_finite_f64
; CHECK: __xl_acosh
; CHECK: blr
@@ -706,7 +706,7 @@ entry:
ret double %call
}
-define double @__asin_finite_f64(double %a) #0 {
+define double @__asin_finite_f64(double %a) {
; CHECK-LABEL: __asin_finite_f64
; CHECK: __xl_asin
; CHECK: blr
@@ -715,7 +715,7 @@ entry:
ret double %call
}
-define double @__atan2_finite_f64(double %a, double %b) #0 {
+define double @__atan2_finite_f64(double %a, double %b) {
; CHECK-LABEL: __atan2_finite_f64
; CHECK: __xl_atan2
; CHECK: blr
@@ -724,7 +724,7 @@ entry:
ret double %call
}
-define double @__atanh_finite_f64(double %a) #0 {
+define double @__atanh_finite_f64(double %a) {
; CHECK-LABEL: __atanh_finite_f64
; CHECK: __xl_atanh
; CHECK: blr
@@ -733,7 +733,7 @@ entry:
ret double %call
}
-define double @__cosh_finite_f64(double %a) #0 {
+define double @__cosh_finite_f64(double %a) {
; CHECK-LABEL: __cosh_finite_f64
; CHECK: __xl_cosh
; CHECK: blr
@@ -742,7 +742,7 @@ entry:
ret double %call
}
-define double @__exp_finite_f64(double %a) #0 {
+define double @__exp_finite_f64(double %a) {
; CHECK-LABEL: __exp_finite_f64
; CHECK: __xl_exp
; CHECK: blr
@@ -751,7 +751,7 @@ entry:
ret double %call
}
-define double @__log_finite_f64(double %a) #0 {
+define double @__log_finite_f64(double %a) {
; CHECK-LABEL: __log_finite_f64
; CHECK: __xl_log
; CHECK: blr
@@ -760,7 +760,7 @@ entry:
ret double %call
}
-define double @__log10_finite_f64(double %a) #0 {
+define double @__log10_finite_f64(double %a) {
; CHECK-LABEL: __log10_finite_f64
; CHECK: __xl_log10
; CHECK: blr
@@ -769,7 +769,7 @@ entry:
ret double %call
}
-define double @__pow_finite_f64(double %a, double %b) #0 {
+define double @__pow_finite_f64(double %a, double %b) {
; CHECK-LABEL: __pow_finite_f64
; CHECK: __xl_pow
; CHECK: blr
@@ -778,7 +778,7 @@ entry:
ret double %call
}
-define double @__sinh_finite_f64(double %a) #0 {
+define double @__sinh_finite_f64(double %a) {
; CHECK-LABEL: __sinh_finite_f64
; CHECK: __xl_sinh
; CHECK: blr
@@ -786,5 +786,3 @@ entry:
%call = tail call afn double @__sinh_finite(double %a)
ret double %call
}
-
-attributes #0 = { "approx-func-fp-math"="true" }
diff --git a/llvm/test/CodeGen/PowerPC/pow-025-075-intrinsic-scalar-mass-fast.ll b/llvm/test/CodeGen/PowerPC/pow-025-075-intrinsic-scalar-mass-fast.ll
index 58e228a5a0ccd..ff8c7ffa272d1 100644
--- a/llvm/test/CodeGen/PowerPC/pow-025-075-intrinsic-scalar-mass-fast.ll
+++ b/llvm/test/CodeGen/PowerPC/pow-025-075-intrinsic-scalar-mass-fast.ll
@@ -309,4 +309,4 @@ entry:
%call = tail call nnan ninf afn nsz double @llvm.pow.f64(double %a, double 5.000000e-01)
ret double %call
}
-attributes #1 = { "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "approx-func-fp-math"="true" }
+attributes #1 = { "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" }
diff --git a/llvm/test/CodeGen/PowerPC/pow-025-075-nointrinsic-scalar-mass-fast.ll b/llvm/test/CodeGen/PowerPC/pow-025-075-nointrinsic-scalar-mass-fast.ll
index c43bccc3f2398..3e0cdb03d3868 100644
--- a/llvm/test/CodeGen/PowerPC/pow-025-075-nointrinsic-scalar-mass-fast.ll
+++ b/llvm/test/CodeGen/PowerPC/pow-025-075-nointrinsic-scalar-mass-fast.ll
@@ -453,4 +453,4 @@ entry:
ret double %call
}
-attributes #1 = { "approx-func-fp-math"="true" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" }
+attributes #1 = { "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" }
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/StructuredBuffer.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/StructuredBuffer.ll
index ef2185af396c3..626f055859b90 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-resources/StructuredBuffer.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/StructuredBuffer.ll
@@ -74,7 +74,7 @@ declare ptr addrspace(11) @llvm.spv.resource.getpointer.p11.tspirv.VulkanBuffer_
declare ptr addrspace(11) @llvm.spv.resource.getpointer.p11.tspirv.VulkanBuffer_a0i32_12_0t(target("spirv.VulkanBuffer", [0 x i32], 12, 0), i32) #0
attributes #0 = { mustprogress nocallback nofree nosync nounwind willreturn memory(none) }
-attributes #1 = { mustprogress nofree noinline norecurse nosync nounwind willreturn memory(readwrite, inaccessiblemem: none) "approx-func-fp-math"="false" "frame-pointer"="all" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
+attributes #1 = { mustprogress nofree noinline norecurse nosync nounwind willreturn memory(readwrite, inaccessiblemem: none) "frame-pointer"="all" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
!llvm.module.flags = !{!0, !1}
!llvm.ident = !{!2}
diff --git a/llvm/test/CodeGen/SPIRV/hlsl-resources/spirv.layout.type.ll b/llvm/test/CodeGen/SPIRV/hlsl-resources/spirv.layout.type.ll
index f6677c9c2b1d9..ac538737018df 100644
--- a/llvm/test/CodeGen/SPIRV/hlsl-resources/spirv.layout.type.ll
+++ b/llvm/test/CodeGen/SPIRV/hlsl-resources/spirv.layout.type.ll
@@ -47,4 +47,4 @@ entry:
ret void
}
-attributes #1 = { mustprogress nofree noinline norecurse nosync nounwind willreturn memory(readwrite, argmem: write, inaccessiblemem: none) "approx-func-fp-math"="false" "frame-pointer"="all" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
+attributes #1 = { mustprogress nofree noinline norecurse nosync nounwind willreturn memory(readwrite, argmem: write, inaccessiblemem: none) "frame-pointer"="all" "hlsl.numthreads"="1,1,1" "hlsl.shader"="compute" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" }
diff --git a/llvm/test/Transforms/PhaseOrdering/AArch64/reduce_muladd.ll b/llvm/test/Transforms/PhaseOrdering/AArch64/reduce_muladd.ll
index ca78ff756ef55..27e8fd0ece55f 100644
--- a/llvm/test/Transforms/PhaseOrdering/AArch64/reduce_muladd.ll
+++ b/llvm/test/Transforms/PhaseOrdering/AArch64/reduce_muladd.ll
@@ -68,7 +68,7 @@ define dso_local nofpclass(nan inf) float @vmlaq(ptr noundef %0, ptr noundef %1)
declare void @llvm.lifetime.start.p0(ptr captures(none)) #1
declare void @llvm.lifetime.end.p0(ptr captures(none)) #1
-attributes #0 = { nounwind uwtable "approx-func-fp-math"="true" "frame-pointer"="non-leaf" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+fp-armv8,+neon,+v8a,-fmv" "unsafe-fp-math"="true" }
+attributes #0 = { nounwind uwtable "frame-pointer"="non-leaf" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+fp-armv8,+neon,+v8a,-fmv" "unsafe-fp-math"="true" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }
diff --git a/llvm/test/Transforms/PhaseOrdering/AArch64/reduce_submuladd.ll b/llvm/test/Transforms/PhaseOrdering/AArch64/reduce_submuladd.ll
index fb958b822503a..68bfbc1344f23 100644
--- a/llvm/test/Transforms/PhaseOrdering/AArch64/reduce_submuladd.ll
+++ b/llvm/test/Transforms/PhaseOrdering/AArch64/reduce_submuladd.ll
@@ -248,8 +248,8 @@ define internal noundef nofpclass(nan inf) float @_ZL6reduceILi7EEfPKfS1_ii(ptr
declare void @llvm.lifetime.start.p0(ptr captures(none)) #2
declare void @llvm.lifetime.end.p0(ptr captures(none)) #2
-attributes #0 = { mustprogress uwtable "approx-func-fp-math"="true" "frame-pointer"="non-leaf" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+fp-armv8,+neon,+v8a,-fmv" "unsafe-fp-math"="true" }
-attributes #1 = { inlinehint mustprogress nounwind uwtable "approx-func-fp-math"="true" "frame-pointer"="non-leaf" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+fp-armv8,+neon,+v8a,-fmv" "unsafe-fp-math"="true" }
+attributes #0 = { mustprogress uwtable "frame-pointer"="non-leaf" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+fp-armv8,+neon,+v8a,-fmv" "unsafe-fp-math"="true" }
+attributes #1 = { inlinehint mustprogress nounwind uwtable "frame-pointer"="non-leaf" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+fp-armv8,+neon,+v8a,-fmv" "unsafe-fp-math"="true" }
attributes #2 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #3 = { nounwind }
diff --git a/llvm/test/Transforms/PhaseOrdering/AArch64/slpordering.ll b/llvm/test/Transforms/PhaseOrdering/AArch64/slpordering.ll
index d19242fdd2e13..1fe3fde61f410 100644
--- a/llvm/test/Transforms/PhaseOrdering/AArch64/slpordering.ll
+++ b/llvm/test/Transforms/PhaseOrdering/AArch64/slpordering.ll
@@ -468,7 +468,7 @@ entry:
ret i32 %xor
}
-attributes #0 = { nounwind uwtable "approx-func-fp-math"="true" "frame-pointer"="non-leaf" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+fp-armv8,+neon,+v8a,-fmv" "unsafe-fp-math"="true" }
+attributes #0 = { nounwind uwtable "frame-pointer"="non-leaf" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+fp-armv8,+neon,+v8a,-fmv" "unsafe-fp-math"="true" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: readwrite) }
attributes #2 = { nounwind }
diff --git a/llvm/test/Transforms/PhaseOrdering/ARM/arm_mean_q7.ll b/llvm/test/Transforms/PhaseOrdering/ARM/arm_mean_q7.ll
index 6862d8b33faa1..435e6fccd620c 100644
--- a/llvm/test/Transforms/PhaseOrdering/ARM/arm_mean_q7.ll
+++ b/llvm/test/Transforms/PhaseOrdering/ARM/arm_mean_q7.ll
@@ -133,7 +133,7 @@ declare void @llvm.lifetime.start.p0(ptr nocapture) #1
declare i32 @llvm.arm.mve.addv.v16i8(<16 x i8>, i32) #2
declare void @llvm.lifetime.end.p0(ptr nocapture) #1
-attributes #0 = { nounwind "approx-func-fp-math"="true" "frame-pointer"="all" "min-legal-vector-width"="0" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-m55" "target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+ras,+strict-align,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp,-aes,-bf16,-cdecp0,-cdecp1,-cdecp2,-cdecp3,-cdecp4,-cdecp5,-cdecp6,-cdecp7,-crc,-crypto,-d32,-dotprod,-fp-armv8,-fp-armv8sp,-fp16fml,-hwdiv-arm,-i8mm,-neon,-pacbti,-sb,-sha2,-vfp3,-vfp3sp,-vfp4,-vfp4sp" "unsafe-fp-math"="true" }
+attributes #0 = { nounwind "frame-pointer"="all" "min-legal-vector-width"="0" "no-infs-fp-math"="true" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-m55" "target-features"="+armv8.1-m.main,+dsp,+fp-armv8d16,+fp-armv8d16sp,+fp16,+fp64,+fullfp16,+hwdiv,+lob,+mve,+mve.fp,+ras,+strict-align,+thumb-mode,+vfp2,+vfp2sp,+vfp3d16,+vfp3d16sp,+vfp4d16,+vfp4d16sp,-aes,-bf16,-cdecp0,-cdecp1,-cdecp2,-cdecp3,-cdecp4,-cdecp5,-cdecp6,-cdecp7,-crc,-crypto,-d32,-dotprod,-fp-armv8,-fp-armv8sp,-fp16fml,-hwdiv-arm,-i8mm,-neon,-pacbti,-sb,-sha2,-vfp3,-vfp3sp,-vfp4,-vfp4sp" "unsafe-fp-math"="true" }
attributes #1 = { argmemonly nocallback nofree nosync nounwind willreturn }
attributes #2 = { nounwind readnone }
attributes #3 = { nounwind }
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