[llvm] [RISCV] Compress shxadd to qc.c.muliadd when rd = rs2 (PR #155843)

[Sudharsan Veeravalli via llvm-commits]

https://github.com/svs-quic updated https://github.com/llvm/llvm-project/pull/155843

>From 8f146b20dccc48b40b6ad4bf0dbf0e85f8e5a25e Mon Sep 17 00:00:00 2001
From: Sudharsan Veeravalli <quic_svs at quicinc.com>
Date: Thu, 28 Aug 2025 19:47:09 +0530
Subject: [PATCH 1/2] [RISCV] Compress shxadd to qc.c.muliadd when rd = rs2

Do this when Zba and Xqciac are both enabled.
---
 llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td |  9 +++++++
 llvm/test/MC/RISCV/xqciac-valid.s           | 26 ++++++++++++++++-----
 2 files changed, 29 insertions(+), 6 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 2c64b0c220fba..5c267bf3c8afc 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -1743,6 +1743,15 @@ def : CompressPat<(QC_MULIADD GPRC:$rd, GPRC:$rs1, uimm5:$imm5),
                   (QC_C_MULIADD GPRC:$rd, GPRC:$rs1, uimm5:$imm5)>;
 }
 
+let Predicates = [HasVendorXqciac, HasStdExtZba, IsRV32] in {
+def : CompressPat<(SH1ADD GPRC:$rd, GPRC:$rs1, GPRC:$rd),
+                  (QC_C_MULIADD GPRC:$rd, GPRC:$rs1, 2)>;
+def : CompressPat<(SH2ADD GPRC:$rd, GPRC:$rs1, GPRC:$rd),
+                  (QC_C_MULIADD GPRC:$rd, GPRC:$rs1, 4)>;
+def : CompressPat<(SH3ADD GPRC:$rd, GPRC:$rs1, GPRC:$rd),
+                  (QC_C_MULIADD GPRC:$rd, GPRC:$rs1, 8)>;
+}
+
 let isCompressOnly = true, Predicates = [HasVendorXqcibi, IsRV32] in {
 def : CompressPat<(QC_E_BEQI GPRNoX0:$rs1, simm5nonzero:$imm5, bare_simm13_lsb0:$imm12),
                   (QC_BEQI GPRNoX0:$rs1, simm5nonzero:$imm5, bare_simm13_lsb0:$imm12)>;
diff --git a/llvm/test/MC/RISCV/xqciac-valid.s b/llvm/test/MC/RISCV/xqciac-valid.s
index 1afebc75cb45a..dd0848358c149 100644
--- a/llvm/test/MC/RISCV/xqciac-valid.s
+++ b/llvm/test/MC/RISCV/xqciac-valid.s
@@ -1,13 +1,13 @@
 # Xqciac - Qualcomm uC Load-Store Address Calculation Extension
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqciac -M no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqciac,+zba -M no-aliases -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-NOALIAS %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqciac < %s \
-# RUN:     | llvm-objdump --mattr=+experimental-xqciac -M no-aliases --no-print-imm-hex -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqciac,+zba < %s \
+# RUN:     | llvm-objdump --mattr=+experimental-xqciac,+zba -M no-aliases --no-print-imm-hex -d - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST %s
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqciac -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-xqciac,+zba -show-encoding \
 # RUN:     | FileCheck -check-prefixes=CHECK-ENC,CHECK-INST,CHECK-ALIAS %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqciac < %s \
-# RUN:     | llvm-objdump --mattr=+experimental-xqciac --no-print-imm-hex -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+experimental-xqciac,+zba < %s \
+# RUN:     | llvm-objdump --mattr=+experimental-xqciac,+zba --no-print-imm-hex -d - \
 # RUN:     | FileCheck -check-prefix=CHECK-INST %s
 
 # CHECK-NOALIAS: qc.c.muliadd    a0, a1, 0
@@ -58,3 +58,17 @@ qc.shladd x10, x11, x12, 31
 # CHECK-ENC: encoding: [0xaa,0x21]
 qc.muliadd x10, x11, 16
 
+# CHECK-NOALIAS: qc.c.muliadd    a0, a1, 2
+# CHECK-ALIAS: qc.muliadd    a0, a1, 2
+# CHECK-ENC: encoding: [0x8a,0x25]
+sh1add x10, x11, x10
+
+# CHECK-NOALIAS: qc.c.muliadd    a0, a1, 4
+# CHECK-ALIAS: qc.muliadd    a0, a1, 4
+# CHECK-ENC: encoding: [0x8a,0x29]
+sh2add x10, x11, x10
+
+# CHECK-NOALIAS: qc.c.muliadd    a0, a1, 8
+# CHECK-ALIAS: qc.muliadd    a0, a1, 8
+# CHECK-ENC: encoding: [0x8a,0x31]
+sh3add x10, x11, x10

>From a5ef71b2abeed5e463c9a1f74f2a1aa09d372c88 Mon Sep 17 00:00:00 2001
From: Sudharsan Veeravalli <quic_svs at quicinc.com>
Date: Fri, 29 Aug 2025 06:37:58 +0530
Subject: [PATCH 2/2] Add isCompressOnly, update test

---
 llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td | 2 +-
 llvm/test/CodeGen/RISCV/xqciac.ll           | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
index 5c267bf3c8afc..8fbcca6ad279a 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoXqci.td
@@ -1743,7 +1743,7 @@ def : CompressPat<(QC_MULIADD GPRC:$rd, GPRC:$rs1, uimm5:$imm5),
                   (QC_C_MULIADD GPRC:$rd, GPRC:$rs1, uimm5:$imm5)>;
 }
 
-let Predicates = [HasVendorXqciac, HasStdExtZba, IsRV32] in {
+let isCompressOnly = true, Predicates = [HasVendorXqciac, HasStdExtZba, IsRV32] in {
 def : CompressPat<(SH1ADD GPRC:$rd, GPRC:$rs1, GPRC:$rd),
                   (QC_C_MULIADD GPRC:$rd, GPRC:$rs1, 2)>;
 def : CompressPat<(SH2ADD GPRC:$rd, GPRC:$rs1, GPRC:$rd),
diff --git a/llvm/test/CodeGen/RISCV/xqciac.ll b/llvm/test/CodeGen/RISCV/xqciac.ll
index 934deb5a0c327..6d5e4a78af4f0 100644
--- a/llvm/test/CodeGen/RISCV/xqciac.ll
+++ b/llvm/test/CodeGen/RISCV/xqciac.ll
@@ -259,7 +259,7 @@ define dso_local i32 @shxadd(i32 %a, i32 %b) local_unnamed_addr #0 {
 ;
 ; RV32IZBAMXQCIAC-LABEL: shxadd:
 ; RV32IZBAMXQCIAC:       # %bb.0: # %entry
-; RV32IZBAMXQCIAC-NEXT:    sh1add a0, a1, a0
+; RV32IZBAMXQCIAC-NEXT:    qc.muliadd a0, a1, 2
 ; RV32IZBAMXQCIAC-NEXT:    ret
 entry:
   %mul = mul nsw i32 %b, 2